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[PATCH] RISC-V: Relax tail/j to c.j for RV64.
- From: Jim Wilson <jimw at sifive dot com>
- To: binutils at sourceware dot org
- Cc: Jim Wilson <jimw at sifive dot com>
- Date: Sat, 30 Mar 2019 10:13:16 -0700
- Subject: [PATCH] RISC-V: Relax tail/j to c.j for RV64.
This is a minor code size optimization to add a missing relaxation for the
4-byte tail/j instruction to the 2-byte c.j instruction. This triggers over
600K times during a riscv64-elf gcc C testsuite run, so it is definitely
useful.
This was tested with 32/64 elf/linux binutils builds and tests, and gcc
builds and tests. There were no regressions.
Committed.
Jim
2019-03-30 Andrew Waterman <andrew@sifive.com>
bfd/
* elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for
rd == X_RA case.
---
bfd/elfnn-riscv.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index bb114e59c7..dba1025994 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -3416,9 +3416,12 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
auipc = bfd_get_32 (abfd, contents + rel->r_offset);
jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4);
rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
- rvc = rvc && VALID_RVC_J_IMM (foff) && ARCH_SIZE == 32;
+ rvc = rvc && VALID_RVC_J_IMM (foff);
- if (rvc && (rd == 0 || rd == X_RA))
+ /* C.J exists on RV32 and RV64, but C.JAL is RV32-only. */
+ rvc = rvc && (rd == 0 || (rd == X_RA && ARCH_SIZE == 32));
+
+ if (rvc)
{
/* Relax to C.J[AL] rd, addr. */
r_type = R_RISCV_RVC_JUMP;
--
2.17.1