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[visium] Align branch absolute instruction for the GR6
- From: Eric Botcazou <ebotcazou at adacore dot com>
- To: binutils at sourceware dot org
- Date: Thu, 07 Feb 2019 17:14:55 +0100
- Subject: [visium] Align branch absolute instruction for the GR6
This is done in order to avoid a pipeline hazard on the GR6.
Tested for visium-elf, applied on mainline, 2.32 and 2.31 branches.
2019-02-07 Eric Botcazou <ebotcazou@adacore.com>
gas/
* config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on
64-bit boundaries for the GR6.
* testsuite/gas/visium/allinsn_gr6.s: Tweak.
* testsuite/gas/visium/allinsn_gr6.d: Likewise.
* testsuite/gas/visium/bra-1.d: New test.
* testsuite/gas/visium/bra-1.s: Likewise.
* testsuite/gas/visium/visium.exp: Run bra-1 test.
--
Eric Botcazou
diff --git a/gas/config/tc-visium.c b/gas/config/tc-visium.c
index 36a682c4085..bbd320e5edc 100644
--- a/gas/config/tc-visium.c
+++ b/gas/config/tc-visium.c
@@ -1368,6 +1368,10 @@ md_assemble (char *str0)
if (previous_mode == mode_cad || previous_mode == mode_ci)
as_bad ("branch instruction in delay slot");
+ /* For the GR6, BRA insns must be aligned on 64-bit boundaries. */
+ if (visium_arch == VISIUM_ARCH_GR6)
+ do_align (3, NULL, 0, 0);
+
this_dest = r3;
condition_code = cc;
break;
diff --git a/gas/testsuite/gas/visium/allinsn_gr6.d b/gas/testsuite/gas/visium/allinsn_gr6.d
index bb198eca8e5..c7f627bb34f 100644
--- a/gas/testsuite/gas/visium/allinsn_gr6.d
+++ b/gas/testsuite/gas/visium/allinsn_gr6.d
@@ -86,10 +86,10 @@ Disassembly of section .text:
120: 06 a5 1a 02 asr.w r6,r5,0
124: 86 a5 1a 12 asr.w r6,r5,1
128: 86 a7 23 f1 asr.b r8,r7,31
- 12c: 0f 89 28 04 bra eq,r9,r10
- 130: 07 a0 00 04 rflag r0
- 134: af 87 04 04 bra ne,r7,r1
- 138: 07 e0 ae 04 readmda r11
+ 12c: 07 a0 00 04 rflag r0
+ 130: 0f 89 28 04 bra eq,r9,r10
+ 134: 07 e0 ae 04 readmda r11
+ 138: af 87 04 04 bra ne,r7,r1
13c: 07 e0 b3 f4 eamread r12,31
140: 87 cd 30 04 extb.l r12,r13
144: 87 cf 38 02 extb.w r14,r15
@@ -130,8 +130,8 @@ Disassembly of section .text:
1d0: 84 a7 7f ff moviu r7,0x7FFF
1d4: 04 c6 00 01 moviq r6,1
1d8: 84 47 ff ff subi r7,65535
- 1dc: ff 86 00 04 bra tr,r6,r0
- 1e0: 86 00 00 04 add.l r0,r0,r0
+ 1dc: 86 00 00 04 add.l r0,r0,r0
+ 1e0: ff 86 00 04 bra tr,r6,r0
1e4: d3 e3 84 5c fpinst 10,f1,f3,f5
1e8: db e4 88 6c fpinst 11,f2,f4,f6
1ec: 7b ed ac fc fpinst 15,f11,f13,f15
diff --git a/gas/testsuite/gas/visium/allinsn_gr6.s b/gas/testsuite/gas/visium/allinsn_gr6.s
index 32953fbfb88..11006b836bc 100644
--- a/gas/testsuite/gas/visium/allinsn_gr6.s
+++ b/gas/testsuite/gas/visium/allinsn_gr6.s
@@ -93,11 +93,10 @@ sreg:
asr.w r6,r5,1
asr.b r8,r7,31
- bra eq,r9,r10
rflag r0
- bra ne,r7,r1
-
+ bra eq,r9,r10
eamread r11,0
+ bra ne,r7,r1
eamread r12,31
extb.l r12,r13
@@ -151,8 +150,8 @@ sreg:
moviq r6,1
subi r7,65535
- bra tr,r6,r0
add.l r0,r0,r0
+ bra tr,r6,r0
fpinst 10,f1,f3,f5
diff --git a/gas/testsuite/gas/visium/bra-1.d b/gas/testsuite/gas/visium/bra-1.d
new file mode 100644
index 00000000000..483b36bc8f4
--- /dev/null
+++ b/gas/testsuite/gas/visium/bra-1.d
@@ -0,0 +1,12 @@
+#as: -mtune=gr6
+#objdump: -d
+#name: bra-1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <foo>:
+ ...
+ 8: ff 95 54 04 bra tr,r21,r21
+ c: 00 00 00 00 nop
diff --git a/gas/testsuite/gas/visium/bra-1.s b/gas/testsuite/gas/visium/bra-1.s
new file mode 100644
index 00000000000..11544b887d2
--- /dev/null
+++ b/gas/testsuite/gas/visium/bra-1.s
@@ -0,0 +1,5 @@
+ .text
+foo:
+ nop
+ bra tr,r21,r21
+ nop
diff --git a/gas/testsuite/gas/visium/visium.exp b/gas/testsuite/gas/visium/visium.exp
index eabe1b0aa3b..4c1ac2c7e7a 100644
--- a/gas/testsuite/gas/visium/visium.exp
+++ b/gas/testsuite/gas/visium/visium.exp
@@ -24,6 +24,7 @@ if [istarget visium-*-*] {
run_dump_test "allinsn_def"
run_dump_test "allinsn_gr5"
run_dump_test "allinsn_gr6"
+ run_dump_test "bra-1"
run_dump_test "brr-1"
run_dump_test "brr-2"
run_dump_test "high-1"