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Re: [PATCH, BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension
- From: Sudakshina Das <Sudi dot Das at arm dot com>
- To: Richard Earnshaw <Richard dot Earnshaw at arm dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: "nickc at redhat dot com" <nickc at redhat dot com>, Ramana Radhakrishnan <Ramana dot Radhakrishnan at arm dot com>, nd <nd at arm dot com>
- Date: Thu, 8 Nov 2018 10:34:00 +0000
- Subject: Re: [PATCH, BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension
- References: <5d8925e5-edd0-96dc-28c6-b2a7d363fadc@arm.com> <1aa9d22b-2bc0-a17b-a704-0c2c6e356d5c@arm.com> <3d47ebd3-0c44-013b-7202-e51811f943e1@arm.com> <3102cf3b-7d5a-7d1c-046c-a9e926585713@arm.com>
Hi Richard
On 06/11/18 15:29, Richard Earnshaw (lists) wrote:
> On 02/11/2018 16:08, Sudakshina Das wrote:
>> Hi Richard
>>
>> On 30/10/18 09:39, Richard Earnshaw (lists) wrote:
>>> On 09/10/2018 18:23, Sudakshina Das wrote:
>>>> Hi
>>>>
>>>> This patch is part of the patch series to add support for ARMv8.5-A
>>>> Memory Tagging Extensions.
>>>> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>>>> Memory Tagging Extension (MTE) is an optional extension to
>>>> ARMv8.5-A and is enabled using the +memtag command line option.
>>>>
>>>> This patch add support to the Tag generation instructions from
>>>> MTE. These are the following instructions added in this patch:
>>>> - IRG <Xd|SP>, <Xn|SP>{, Xm}
>>>> - ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
>>>> - SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
>>>> - GMI <Xd>, <Xn|SP>, <Xm>
>>>>
>>>> where
>>>> <Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
>>>> <Xn|SP> : Is the 64-bit source GPR or Stack pointer.
>>>> <uimm1> : Is the unsigned immediate, a multiple of 16
>>>> in the range 0 to 1008.
>>>> <uimm2> : Is the unsigned immediate, in the range 0 to 15.
>>>>
>>>> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
>>>> Added test.
>>>>
>>>> Is this ok for trunk>>>
>>>> Thanks
>>>> Sudi
>>>>
>>>> *** include/ChangeLog ***
>>>>
>>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>>
>>>> * opcode/aarch64.h (aarch64_opnd): Add
>>>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
>>>>
>>>> *** opcodes/ChangeLog ***
>>>>
>>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>>
>>>> * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
>>>> (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
>>>> * aarch64-opc.c (fields): Add entry for imm4_3.
>>>> (operand_general_constraint_met_p): Add cases for
>>>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
>>>> (aarch64_print_operand): Likewise.
>>>> * aarch64-tbl.h (QL_ADDG): New.
>>>> (aarch64_opcode_table): Add addg, subg, irg and gmi.
>>>> (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
>>>> * aarch64-asm.c (aarch64_ins_imm): Add case for
>>>> operand_need_shift_by_four.
>>>> * aarch64-asm-2.c: Regenarated.
>>>> * aarch64-dis-2.c: Regenerated.
>>>> * aarch64-opc-2.c: Regenerated.
>>>>
>>>> *** gas/ChangeLog ***
>>>>
>>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>>
>>>> * config/tc-aarch64.c (parse_operands): Add switch case for
>>>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
>>>> * testsuite/gas/aarch64/armv8_5-a-mte.s: New.
>>>> * testsuite/gas/aarch64/armv8_5-a-mte.d: Likewise.
>>>>
>>>>
>>>>
>>>
>>> Urgh! We really need to get rid of those ridiculous autogenerated files
>>> from the source tree...
>>>
>>
>> Agreed, I will try to move these after I commit these.
>>
>>> Same issue as patch 1 re mte/memtag.
>>
>> Done
>>
>>>
>>> aarch64-opc.c:
>>> + case AARCH64_OPND_UIMM10:
>>> + /* Scaled unsigned 10 bits immediate offset. */
>>> + if (!value_in_range_p (opnd->imm.value, 0, 1008))
>>> + {
>>> + set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
>>> + return 0;
>>> + }
>>> + if (!value_aligned_p (opnd->imm.value, 16))
>>> + {
>>> +
>>>
>>> Blank line between independent if clauses.
>>
>> Done.
>>
>> Thanks you for test case suggestions. I have also updated the tests and
>> added a test for the illegal tests. The illegal testing has also
>> allowed me to fish out a couple of bugs.
>>
>> I have changed the general format of the positive tests to make it
>> better to read. All macros are moved on top and every instruction has
>> the following testing pattern:
>> 1) Base test with x0 and #0 depending on the instruction
>> 2) Macro call to add some random tests of different combinations.
>> 3) Special casing some SP register and immediate corner cases depending
>> on the instruction.
>>
>> All of these tests are cross referenced with a different disassembler to
>> make sure of the encodings. This applies to the tests of all the patches
>> that I am updating.
>>
>
> Thanks for the updates. I don't see, however, any tests for when SP is
> valid as an operand, or any tests for when Xzr should be accepted/rejected.
>
I have added xzr both for positive and negative tests
SP was already there, but I have further reduces the positive test cases
to not include too much macros and only test one field at a time as you
suggested offline.
I am attaching the new patches without the regenerated files and there
is no change to the changelog.
Thanks
Sudi
PS: This applies to all the tests in the patch series 2/8 - 6/8
> R.
>
>> *** include/ChangeLog ***
>>
>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>
>> * opcode/aarch64.h (aarch64_opnd): Add
>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
>>
>> *** opcodes/ChangeLog ***
>>
>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>
>> * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
>> (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
>> * aarch64-opc.c (fields): Add entry for imm4_3.
>> (operand_general_constraint_met_p): Add cases for
>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
>> (aarch64_print_operand): Likewise.
>> * aarch64-tbl.h (QL_ADDG): New.
>> (aarch64_opcode_table): Add addg, subg, irg and gmi.
>> (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
>> * aarch64-asm.c (aarch64_ins_imm): Add case for
>> operand_need_shift_by_four.
>> * aarch64-asm-2.c: Regenerated.
>> * aarch64-dis-2.c: Regenerated.
>> * aarch64-opc-2.c: Regenerated.
>>
>> *** gas/ChangeLog ***
>>
>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>
>> * config/tc-aarch64.c (parse_operands): Add switch case for
>> AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
>> * testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
>> * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
>> * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
>> * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
>> * testsuite/gas/aarch64/illegal-memtag.d: Likewise.
>>
>> Thanks
>> Sudi
>>
>>>
>>> Otherwise OK.
>>>
>>> R.
>>>
>>
>>
>>
>
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index b9aceb2f0f548d361a584f50ce6bb75058212980..5f79e92c04ad8fba38cbc4fdf2664bfd63e1b891 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5742,6 +5742,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SIMM5:
case AARCH64_OPND_FBITS:
case AARCH64_OPND_UIMM4:
+ case AARCH64_OPND_UIMM4_ADDG:
+ case AARCH64_OPND_UIMM10:
case AARCH64_OPND_UIMM3_OP1:
case AARCH64_OPND_UIMM3_OP2:
case AARCH64_OPND_IMM_VLSL:
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
new file mode 100644
index 0000000000000000000000000000000000000000..461046194822a0f836c179dac3965c404e30e45b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
@@ -0,0 +1,35 @@
+#as: -march=armv8.5-a+memtag
+# objdump: -d
+
+.*: .*
+
+
+Disassembly of section \.text:
+
+0+0 <func>:
+.*: 9ac01000 irg x0, x0, x0
+.*: 9ac0101b irg x27, x0, x0
+.*: 9ac01360 irg x0, x27, x0
+.*: 9adb1000 irg x0, x0, x27
+.*: 9adb137b irg x27, x27, x27
+.*: 9adf101f irg sp, x0
+.*: 9adf13e0 irg x0, sp
+.*: 9ac01400 gmi x0, x0, x0
+.*: 9ac0141b gmi x27, x0, x0
+.*: 9ac01760 gmi x0, x27, x0
+.*: 9adb1400 gmi x0, x0, x27
+.*: 9adb177b gmi x27, x27, x27
+.*: 9ac017e0 gmi x0, sp, x0
+.*: 9ac0141f gmi xzr, x0, x0
+.*: 91800000 addg x0, x0, #0x0, #0x0
+.*: 9180001b addg x27, x0, #0x0, #0x0
+.*: 91800360 addg x0, x27, #0x0, #0x0
+.*: 9180037b addg x27, x27, #0x0, #0x0
+.*: 91bf3fe0 addg x0, sp, #0x3f0, #0xf
+.*: 91aa3c1f addg sp, x0, #0x2a0, #0xf
+.*: d1800000 subg x0, x0, #0x0, #0x0
+.*: d180001b subg x27, x0, #0x0, #0x0
+.*: d1800360 subg x0, x27, #0x0, #0x0
+.*: d180037b subg x27, x27, #0x0, #0x0
+.*: d1bf3fe0 subg x0, sp, #0x3f0, #0xf
+.*: d1bf141f subg sp, x0, #0x3f0, #0x5
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
new file mode 100644
index 0000000000000000000000000000000000000000..96a3f3756ec813b9cb93ca705750b56b3d588459
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
@@ -0,0 +1,37 @@
+func:
+ # OP x[0,30], x[0,30], x[0,30]
+ .macro expand_3_reg op
+ \op x0, x0, x0
+ \op x27, x0, x0
+ \op x0, x27, x0
+ \op x0, x0, x27
+ \op x27, x27, x27
+ .endm
+
+ # OP x[0,30], x[0,30], #[0,30], #[0,14]
+ .macro expand_2_reg op
+ \op x0, x0, #0, #0
+ \op x27, x0, #0, #0
+ \op x0, x27, #0, #0
+ \op x27, x27, #0, #0
+ .endm
+
+ # IRG
+ expand_3_reg irg
+ irg sp, x0
+ irg x0, sp
+
+ # GMI
+ expand_3_reg gmi
+ gmi x0, sp, x0
+ gmi xzr, x0, x0
+
+ # ADDG
+ expand_2_reg addg
+ addg x0, sp, #0x3f0, #0xf
+ addg sp, x0, #0x2a0, #0xf
+
+ # SUBG
+ expand_2_reg subg
+ subg x0, sp, #0x3f0, #0xf
+ subg sp, x0, #0x3f0, #0x5
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.d b/gas/testsuite/gas/aarch64/illegal-memtag.d
new file mode 100644
index 0000000000000000000000000000000000000000..913661ab53f4318817df87104d7f2be33697b650
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.d
@@ -0,0 +1,3 @@
+#as: -march=armv8.5-a+memtag
+#source: illegal-memtag.s
+#error_output: illegal-memtag.l
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
new file mode 100644
index 0000000000000000000000000000000000000000..501faa76fc2057fb628d84757b3d6ddd40aafe75
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -0,0 +1,14 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `addg x1,x2,#0x3ef,#0x6'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1008 at operand 3 -- `subg x1,x2,#0x400,#0x3'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 1008 at operand 3 -- `subg x1,x2,-16,#0x3'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `addg x1,x2,#0x3f0,#0x10'
+[^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `subg x1,x2,#0x3f0,-4'
+[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
+[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
+[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
+[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `gmi x1,x2,sp'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `gmi sp,x2,x3'
+[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `gmi x1,xzr,x3'
+[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `addg xzr,x2,#0,#0'
+[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subg x1,xzr,#0,#0'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
new file mode 100644
index 0000000000000000000000000000000000000000..05f3ead5c94abb50c0717d27c11370ebd0ebc875
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
@@ -0,0 +1,19 @@
+func:
+ # ADDG/SUBG : Fail uimm6
+ addg x1, x2, #0x3ef, #0x6
+ subg x1, x2, #0x400, #0x3
+ subg x1, x2, -16, #0x3
+
+ # ADDG/SUBG : Fail uimm4
+ addg x1, x2, #0x3f0, #0x10
+ subg x1, x2, #0x3f0, -4
+
+ # Illegal SP/XZR registers
+ irg xzr, x2, x3
+ irg x1, xzr, x3
+ irg x1, x2, sp
+ gmi x1, x2, sp
+ gmi sp, x2, x3
+ gmi x1, xzr, x3
+ addg xzr, x2, #0, #0
+ subg x1, xzr, #0, #0
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 813c36a465951a5337276d9a5308d98eb01680e9..d6e639db9727273e0a6a4e17f54a1f0b99d08b74 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -246,7 +246,9 @@ enum aarch64_opnd
AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
+ AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
+ AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
AARCH64_OPND_BIT_NUM, /* Immediate. */
AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index b865d50d01ad8d1a5deb718289d6b3261b464f2d..fc7ac88f1a0ef35f21e27cbf248ee8e45643f597 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -381,6 +381,8 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
imm = info->imm.value;
if (operand_need_shift_by_two (self))
imm >>= 2;
+ if (operand_need_shift_by_four (self))
+ imm >>= 4;
insert_all_fields (self, code, imm);
return TRUE;
}
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 03851ca3e2d2068a84afaf6ec0322f2a8243d638..b37741a9aae8c383e94c47f210795a7643f93aa3 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -665,6 +665,8 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
if (operand_need_shift_by_two (self))
imm <<= 2;
+ else if (operand_need_shift_by_four (self))
+ imm <<= 4;
if (info->type == AARCH64_OPND_ADDR_ADRP)
imm <<= 12;
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 79227883d802455323692939dae6ce5c3a803143..3d1765ba95bbe000b12a3041668859ad3ead8d25 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -70,6 +70,7 @@ enum aarch64_field_kind
FLD_imm6_2,
FLD_imm4,
FLD_imm4_2,
+ FLD_imm4_3,
FLD_imm5,
FLD_imm7,
FLD_imm8,
@@ -199,6 +200,10 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
#define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
#define OPD_F_OD_LSB 5
#define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
+#define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
+ value by 4 to get the value
+ of an immediate operand. */
+
/* Register flags. */
@@ -253,6 +258,12 @@ operand_need_shift_by_two (const aarch64_operand *operand)
}
static inline bfd_boolean
+operand_need_shift_by_four (const aarch64_operand *operand)
+{
+ return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
+}
+
+static inline bfd_boolean
operand_maybe_stack_pointer (const aarch64_operand *operand)
{
return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 44d2ca66fab7cdb2f7e432e82634eddc31b499c3..d73542f2409786e3537458c5c78d3560594335a1 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -243,6 +243,7 @@ const aarch64_field fields[] =
{ 15, 6 }, /* imm6_2: in rmif instructions. */
{ 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
{ 0, 4 }, /* imm4_2: in rmif instructions. */
+ { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
{ 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
{ 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
{ 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
@@ -2091,6 +2092,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_CCMP_IMM:
case AARCH64_OPND_EXCEPTION:
case AARCH64_OPND_UIMM4:
+ case AARCH64_OPND_UIMM4_ADDG:
case AARCH64_OPND_UIMM7:
case AARCH64_OPND_UIMM3_OP1:
case AARCH64_OPND_UIMM3_OP2:
@@ -2108,6 +2110,21 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
}
break;
+ case AARCH64_OPND_UIMM10:
+ /* Scaled unsigned 10 bits immediate offset. */
+ if (!value_in_range_p (opnd->imm.value, 0, 1008))
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
+ return 0;
+ }
+
+ if (!value_aligned_p (opnd->imm.value, 16))
+ {
+ set_unaligned_error (mismatch_detail, idx, 16);
+ return 0;
+ }
+ break;
+
case AARCH64_OPND_SIMM5:
case AARCH64_OPND_SVE_SIMM5:
case AARCH64_OPND_SVE_SIMM5B:
@@ -3434,7 +3451,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_NZCV:
case AARCH64_OPND_EXCEPTION:
case AARCH64_OPND_UIMM4:
+ case AARCH64_OPND_UIMM4_ADDG:
case AARCH64_OPND_UIMM7:
+ case AARCH64_OPND_UIMM10:
if (optional_operand_p (opcode, idx) == TRUE
&& (opnd->imm.value ==
(int64_t) get_optional_operand_default_value (opcode)))
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5a4eaea4ecea9299686a7d712d24a05cfbc0334c..a599b931d7fea623910ac7f60d82df73e636a408 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -240,6 +240,12 @@
QLF4(X,X,imm_0_63,imm_0_63), \
}
+/* e.g. ADDG <Xd>, <Xn>, #<uimm10>, #<uimm4>. */
+#define QL_ADDG \
+{ \
+ QLF4(X,X,NIL,imm_0_15), \
+} \
+
/* e.g. BFC <Wd>, #<immr>, #<imms>. */
#define QL_BF1 \
{ \
@@ -2298,6 +2304,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
+ MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
+ MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
/* Add/subtract (shifted register). */
CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
@@ -3036,6 +3044,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS),
CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
+ MEMTAG_INSN ("irg", 0x9ac01000, 0xffe0fc00, dp_2src, OP3 (Rd_SP, Rn_SP, Rm), QL_I3SAMEX, F_OPD2_OPT | F_DEFAULT (0x1f)),
+ MEMTAG_INSN ("gmi", 0x9ac01400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm), QL_I3SAMEX, 0),
V8_3_INSN ("pacga", 0x9ac03000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm_SP), QL_I3SAMEX, 0),
/* CRC instructions. */
_CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0),
@@ -4559,8 +4569,12 @@ struct aarch64_opcode aarch64_opcode_table[] =
"a 3-bit unsigned immediate") \
Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \
"a 4-bit unsigned immediate") \
+ Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD_imm4_3), \
+ "a 4-bit unsigned Logical Address Tag modifier") \
Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \
"a 7-bit unsigned immediate") \
+ Y(IMMEDIATE, imm, "UIMM10", OPD_F_SHIFT_BY_4, F(FLD_immr), \
+ "a 10-bit unsigned multiple of 16") \
Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \
"the bit number to be tested") \
Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \