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Re: [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers

From: "Richard Earnshaw (lists)" <Richard dot Earnshaw at arm dot com>
To: Sudakshina Das <sudi dot das at arm dot com>, Jan Beulich <JBeulich at suse dot com>
Cc: nd at arm dot com, ramana dot radhakrishnan at arm dot com, Nick Clifton <nickc at redhat dot com>, binutils at sourceware dot org
Date: Tue, 9 Oct 2018 15:44:08 +0100
Subject: Re: [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers
References: <3deae8b5-ceeb-c41c-8b79-aea32205a4ba@arm.com> <5BA77AF4020000780013E0E5@prv1-mh.provo.novell.com> <9846cceb-6acd-391a-c4ad-44b28ec25c49@arm.com> <5BA9E33502000078001EB6E1@prv1-mh.provo.novell.com> <354d551e-46ef-b093-d05e-4acbf45626a5@arm.com>

On 26/09/18 11:17, Sudakshina Das wrote:
> Hi Jan
> 
> On 25/09/18 08:26, Jan Beulich wrote:
>>>>> On 24.09.18 at 19:20, <sudi.das@arm.com> wrote:
>>> On 23/09/18 12:37, Jan Beulich wrote:
>>>>>>> Sudakshina Das <sudi.das@arm.com> 09/19/18 4:30 PM >>>
>>>>> --- a/opcodes/aarch64-opc.c
>>>>> +++ b/opcodes/aarch64-opc.c
>>>>> @@ -3714,6 +3714,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
>>>>> { "id_dfr0_el1",      CPENC(3,0,C0,C1,2),    F_REG_READ }, /* RO */
>>>>> { "id_pfr0_el1",      CPENC(3,0,C0,C1,0),    F_REG_READ }, /* RO */
>>>>> { "id_pfr1_el1",      CPENC(3,0,C0,C1,1),    F_REG_READ }, /* RO */
>>>>> +  { "id_pfr2_el1",      CPENC(3,0,C0,C3,4),    F_ARCHEXT },
>>>>
>>>> Judging by the neighboring ones - isn't this new one supposed to have
>>> F_REG_READ set?
>>>
>>> Ah yes. Thanks for noticing. I will send out a modified patch soon.
>>
>> Btw, I've also been wondering about the random number registers,
>> which look to support reads only as well.
>>
>> Jan
> 
> Attaching the new version with updated flags. The Changelog still
> applies from before. Random number register patch coming up.
> 
> Thanks
> Sudi
> 
>>
>>

Committed.

R.

> 
> 
> rb9970.patch
> 
> 
> diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
> index 2e0851c6855b82cdcf7fcd7b803eb102705d99d5..35c3ceae37be549015b1561da275a2cde3ea2caa 100644
> --- a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
> +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
> @@ -8,3 +8,9 @@
>  [^:]*:[0-9]+: Error: selected processor does not support system register name 'cvadp'
>  [^:]*:[0-9]+: Error: selected processor does not support system register name 'rndr'
>  [^:]*:[0-9]+: Error: selected processor does not support system register name 'rndrrs'
> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el0'
> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el1'
> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el2'
> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el3'
> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el12'
> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'id_pfr2_el1'
> diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d
> index 3ce7501908003bc6d0d6fe61f7f95aa3f227d53c..c24a2326c34a9ad672909c64ac1aff92136b1f05 100644
> --- a/gas/testsuite/gas/aarch64/sysreg-4.d
> +++ b/gas/testsuite/gas/aarch64/sysreg-4.d
> @@ -13,3 +13,9 @@ Disassembly of section \.text:
>  .*:	d50b7d24 	dc	cvadp, x4
>  .*:	d53b2405 	mrs	x5, rndr
>  .*:	d53b2426 	mrs	x6, rndrrs
> +.*:	d53bd0e7 	mrs	x7, scxtnum_el0
> +.*:	d538d0e7 	mrs	x7, scxtnum_el1
> +.*:	d53cd0e7 	mrs	x7, scxtnum_el2
> +.*:	d53ed0e7 	mrs	x7, scxtnum_el3
> +.*:	d53dd0e7 	mrs	x7, scxtnum_el12
> +.*:	d5380388 	mrs	x8, id_pfr2_el1
> diff --git a/gas/testsuite/gas/aarch64/sysreg-4.s b/gas/testsuite/gas/aarch64/sysreg-4.s
> index 30decbd843b3017f2b8aef1159405fcbcbbc2c0b..b8f40d478a19773d7b74bb87f6b001fe5b663c43 100644
> --- a/gas/testsuite/gas/aarch64/sysreg-4.s
> +++ b/gas/testsuite/gas/aarch64/sysreg-4.s
> @@ -6,3 +6,9 @@ func:
>  	dc cvadp, x4
>  	mrs x5, rndr
>  	mrs x6, rndrrs
> +	mrs x7, scxtnum_el0
> +	mrs x7, scxtnum_el1
> +	mrs x7, scxtnum_el2
> +	mrs x7, scxtnum_el3
> +	mrs x7, scxtnum_el12
> +	mrs x8, id_pfr2_el1
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index 07a91f256d9ecd45b176d26ee913524b63f7463d..877a9284b6e37d581e5fcb456648c3644a7501ed 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -78,6 +78,11 @@ typedef uint32_t aarch64_insn;
>  #define AARCH64_FEATURE_RNG		0x80000000000ULL
>  /* BTI instructions.  */
>  #define AARCH64_FEATURE_BTI		0x100000000000ULL
> +/* SCXTNUM_ELx.  */
> +#define AARCH64_FEATURE_SCXTNUM		0x200000000000ULL
> +/* ID_PFR2 instructions.  */
> +#define AARCH64_FEATURE_ID_PFR2		0x400000000000ULL
> +
>  
>  /* Architectures are the sum of the base and extensions.  */
>  #define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \
> @@ -108,7 +113,9 @@ typedef uint32_t aarch64_insn;
>  						 | AARCH64_FEATURE_SB   \
>  						 | AARCH64_FEATURE_PREDRES \
>  						 | AARCH64_FEATURE_CVADP \
> -						 | AARCH64_FEATURE_BTI)
> +						 | AARCH64_FEATURE_BTI	\
> +						 | AARCH64_FEATURE_SCXTNUM \
> +						 | AARCH64_FEATURE_ID_PFR2)
>  
>  
>  #define AARCH64_ARCH_NONE	AARCH64_FEATURE (0, 0)
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index e6f8339a1e35a0e66213ec50d7b5ea20a106db1b..a2640399f6e94d1c5e92375bf232d9996cfedf48 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -3714,6 +3714,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
>    { "id_dfr0_el1",      CPENC(3,0,C0,C1,2),	F_REG_READ }, /* RO */
>    { "id_pfr0_el1",      CPENC(3,0,C0,C1,0),	F_REG_READ }, /* RO */
>    { "id_pfr1_el1",      CPENC(3,0,C0,C1,1),	F_REG_READ }, /* RO */
> +  { "id_pfr2_el1",      CPENC(3,0,C0,C3,4),	F_ARCHEXT | F_REG_READ}, /* RO */
>    { "id_afr0_el1",      CPENC(3,0,C0,C1,3),	F_REG_READ }, /* RO */
>    { "id_mmfr0_el1",     CPENC(3,0,C0,C1,4),	F_REG_READ }, /* RO */
>    { "id_mmfr1_el1",     CPENC(3,0,C0,C1,5),	F_REG_READ }, /* RO */
> @@ -3850,6 +3851,11 @@ const aarch64_sys_reg aarch64_sys_regs [] =
>    { "tpidr_el1",        CPENC(3,0,C13,C0,4),	0 },
>    { "tpidr_el2",        CPENC(3,4,C13,C0,2),	0 },
>    { "tpidr_el3",        CPENC(3,6,C13,C0,2),	0 },
> +  { "scxtnum_el0",      CPENC(3,3,C13,C0,7), F_ARCHEXT },
> +  { "scxtnum_el1",      CPENC(3,0,C13,C0,7), F_ARCHEXT },
> +  { "scxtnum_el2",      CPENC(3,4,C13,C0,7), F_ARCHEXT },
> +  { "scxtnum_el12",     CPENC(3,5,C13,C0,7), F_ARCHEXT },
> +  { "scxtnum_el3",      CPENC(3,6,C13,C0,7), F_ARCHEXT },
>    { "teecr32_el1",      CPENC(2,2,C0, C0,0),	0 }, /* See section 3.9.7.1 */
>    { "cntfrq_el0",       CPENC(3,3,C14,C0,0),	0 }, /* RW */
>    { "cntpct_el0",       CPENC(3,3,C14,C0,1),	F_REG_READ }, /* RO */
> @@ -4089,6 +4095,20 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
>        && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
>      return FALSE;
>  
> +  /* SCXTNUM_ELx registers.  */
> +  if ((reg->value == CPENC (3, 3, C13, C0, 7)
> +       || reg->value == CPENC (3, 0, C13, C0, 7)
> +       || reg->value == CPENC (3, 4, C13, C0, 7)
> +       || reg->value == CPENC (3, 6, C13, C0, 7)
> +       || reg->value == CPENC (3, 5, C13, C0, 7))
> +      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
> +      return FALSE;
> +
> +  /* ID_PFR2_EL1 register.  */
> +  if (reg->value == CPENC(3, 0, C0, C3, 4)
> +      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
> +    return FALSE;
> +
>    /* Virtualization host extensions: system registers.  */
>    if ((reg->value == CPENC (3, 4, C2, C0, 1)
>         || reg->value == CPENC (3, 4, C13, C0, 1)
>

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