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Re: [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction
- From: "Richard Earnshaw (lists)" <Richard dot Earnshaw at arm dot com>
- To: Sudakshina Das <sudi dot das at arm dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: nd <nd at arm dot com>, Ramana Radhakrishnan <Ramana dot Radhakrishnan at arm dot com>, Nick Clifton <nickc at redhat dot com>
- Date: Tue, 9 Oct 2018 15:42:51 +0100
- Subject: Re: [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction
- References: <f99347e6-6fc8-ca2b-59dd-efcb0c5cbe73@arm.com>
On 19/09/18 15:23, Sudakshina Das wrote:
> Hi
>
> This patch is part of the patch series to add support for ARMv8.5-A
> extensions.
> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys)
>
>
> This patch adds the DC CVADP instruction. Since this has a separate
> identification mechanism a new feature bit is added.
>
> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
> and aarch64-none-elf. Added new test.
>
> Ok for trunk?
>
> Thanks
> Sudi
> PS. I do not have commit access so if OK can someone apply for me?
>
> *** include/ChangeLog ***
>
> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
>
> *** opcodes/ChangeLog ***
>
> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
> (aarch64_sys_ins_reg_supported_p): New check for above.
>
> *** gas/ChangeLog ***
>
> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * testsuite/gas/aarch64/sysreg-4.s: Test instruction.
> * testsuite/gas/aarch64/sysreg-4.d: Likewise.
> * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
>
>
Committed.
R.
>
> rb9966.patch
>
>
> diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
> index 68471a17bd096931674efb2a40fd04980d60617e..f3167e3824f7d21a62e783146251dc5d9673b0cb 100644
> --- a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
> +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
> @@ -5,3 +5,4 @@
> [^:]*:[0-9]+: Error: selected processor does not support `dvp rctx,x2'
> [^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
> [^:]*:[0-9]+: Error: selected processor does not support `cpp rctx,x3'
> +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cvadp'
> diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d
> index f3ea5d1b96a5be47d73d66a02883429a946813ef..1c14016beac9cca24e90e3139f3db950416e785f 100644
> --- a/gas/testsuite/gas/aarch64/sysreg-4.d
> +++ b/gas/testsuite/gas/aarch64/sysreg-4.d
> @@ -10,3 +10,4 @@ Disassembly of section \.text:
> .*: d50b7381 cfp rctx, x1
> .*: d50b73a2 dvp rctx, x2
> .*: d50b73e3 cpp rctx, x3
> +.*: d50b7d24 dc cvadp, x4
> diff --git a/gas/testsuite/gas/aarch64/sysreg-4.s b/gas/testsuite/gas/aarch64/sysreg-4.s
> index 6ec069ac957e0d1fa094f641633b49d74b673907..49907c0b22e8a0eb9dae0fc9c4ba5adfdd232074 100644
> --- a/gas/testsuite/gas/aarch64/sysreg-4.s
> +++ b/gas/testsuite/gas/aarch64/sysreg-4.s
> @@ -3,3 +3,4 @@ func:
> cfp rctx, x1
> dvp rctx, x2
> cpp rctx, x3
> + dc cvadp, x4
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index 22625b7376e54975f3f04fd371872c21e4dab255..f364771ea2f03f419f2b90c5ce703b6a172ee7bf 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -72,6 +72,8 @@ typedef uint32_t aarch64_insn;
> #define AARCH64_FEATURE_SB 0x10000000000ULL
> /* Execution and Data Prediction Restriction instructions. */
> #define AARCH64_FEATURE_PREDRES 0x20000000000ULL
> +/* DC CVADP. */
> +#define AARCH64_FEATURE_CVADP 0x40000000000ULL
>
> /* Architectures are the sum of the base and extensions. */
> #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
> @@ -100,7 +102,8 @@ typedef uint32_t aarch64_insn;
> | AARCH64_FEATURE_FLAGMANIP \
> | AARCH64_FEATURE_FRINTTS \
> | AARCH64_FEATURE_SB \
> - | AARCH64_FEATURE_PREDRES)
> + | AARCH64_FEATURE_PREDRES \
> + | AARCH64_FEATURE_CVADP)
>
>
> #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index db3c16d7694fbb9c445c43b09a2734bad1e22ee6..b47f0ca50526fa4a574fc0954ddf24ab740c42d1 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -4330,6 +4330,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
> { "csw", CPENS (0, C7, C10, 2), F_HASXT },
> { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
> { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
> + { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
> { "civac", CPENS (3, C7, C14, 1), F_HASXT },
> { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
> { 0, CPENS(0,0,0,0), 0 }
> @@ -4465,6 +4466,11 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
> && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
> return FALSE;
>
> + /* DC CVADP. Values are from aarch64_sys_regs_dc. */
> + if (reg->value == CPENS (3, C7, C13, 1)
> + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
> + return FALSE;
> +
> /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
> if ((reg->value == CPENS (0, C7, C9, 0)
> || reg->value == CPENS (0, C7, C9, 1))
>
>