This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
Re: [PATCH, BINUTILS, ARM, 3/3] Add Execution and Data Prediction instructions for AArch32
- From: "Richard Earnshaw (lists)" <Richard dot Earnshaw at arm dot com>
- To: Sudakshina Das <Sudi dot Das at arm dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: nd <nd at arm dot com>, Ramana Radhakrishnan <Ramana dot Radhakrishnan at arm dot com>, "nickc at redhat dot com" <nickc at redhat dot com>
- Date: Fri, 5 Oct 2018 11:33:23 +0100
- Subject: Re: [PATCH, BINUTILS, ARM, 3/3] Add Execution and Data Prediction instructions for AArch32
- References: <96f9b1e1-2c60-8e60-4c62-724275cae0df@arm.com> <5ebf171b-1d57-787c-41d8-6957acdbc4c4@arm.com> <b7f452ad-5c01-1ddf-3a05-ff518a39333f@arm.com> <81c23280-9767-f94b-0575-6957768b1c7a@arm.com> <4ced24c7-2ef1-902e-f74d-0864c64070c8@arm.com>
On 04/10/18 14:34, Sudakshina Das wrote:
> Hi
>
> On 28/09/18 18:47, Sudakshina Das wrote:
>> Hi Richard
>>
>> On 24/09/18 17:15, Sudakshina Das wrote:
>>> Hi Richard
>>>
>>> On 20/09/18 14:15, Richard Earnshaw (lists) wrote:
>>>> On 19/09/18 15:36, Sudakshina Das wrote:
>>>>> Hi
>>>>>
>>>>> This patch is part of the patch series to add support for ARMv8.5-A
>>>>> extensions.
>>>>> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>>>>>
>>>>>
>>>>>
>>>>> This patch adds the Execution and Data Prediction Restriction
>>>>> instructions (that is, cfprctx, dvprxtc, cpprctx). These are all
>>>>> aliases
>>>>> to MCR and are disassembled as such.
>>>>>
>>>>> This instruction is retrospectively made optional for all versions of
>>>>> the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5.
>>>>> Hence adding a new +predres for older versions of the architecture.
>>>>>
>>>>> Testing done: Builds and reg tests all pass on arm-none-eabi.
>>>>> Added new tests.
>>>>>
>>>>> Ok for trunk?
>>>>>
>>>>
>>>> This has the same problem as the previous patch, the constant is too
>>>> large for the storage on a 32-bit host. Also, please keep the #defines
>>>> grouped and sorted in order, so that we know which bits have been used.
>>>>
>>>> R.
>>>>
>>>
>>> Sorry about the overlook, I missed out on the macro values completely.
>>> The list of the extensions, where I added these two are oddly going in a
>>> descending order (with an exception of FPU_ENDIAN_BIG). I guess I should
>>> add them at the bottom with the next lowest values. I will send the
>>> edited patches soon.
>>>
>>> Thanks
>>> Sudi
>>>
>>
>> Please find the updated patch attached.
>>
>> *** include/ChangeLog ***
>>
>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>
>> * opcode/arm.h (ARM_EXT2_PREDRES): New.
>> (ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default.
>>
>> *** gas/ChangeLog ***
>>
>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>
>> * config/tc-arm.c (predres_ext_armv8): New.
>> (insns): Add new cfprctx, dvprctx and cpprctx instructions.
>> (arm_extensions): Add "predres".
>> * doc/c-arm.texi: Document the above.
>> * testsuite/gas/arm/predres-bad.d: New test.
>> * testsuite/gas/arm/predres-bad.l: New test.
>> * testsuite/gas/arm/predres.s: New test.
>> * testsuite/gas/arm/predres1.d: New test.
>> * testsuite/gas/arm/predres2.d: New test.
>>
>> Thanks
>> Sudi
>>
>
> Please find the new patch attached:
>
> *** include/ChangeLog ***
>
> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * opcode/arm.h (ARM_EXT2_PREDRES): New.
> (ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default.
>
> *** gas/ChangeLog ***
>
> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>
> * config/tc-arm.c (arm_ext_predres): New.
> (insns): Add new cfprctx, dvprctx and cpprctx instructions.
> (arm_extensions): Add "predres".
> * doc/c-arm.texi: Document the above.
> * testsuite/gas/arm/predres-bad.d: New test.
> * testsuite/gas/arm/predres-bad.l: New test.
> * testsuite/gas/arm/predres.s: New test.
> * testsuite/gas/arm/predres1.d: New test.
> * testsuite/gas/arm/predres2.d: New test.
>
> Thanks
> Sudi
>
Applied.
Thanks,
R.
>>>
>>>>> Thanks
>>>>> Sudi
>>>>> PS. I do not have commit access so if OK can someone apply for me?
>>>>>
>>>>> *** include/ChangeLog ***
>>>>>
>>>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>>>
>>>>> * opcode/arm.h (PREDRES_EXT_ARMV8): New.
>>>>> (ARM_ARCH_V8_5A): Add PREDRES_EXT_ARMV8 by default.
>>>>>
>>>>> *** gas/ChangeLog ***
>>>>>
>>>>> 2018-xx-xx Sudakshina Das <sudi.das@arm.com>
>>>>>
>>>>> * config/tc-arm.c (predres_ext_armv8): New.
>>>>> (insns): Add new cfprctx, dvprctx and cpprctx instructions.
>>>>> (arm_extensions): Add "predres".
>>>>> * doc/c-arm.texi: Document the above.
>>>>> * testsuite/gas/arm/predres-bad.d: New test.
>>>>> * testsuite/gas/arm/predres-bad.l: New test.
>>>>> * testsuite/gas/arm/predres.s: New test.
>>>>> * testsuite/gas/arm/predres1.d: New test.
>>>>> * testsuite/gas/arm/predres2.d: New test.
>>>>>
>>>>>
>>>>>
>>>>> rb9985.patch
>>>>>
>>>>>
>>>>> diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
>>>>> index
>>>>> e4c7dcb56a28ad7663d3b19a9b76e43d94fbe6a8..f1e46f99182fa3300cdcf8c86588cd72fc03f586
>>>>> 100644
>>>>> --- a/gas/config/tc-arm.c
>>>>> +++ b/gas/config/tc-arm.c
>>>>> @@ -317,6 +317,8 @@ static const arm_feature_set fpu_neon_ext_dotprod =
>>>>> ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
>>>>> static const arm_feature_set sb_ext_armv8 =
>>>>> ARM_FEATURE_COPROC (SB_EXT_ARMV8);
>>>>> +static const arm_feature_set predres_ext_armv8 =
>>>>> + ARM_FEATURE_COPROC (PREDRES_EXT_ARMV8);
>>>>> static int mfloat_abi_opt = -1;
>>>>> /* Architecture feature bits selected by the last -mcpu/-march or
>>>>> .cpu/.arch
>>>>> @@ -21525,6 +21527,14 @@ static const struct asm_opcode insns[] =
>>>>> #define THUMB_VARIANT & sb_ext_armv8
>>>>> TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
>>>>> +#undef ARM_VARIANT
>>>>> +#define ARM_VARIANT & predres_ext_armv8
>>>>> +#undef THUMB_VARIANT
>>>>> +#define THUMB_VARIANT & predres_ext_armv8
>>>>> + CE("cfprctx", e070f93, 1, (RRnpc), rd),
>>>>> + CE("dvprctx", e070fb3, 1, (RRnpc), rd),
>>>>> + CE("cpprctx", e070ff3, 1, (RRnpc), rd),
>>>>> +
>>>>> /* ARMv8-M instructions. */
>>>>> #undef ARM_VARIANT
>>>>> #define ARM_VARIANT NULL
>>>>> @@ -26421,6 +26431,9 @@ static const struct
>>>>> arm_option_extension_value_table arm_extensions[] =
>>>>> ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
>>>>> ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
>>>>> ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
>>>>> + ARM_EXT_OPT ("predres", ARM_FEATURE_COPROC (PREDRES_EXT_ARMV8),
>>>>> + ARM_FEATURE_COPROC (PREDRES_EXT_ARMV8),
>>>>> + ARM_ARCH_V8A),
>>>>> ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
>>>>> ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
>>>>> ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
>>>>> diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
>>>>> index
>>>>> b9910dab6118af0828d1d812ccead0aef5b8eb9e..5dbb5bdf2f0122324988673ba9620bd56b37e3f4
>>>>> 100644
>>>>> --- a/gas/doc/c-arm.texi
>>>>> +++ b/gas/doc/c-arm.texi
>>>>> @@ -189,6 +189,8 @@ The following extensions are currently supported:
>>>>> @code{mp} (Multiprocessing Extensions for v7-A and v7-R
>>>>> architectures),
>>>>> @code{os} (Operating System for v6M architecture),
>>>>> +@code{predres} (Execution and Data Prediction Restriction
>>>>> Instruction for
>>>>> +v8-A archtectures, added by default from v8.5-A),
>>>>> @code{sb} (Speculation Barrier Instruction for v8-A archtectures,
>>>>> added by
>>>>> default from v8.5-A),
>>>>> @code{sec} (Security Extensions for v6K and v7-A architectures),
>>>>> diff --git a/gas/testsuite/gas/arm/predres-bad.d
>>>>> b/gas/testsuite/gas/arm/predres-bad.d
>>>>> new file mode 100644
>>>>> index
>>>>> 0000000000000000000000000000000000000000..7fc8ca077799da0a8ddd3ab21f87ac2a4eee9eb3
>>>>>
>>>>> --- /dev/null
>>>>> +++ b/gas/testsuite/gas/arm/predres-bad.d
>>>>> @@ -0,0 +1,4 @@
>>>>> +#name: Error for Prediction Restriction instructions without +predres
>>>>> +#source: predres.s
>>>>> +#as: -march=armv8-a
>>>>> +#error-output: predres-bad.l
>>>>> diff --git a/gas/testsuite/gas/arm/predres-bad.l
>>>>> b/gas/testsuite/gas/arm/predres-bad.l
>>>>> new file mode 100644
>>>>> index
>>>>> 0000000000000000000000000000000000000000..3f7efc62b069d678dcfeb48f6e93be7c328c16de
>>>>>
>>>>> --- /dev/null
>>>>> +++ b/gas/testsuite/gas/arm/predres-bad.l
>>>>> @@ -0,0 +1,4 @@
>>>>> +[^:]*: Assembler messages:
>>>>> +[^:]*:4: Error: selected processor does not support `cfprctx r1' in
>>>>> ARM mode
>>>>> +[^:]*:5: Error: selected processor does not support `dvprctx r2' in
>>>>> ARM mode
>>>>> +[^:]*:6: Error: selected processor does not support `cpprctx r3' in
>>>>> ARM mode
>>>>> diff --git a/gas/testsuite/gas/arm/predres.s
>>>>> b/gas/testsuite/gas/arm/predres.s
>>>>> new file mode 100644
>>>>> index
>>>>> 0000000000000000000000000000000000000000..6cfb1f166fe1d3744a9f081758bf25b090e3fa1a
>>>>>
>>>>> --- /dev/null
>>>>> +++ b/gas/testsuite/gas/arm/predres.s
>>>>> @@ -0,0 +1,6 @@
>>>>> +@ Test case to validate Prediction Restriction Instructions
>>>>> +.section .text
>>>>> +.syntax unified
>>>>> + cfprctx r1
>>>>> + dvprctx r2
>>>>> + cpprctx r3
>>>>> diff --git a/gas/testsuite/gas/arm/predres1.d
>>>>> b/gas/testsuite/gas/arm/predres1.d
>>>>> new file mode 100644
>>>>> index
>>>>> 0000000000000000000000000000000000000000..b3a900a3d4756da529e2b765b20be4831b1cf3df
>>>>>
>>>>> --- /dev/null
>>>>> +++ b/gas/testsuite/gas/arm/predres1.d
>>>>> @@ -0,0 +1,11 @@
>>>>> +#name: Execution and Data Prediction Restriction instructions
>>>>> +#source: predres.s
>>>>> +#as: -march=armv8.5-a
>>>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>>>> +
>>>>> +.*: *file format .*arm.*
>>>>> +
>>>>> +Disassembly of section .text:
>>>>> +.*> ee071f93 mcr 15, 0, r1, cr7, cr3, \{4\}
>>>>> +.*> ee072fb3 mcr 15, 0, r2, cr7, cr3, \{5\}
>>>>> +.*> ee073ff3 mcr 15, 0, r3, cr7, cr3, \{7\}
>>>>> diff --git a/gas/testsuite/gas/arm/predres2.d
>>>>> b/gas/testsuite/gas/arm/predres2.d
>>>>> new file mode 100644
>>>>> index
>>>>> 0000000000000000000000000000000000000000..d17cf06eb0ea36977aa13853d4872daded805bc5
>>>>>
>>>>> --- /dev/null
>>>>> +++ b/gas/testsuite/gas/arm/predres2.d
>>>>> @@ -0,0 +1,11 @@
>>>>> +#name: Execution and Data Prediction Restriction instructions with
>>>>> +predres
>>>>> +#source: predres.s
>>>>> +#as: -march=armv8-a+predres
>>>>> +#objdump: -dr --prefix-addresses --show-raw-insn
>>>>> +
>>>>> +.*: *file format .*arm.*
>>>>> +
>>>>> +Disassembly of section .text:
>>>>> +.*> ee071f93 mcr 15, 0, r1, cr7, cr3, \{4\}
>>>>> +.*> ee072fb3 mcr 15, 0, r2, cr7, cr3, \{5\}
>>>>> +.*> ee073ff3 mcr 15, 0, r3, cr7, cr3, \{7\}
>>>>> diff --git a/include/opcode/arm.h b/include/opcode/arm.h
>>>>> index
>>>>> f4e0832ac662424899f91314fc1b20eabbce8507..e8800ca6d56886ff16be4485d7ae48ae8bd75694
>>>>> 100644
>>>>> --- a/include/opcode/arm.h
>>>>> +++ b/include/opcode/arm.h
>>>>> @@ -76,6 +76,7 @@
>>>>> #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX
>>>>> technology coprocessor. */
>>>>> #define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX
>>>>> technology coprocessor version 2. */
>>>>> +#define PREDRES_EXT_ARMV8 0x200000000 /* Prediction Restriction
>>>>> insns. */
>>>>> #define SB_EXT_ARMV8 0x100000000 /* SB instruction. */
>>>>> #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian
>>>>> doubles. */
>>>>> #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
>>>>> @@ -298,7 +299,8 @@
>>>>> | FPU_NEON_EXT_DOTPROD)
>>>>> #define ARM_ARCH_V8_5A ARM_FEATURE (ARM_AEXT_V8A,
>>>>> ARM_AEXT2_V8_5A, \
>>>>> CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
>>>>> - | FPU_NEON_EXT_DOTPROD | SB_EXT_ARMV8)
>>>>> + | FPU_NEON_EXT_DOTPROD | SB_EXT_ARMV8 \
>>>>> + | PREDRES_EXT_ARMV8)
>>>>> #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE,
>>>>> ARM_AEXT2_V8M)
>>>>> #define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \
>>>>> ARM_AEXT2_V8M_MAIN)
>>>>>
>>>>>
>>>>
>>>
>>
>
>
> rb9985.patch
>
>
> diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
> index 1ecaa4594ad5236d5087d7bf283c0e7326459a4e..80fb0c3b5ea31b399331c2b1d60e4a7ad05899cf 100644
> --- a/gas/config/tc-arm.c
> +++ b/gas/config/tc-arm.c
> @@ -258,6 +258,8 @@ static const arm_feature_set arm_ext_v8_3 =
> ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
> static const arm_feature_set arm_ext_sb =
> ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
> +static const arm_feature_set arm_ext_predres =
> + ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
>
> static const arm_feature_set arm_arch_any = ARM_ANY;
> #ifdef OBJ_ELF
> @@ -21525,6 +21527,14 @@ static const struct asm_opcode insns[] =
> #define THUMB_VARIANT & arm_ext_sb
> TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
>
> +#undef ARM_VARIANT
> +#define ARM_VARIANT & arm_ext_predres
> +#undef THUMB_VARIANT
> +#define THUMB_VARIANT & arm_ext_predres
> + CE("cfprctx", e070f93, 1, (RRnpc), rd),
> + CE("dvprctx", e070fb3, 1, (RRnpc), rd),
> + CE("cpprctx", e070ff3, 1, (RRnpc), rd),
> +
> /* ARMv8-M instructions. */
> #undef ARM_VARIANT
> #define ARM_VARIANT NULL
> @@ -26421,6 +26431,9 @@ static const struct arm_option_extension_value_table arm_extensions[] =
> ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
> ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
> ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
> + ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
> + ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
> + ARM_ARCH_V8A),
> ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
> ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
> ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
> diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
> index 18008c48666ccdea96f166612ab0868dbe4c8bf8..835777a3abb89eba97b11bd9972adf9a0826bd26 100644
> --- a/gas/doc/c-arm.texi
> +++ b/gas/doc/c-arm.texi
> @@ -189,6 +189,8 @@ The following extensions are currently supported:
> @code{mp} (Multiprocessing Extensions for v7-A and v7-R
> architectures),
> @code{os} (Operating System for v6M architecture),
> +@code{predres} (Execution and Data Prediction Restriction Instruction for
> +v8-A architectures, added by default from v8.5-A),
> @code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
> default from v8.5-A),
> @code{sec} (Security Extensions for v6K and v7-A architectures),
> diff --git a/gas/testsuite/gas/arm/predres-bad.d b/gas/testsuite/gas/arm/predres-bad.d
> new file mode 100644
> index 0000000000000000000000000000000000000000..8ddc8eeb0f64eeea5937145e99ea8a1aa039a921
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/predres-bad.d
> @@ -0,0 +1,4 @@
> +#name: Error for Prediction Restriction instructions without +predres
> +#source: predres.s
> +#as: -march=armv8-a
> +#error_output: predres-bad.l
> diff --git a/gas/testsuite/gas/arm/predres-bad.l b/gas/testsuite/gas/arm/predres-bad.l
> new file mode 100644
> index 0000000000000000000000000000000000000000..3f7efc62b069d678dcfeb48f6e93be7c328c16de
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/predres-bad.l
> @@ -0,0 +1,4 @@
> +[^:]*: Assembler messages:
> +[^:]*:4: Error: selected processor does not support `cfprctx r1' in ARM mode
> +[^:]*:5: Error: selected processor does not support `dvprctx r2' in ARM mode
> +[^:]*:6: Error: selected processor does not support `cpprctx r3' in ARM mode
> diff --git a/gas/testsuite/gas/arm/predres.s b/gas/testsuite/gas/arm/predres.s
> new file mode 100644
> index 0000000000000000000000000000000000000000..6cfb1f166fe1d3744a9f081758bf25b090e3fa1a
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/predres.s
> @@ -0,0 +1,6 @@
> +@ Test case to validate Prediction Restriction Instructions
> +.section .text
> +.syntax unified
> + cfprctx r1
> + dvprctx r2
> + cpprctx r3
> diff --git a/gas/testsuite/gas/arm/predres1.d b/gas/testsuite/gas/arm/predres1.d
> new file mode 100644
> index 0000000000000000000000000000000000000000..b3a900a3d4756da529e2b765b20be4831b1cf3df
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/predres1.d
> @@ -0,0 +1,11 @@
> +#name: Execution and Data Prediction Restriction instructions
> +#source: predres.s
> +#as: -march=armv8.5-a
> +#objdump: -dr --prefix-addresses --show-raw-insn
> +
> +.*: *file format .*arm.*
> +
> +Disassembly of section .text:
> +.*> ee071f93 mcr 15, 0, r1, cr7, cr3, \{4\}
> +.*> ee072fb3 mcr 15, 0, r2, cr7, cr3, \{5\}
> +.*> ee073ff3 mcr 15, 0, r3, cr7, cr3, \{7\}
> diff --git a/gas/testsuite/gas/arm/predres2.d b/gas/testsuite/gas/arm/predres2.d
> new file mode 100644
> index 0000000000000000000000000000000000000000..d17cf06eb0ea36977aa13853d4872daded805bc5
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/predres2.d
> @@ -0,0 +1,11 @@
> +#name: Execution and Data Prediction Restriction instructions with +predres
> +#source: predres.s
> +#as: -march=armv8-a+predres
> +#objdump: -dr --prefix-addresses --show-raw-insn
> +
> +.*: *file format .*arm.*
> +
> +Disassembly of section .text:
> +.*> ee071f93 mcr 15, 0, r1, cr7, cr3, \{4\}
> +.*> ee072fb3 mcr 15, 0, r2, cr7, cr3, \{5\}
> +.*> ee073ff3 mcr 15, 0, r3, cr7, cr3, \{7\}
> diff --git a/include/opcode/arm.h b/include/opcode/arm.h
> index c595799920e369b859f851d184639f9489554da4..71c430638b1af3785721f789a2fc7a476370da6d 100644
> --- a/include/opcode/arm.h
> +++ b/include/opcode/arm.h
> @@ -70,6 +70,7 @@
> #define ARM_EXT2_FP16_FML 0x00000800 /* ARM V8.2A FP16-FML instructions. */
> #define ARM_EXT2_V8_5A 0x00001000 /* ARM V8.5A. */
> #define ARM_EXT2_SB 0x00002000 /* Speculation Barrier instruction. */
> +#define ARM_EXT2_PREDRES 0x00004000 /* Prediction Restriction insns. */
>
> /* Co-processor space extensions. */
> #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
> @@ -297,7 +298,8 @@
> CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
> | FPU_NEON_EXT_DOTPROD)
> #define ARM_ARCH_V8_5A ARM_FEATURE (ARM_AEXT_V8A, \
> - ARM_AEXT2_V8_5A | ARM_EXT2_SB, \
> + ARM_AEXT2_V8_5A | ARM_EXT2_SB \
> + | ARM_EXT2_PREDRES, \
> CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
> | FPU_NEON_EXT_DOTPROD)
> #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M)
>