Re: [PATCH] RISC-V: Add fence.tso instruction

[Palmer Dabbelt <palmer at sifive dot com>]

On Mon, 01 Oct 2018 13:34:58 PDT (-0700), Jim Wilson wrote:
> On Mon, Oct 1, 2018 at 11:31 AM Palmer Dabbelt <palmer@sifive.com> wrote:
> > The RISC-V memory model has been ratified, and it includes an additional
> > fence: "fence.tso".  This pseudo instruction extends one of the
> > previously reserved full fence patterns to be less restrictive, and
> > therefor will execute correctly on all existing microarchitectures.
> > Thus there is no reason to allow this instruction to be disabled (or
> > unconverted to a full fence), so it's just unconditionally allowed.
>
> The v2.2 ISA fence description says that reserved bits should be
> ignored, so yes, this should be a safe forward compatible change.  I
> see that the draft v2.3 ISA fence description adds a new field "fence
> mode" (fm) which we aren't explicitly handling here, but there is no
> way to set it other than via a fence.tso instruction, so it doesn't
> look like we need explicit support for it.

Makes sense.  The encoding of the various fences (fence, fence.i, and 
fence.tso) isn't readily apparent from their names, but it's designed to be 
more easily detected by the styles of microarchitecture that may need to do so.  
As a result, I don't think allowing users to set the fields directly is that 
useful -- they're all invalid, anyway.

There's the bigger issue of what we'll do for Ztso targets, but for now nothing 
supports those so we can just wait.  My hope is still that nobody builds one... 
:)

Speaking of which, we should reserve an ELF header bit for Ztso.

> This looks OK to me.

Thanks.  Committed.