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[PATCH] Opcodes: (BRCLR / BRSET) Disassemble reserved codes instead of aborting.
- From: John Darrington <john at darrington dot wattle dot id dot au>
- To: binutils at sourceware dot org
- Cc: John Darrington <john at darrington dot wattle dot id dot au>
- Date: Fri, 10 Aug 2018 11:02:09 +0200
- Subject: [PATCH] Opcodes: (BRCLR / BRSET) Disassemble reserved codes instead of aborting.
Bit manipulation instructions which are not normally generated by the
assembler, should nevertheless be decoded by the disassembler.
opcodes/
* s12z-dis.c: BM_RESERVED1 to behave like BM_OPR_REG, and
BM_RESERVED0 like BM_REG_IMM.
---
gas/ChangeLog | 6 +++++
gas/testsuite/gas/s12z/bit-manip-invalid.d | 19 ++++++++++++++
gas/testsuite/gas/s12z/bit-manip-invalid.s | 11 ++++++++
gas/testsuite/gas/s12z/s12z.exp | 1 +
opcodes/ChangeLog | 6 +++++
opcodes/s12z-dis.c | 41 +++++++++++++++---------------
6 files changed, 64 insertions(+), 20 deletions(-)
create mode 100644 gas/testsuite/gas/s12z/bit-manip-invalid.d
create mode 100644 gas/testsuite/gas/s12z/bit-manip-invalid.s
diff --git a/gas/ChangeLog b/gas/ChangeLog
index ba6d9ca..c7799cb 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2018-07-28 John Darrington <john@darrington.wattle.id.au>
+
+ * testsuite/gas/s12z/bit-manip-invalid.d: New file.
+ * testsuite/gas/s12z/bit-manip-invalid.s: New file.
+ * testsuite/gas/s12z/s12z.exp: Add them.
+
2018-08-09 H.J. Lu <hongjiu.lu@intel.com>
* as.c (show_usage): Display default option for --elf-stt-common=.
diff --git a/gas/testsuite/gas/s12z/bit-manip-invalid.d b/gas/testsuite/gas/s12z/bit-manip-invalid.d
new file mode 100644
index 0000000..0cfcfe4
--- /dev/null
+++ b/gas/testsuite/gas/s12z/bit-manip-invalid.d
@@ -0,0 +1,19 @@
+#objdump: -d
+#name: Test of disassembler behaviour by with invalid bit manipulation instructions
+#source: bit-manip-invalid.s
+
+
+dump.o: file format elf32-s12z
+
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 01 nop
+ 1: 03 a5 10 04 brset.w 4100, d4, *+6
+ 5: 06
+ 6: 01 nop
+ 7: 01 nop
+ 8: 03 65 12 brset d1, #4, *+18
+ b: 01 nop
+ c: 01 nop
diff --git a/gas/testsuite/gas/s12z/bit-manip-invalid.s b/gas/testsuite/gas/s12z/bit-manip-invalid.s
new file mode 100644
index 0000000..6876ba8
--- /dev/null
+++ b/gas/testsuite/gas/s12z/bit-manip-invalid.s
@@ -0,0 +1,11 @@
+;;; This is really a test of the disassembler rather than
+;;; the assembler.
+ nop
+ DC.L 0x03A51004
+ DC.B 0x06
+ nop
+
+ nop
+ DC.L 0x03651201
+ nop
+
diff --git a/gas/testsuite/gas/s12z/s12z.exp b/gas/testsuite/gas/s12z/s12z.exp
index acd50cf..9d73ca0 100644
--- a/gas/testsuite/gas/s12z/s12z.exp
+++ b/gas/testsuite/gas/s12z/s12z.exp
@@ -113,6 +113,7 @@ run_dump_test ld-immu18
run_dump_test lea-immu18
run_dump_test ext24-ld-xy
run_dump_test st-xy
+run_dump_test bit-manip-invalid
# Symbol related tests
run_dump_test opr-symbol
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2b6938c..0207a6e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
2018-07-28 John Darrington <john@darrington.wattle.id.au>
+ * s12z-dis.c (bm_decode): Deal with cases where the mode is BM_RESERVED0 or BM_RESERVED1
+ * s12z-dis.c (bm_rel_decode): ditto
+ * s12z-dis.c (bm_n_bytes): ditto
+
+2018-07-28 John Darrington <john@darrington.wattle.id.au>
+
* s12z.h: Delete.
2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
diff --git a/opcodes/s12z-dis.c b/opcodes/s12z-dis.c
index 7130908..6ca9f07 100644
--- a/opcodes/s12z-dis.c
+++ b/opcodes/s12z-dis.c
@@ -1677,6 +1677,12 @@ mul_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
}
+ /* The NXP documentation is vague about BM_RESERVED0 and BM_RESERVED1,
+ and contains obvious typos.
+ However the Freescale tools and experiments with the chip itself
+ seem to indicate that they behave like BM_REG_IMM and BM_OPR_REG
+ respectively. */
+
enum BM_MODE {
BM_REG_IMM,
BM_RESERVED0,
@@ -1731,6 +1737,7 @@ bm_decode (bfd_vma memaddr, struct disassemble_info* info)
switch (mode)
{
case BM_REG_IMM:
+ case BM_RESERVED0:
operand_separator (info);
(*info->fprintf_func) (info->stream, "%s", registers[bm & 0x07].name);
break;
@@ -1747,6 +1754,7 @@ bm_decode (bfd_vma memaddr, struct disassemble_info* info)
opr_decode (memaddr + 1, info);
break;
case BM_OPR_REG:
+ case BM_RESERVED1:
{
uint8_t xb;
read_memory (memaddr + 1, &xb, 1, info);
@@ -1756,10 +1764,6 @@ bm_decode (bfd_vma memaddr, struct disassemble_info* info)
opr_decode (memaddr + 1, info);
}
break;
- case BM_RESERVED0:
- case BM_RESERVED1:
- assert (0);
- break;
}
uint8_t imm = 0;
@@ -1768,7 +1772,7 @@ bm_decode (bfd_vma memaddr, struct disassemble_info* info)
{
case BM_REG_IMM:
{
- imm = (bm & 0xF8) >> 3;
+ imm = (bm & 0x38) >> 3;
(*info->fprintf_func) (info->stream, "#%d", imm);
}
break;
@@ -1783,10 +1787,10 @@ bm_decode (bfd_vma memaddr, struct disassemble_info* info)
(*info->fprintf_func) (info->stream, "#%d", imm);
break;
case BM_OPR_REG:
+ case BM_RESERVED1:
(*info->fprintf_func) (info->stream, "%s", registers[(bm & 0x70) >> 4].name);
break;
case BM_RESERVED0:
- case BM_RESERVED1:
assert (0);
break;
}
@@ -1816,6 +1820,7 @@ bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
switch (mode)
{
case BM_REG_IMM:
+ case BM_RESERVED0:
break;
case BM_OPR_B:
(*info->fprintf_func) (info->stream, ".%c", 'b');
@@ -1827,6 +1832,7 @@ bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
(*info->fprintf_func) (info->stream, ".%c", 'l');
break;
case BM_OPR_REG:
+ case BM_RESERVED1:
{
uint8_t xb;
read_memory (memaddr + 1, &xb, 1, info);
@@ -1836,16 +1842,13 @@ bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
shift_size_table[(bm & 0x0C) >> 2]);
}
break;
- case BM_RESERVED0:
- case BM_RESERVED1:
- assert (0);
- break;
}
int n = 1;
switch (mode)
{
case BM_REG_IMM:
+ case BM_RESERVED0:
operand_separator (info);
(*info->fprintf_func) (info->stream, "%s", registers[bm & 0x07].name);
break;
@@ -1856,11 +1859,8 @@ bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
n = 1 + opr_n_bytes (memaddr + 1, info);
break;
case BM_OPR_REG:
- opr_decode (memaddr + 1, info);
- break;
- case BM_RESERVED0:
case BM_RESERVED1:
- assert (0);
+ opr_decode (memaddr + 1, info);
break;
}
@@ -1879,15 +1879,16 @@ bm_rel_decode (bfd_vma memaddr, struct disassemble_info* info)
imm |= (bm & 0x70) >> 4;
(*info->fprintf_func) (info->stream, "#%d", imm);
break;
+ case BM_RESERVED0:
+ imm = (bm & 0x38) >> 3;
+ (*info->fprintf_func) (info->stream, "#%d", imm);
+ break;
case BM_REG_IMM:
imm = (bm & 0xF8) >> 3;
(*info->fprintf_func) (info->stream, "#%d", imm);
break;
- case BM_RESERVED0:
- case BM_RESERVED1:
- assert (0);
- break;
case BM_OPR_REG:
+ case BM_RESERVED1:
(*info->fprintf_func) (info->stream, "%s", registers[(bm & 0x70) >> 4].name);
n += opr_n_bytes (memaddr + 1, info);
break;
@@ -1920,6 +1921,7 @@ bm_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
switch (mode)
{
case BM_REG_IMM:
+ case BM_RESERVED0:
break;
case BM_OPR_B:
@@ -1928,10 +1930,9 @@ bm_n_bytes (bfd_vma memaddr, struct disassemble_info* info)
n += opr_n_bytes (memaddr + 1, info);
break;
case BM_OPR_REG:
+ case BM_RESERVED1:
n += opr_n_bytes (memaddr + 1, info);
break;
- default:
- break;
}
return n;
--
2.1.4