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Re: [PATCH 6/6] x86: fold RegEip/RegRip and RegEiz/RegRiz
On Wed, Aug 1, 2018 at 11:52 PM, Jan Beulich <JBeulich@suse.com> wrote:
> This allows to simplify the code in a number of places.
>
> gas/
> 2018-08-02 Jan Beulich <jbeulich@suse.com>
>
> * config/tc-i386.c (build_modrm_byte): Use RegIP and RegIZ.
> (output_disp): Use RegIP.
> (i386_addressing_mode): Drop/replace uses of RegEip/RegEiz.
> (parse_real_register): Use RegIZ.
> * config/tc-i386-intel.c (i386_intel_simplify_register): Use
> RegIZ.
> * testsuite/gas/i386/x86-64-mpx-inval-2.l: Adjust expectations.
>
> opcodes/
> 2018-08-02 Jan Beulich <jbeulich@suse.com>
>
> * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
> (RegIP, RegIZ): Define.
> * i386-reg.tbl: Adjust comments.
> (rip): Use Qword instead of BaseIndex. Use RegIP.
> (eip): Use Dword instead of BaseIndex. Use RegIP.
> (riz): Add Qword. Use RegIZ.
> (eiz): Add Dword. Use RegIZ.
> * i386-tbl.h: Re-generate.
>
> --- a/gas/config/tc-i386-intel.c
> +++ b/gas/config/tc-i386-intel.c
> @@ -289,8 +289,7 @@ i386_intel_simplify_register (expression
> && (i386_regtab[reg_num].reg_type.bitfield.xmmword
> || i386_regtab[reg_num].reg_type.bitfield.ymmword
> || i386_regtab[reg_num].reg_type.bitfield.zmmword
> - || i386_regtab[reg_num].reg_num == RegRiz
> - || i386_regtab[reg_num].reg_num == RegEiz))
> + || i386_regtab[reg_num].reg_num == RegIZ))
> intel_state.index = i386_regtab + reg_num;
> else if (!intel_state.base && !intel_state.in_scale)
> intel_state.base = i386_regtab + reg_num;
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -7139,8 +7139,7 @@ build_modrm_byte (void)
>
> if (i.tm.opcode_modifier.vecsib)
> {
> - if (i.index_reg->reg_num == RegEiz
> - || i.index_reg->reg_num == RegRiz)
> + if (i.index_reg->reg_num == RegIZ)
> abort ();
>
> i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
> @@ -7211,8 +7210,7 @@ build_modrm_byte (void)
> else if (!i.tm.opcode_modifier.vecsib)
> {
> /* !i.base_reg && i.index_reg */
> - if (i.index_reg->reg_num == RegEiz
> - || i.index_reg->reg_num == RegRiz)
> + if (i.index_reg->reg_num == RegIZ)
> i.sib.index = NO_INDEX_REGISTER;
> else
> i.sib.index = i.index_reg->reg_num;
> @@ -7238,8 +7236,7 @@ build_modrm_byte (void)
> }
> }
> /* RIP addressing for 64bit mode. */
> - else if (i.base_reg->reg_num == RegRip ||
> - i.base_reg->reg_num == RegEip)
> + else if (i.base_reg->reg_num == RegIP)
> {
> gas_assert (!i.tm.opcode_modifier.vecsib);
> i.rm.regmem = NO_BASE_REGISTER;
> @@ -7331,8 +7328,7 @@ build_modrm_byte (void)
> }
> else if (!i.tm.opcode_modifier.vecsib)
> {
> - if (i.index_reg->reg_num == RegEiz
> - || i.index_reg->reg_num == RegRiz)
> + if (i.index_reg->reg_num == RegIZ)
> i.sib.index = NO_INDEX_REGISTER;
> else
> i.sib.index = i.index_reg->reg_num;
> @@ -8178,8 +8174,7 @@ output_disp (fragS *insn_start_frag, off
> {
> fixP->fx_tcbit = i.rex != 0;
> if (i.base_reg
> - && (i.base_reg->reg_num == RegRip
> - || i.base_reg->reg_num == RegEip))
> + && (i.base_reg->reg_num == RegIP))
> fixP->fx_tcbit2 = 1;
> }
> else
> @@ -9280,9 +9275,7 @@ i386_addressing_mode (void)
>
> if (addr_reg)
> {
> - if (addr_reg->reg_num == RegEip
> - || addr_reg->reg_num == RegEiz
> - || addr_reg->reg_type.bitfield.dword)
> + if (addr_reg->reg_type.bitfield.dword)
> addr_mode = CODE_32BIT;
> else if (flag_code != CODE_64BIT
> && addr_reg->reg_type.bitfield.word)
> @@ -9392,21 +9385,18 @@ bad_address:
> {
> /* 32-bit/64-bit checks. */
> if ((i.base_reg
> - && (addr_mode == CODE_64BIT
> - ? !i.base_reg->reg_type.bitfield.qword
> - : !i.base_reg->reg_type.bitfield.dword)
> - && (i.index_reg
> - || (i.base_reg->reg_num
> - != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
> + && ((addr_mode == CODE_64BIT
> + ? !i.base_reg->reg_type.bitfield.qword
> + : !i.base_reg->reg_type.bitfield.dword)
> + || (i.index_reg && i.base_reg->reg_num == RegIP)
> + || i.base_reg->reg_num == RegIZ))
> || (i.index_reg
> && !i.index_reg->reg_type.bitfield.xmmword
> && !i.index_reg->reg_type.bitfield.ymmword
> && !i.index_reg->reg_type.bitfield.zmmword
> && ((addr_mode == CODE_64BIT
> - ? !(i.index_reg->reg_type.bitfield.qword
> - || i.index_reg->reg_num == RegRiz)
> - : !(i.index_reg->reg_type.bitfield.dword
> - || i.index_reg->reg_num == RegEiz))
> + ? !i.index_reg->reg_type.bitfield.qword
> + : !i.index_reg->reg_type.bitfield.dword)
> || !i.index_reg->reg_type.bitfield.baseindex)))
> goto bad_address;
>
> @@ -9415,7 +9405,7 @@ bad_address:
> || (current_templates->start->base_opcode & ~1) == 0x0f1a)
> {
> /* They cannot use RIP-relative addressing. */
> - if (i.base_reg && i.base_reg->reg_num == RegRip)
> + if (i.base_reg && i.base_reg->reg_num == RegIP)
> {
> as_bad (_("`%s' cannot be used here"), operand_string);
> return 0;
> @@ -10475,8 +10465,7 @@ parse_real_register (char *reg_string, c
> return (const reg_entry *) NULL;
>
> /* Don't allow fake index register unless allow_index_reg isn't 0. */
> - if (!allow_index_reg
> - && (r->reg_num == RegEiz || r->reg_num == RegRiz))
> + if (!allow_index_reg && r->reg_num == RegIZ)
> return (const reg_entry *) NULL;
>
> /* Upper 16 vector registers are only available with VREX in 64bit
> --- a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
> +++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l
> @@ -2,7 +2,7 @@
> .*:6: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
> .*:7: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
> .*:8: Error: `\(%rip\)' cannot be used here
> -.*:9: Error: 32-bit address isn't allowed in 64-bit MPX instructions.
> +.*:9: Error: .*
>
We should keep "32-bit address isn't allowed in 64-bit MPX instructions"
error.
--
H.J.