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Re: [committed, PATCH] x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: "Igor V Tsimbalist" <igor dot v dot tsimbalist at intel dot com>, <binutils at sourceware dot org>
- Date: Wed, 18 Jul 2018 07:48:14 -0600
- Subject: Re: [committed, PATCH] x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq
- References: <20180717195836.GA10930@intel.com> <20180718123543.GA25833@intel.com>
>>> On 18.07.18 at 14:35, <hongjiu.lu@intel.com> wrote:
> On Tue, Jul 17, 2018 at 12:58:36PM -0700, H.J. Lu wrote:
>> After
>>
>> commit 1b54b8d7e4fc8055f9220a5287e8a94d8a65a88d
>> Author: Jan Beulich <jbeulich@novell.com>
>> Date: Mon Dec 18 09:36:14 2017 +0100
>>
>> x86: fold RegXMM/RegYMM/RegZMM into RegSIMD
>>
>> ... qualified by their respective sizes, allowing to drop FirstXmm0 at
>> the same time.
>>
>> folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible
>> to distinguish if XMMWORD can represent a memory reference when operand
>> specification contains SIMD register. For example, template operands
>> specification like these
>>
>> RegXMM|...|Xmmword|...
>>
>> and
>>
>> RegXMM|...
>>
>> The Xmmword bitfield is always set by RegXMM which is represented by
>> "RegSIMD|Xmmword". This patch adds NoXmmWordMem to opcode_modifiers
>> to indicate that Xmmword memory isn't allowed.
>>
>
> This is what I checked in. I will backport it to 2.31 branch later.
Thanks for finding and fixing this.
Jan