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Re: [PATCH] x86/Intel: accept memory operand size specifiers for CET insns
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: Jan Beulich <JBeulich at suse dot com>
- Cc: Binutils <binutils at sourceware dot org>
- Date: Tue, 10 Jul 2018 06:59:45 -0700
- Subject: Re: [PATCH] x86/Intel: accept memory operand size specifiers for CET insns
- References: <5B44B5AD02000078001D2AC3@prv1-mh.provo.novell.com>
On Tue, Jul 10, 2018 at 6:33 AM, Jan Beulich <JBeulich@suse.com> wrote:
> gas/
> 2018-07-10 Jan Beulich <jbeulich@suse.com>
>
> * testsuite/gas/i386/cet.s, testsuite/gas/i386/x86-64-cet.s:
> Add Intel cases with operand size specifiers.
> * testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
> testsuite/gas/i386/x86-64-cet-intel.d,
> testsuite/gas/i386/x86-64-cet.d: Adjust expectations.
>
> opcodes/
> 2018-07-10 Jan Beulich <jbeulich@suse.com>
>
> * i386-opc.tbl (wrssd, wrussd): Add Dword.
> (wrssq, wrussq): Add Qword.
> * i386-tbl.h: Re-generate.
>
Should the disassembler be updated to add DWORD/QWORD?
--
H.J.