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[PATCH 3/5] x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMask
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: <binutils at sourceware dot org>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
- Date: Wed, 25 Apr 2018 04:30:11 -0600
- Subject: [PATCH 3/5] x86: drop CpuRegMMX, CpuReg[XYZ]MM, and CpuRegMask
- References: <5AE0566402000078001BE4EA@prv1-mh.provo.novell.com>
It's not clear to me why they had been introduced - the respective
comments in opcodes/i386-gen.c are certainly wrong: ymm<N> registers
are very well supported (and necessary) with just AVX512F.
gas/
2018-04-25 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (parse_real_register): Re-write {,x,y,z}mm
and mask register handling.
* testsuite/gas/i386/avx512f-ymm.s, testsuite/gas/i386/avx512f-ymm.d,
testsuite/gas/i386/xmmhi32.s, testsuite/gas/i386/xmmhi32.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
opcodes/
2018-04-25 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
comment.
(cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
and CpuRegMask.
* i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
CpuRegMask: Delete.
(union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
cpuregzmm, and cpuregmask.
* i386-init.h: Re-generate.
* i386-tbl.h: Re-generate.
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -10154,21 +10154,23 @@ parse_real_register (char *reg_string, c
&& !cpu_arch_flags.bitfield.cpui386)
return (const reg_entry *) NULL;
- if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
+ if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
return (const reg_entry *) NULL;
- if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
- return (const reg_entry *) NULL;
-
- if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
- return (const reg_entry *) NULL;
-
- if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
- return (const reg_entry *) NULL;
-
- if (r->reg_type.bitfield.regmask
- && !cpu_arch_flags.bitfield.cpuregmask)
- return (const reg_entry *) NULL;
+ if (!cpu_arch_flags.bitfield.cpuavx512f)
+ {
+ if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
+ return (const reg_entry *) NULL;
+
+ if (!cpu_arch_flags.bitfield.cpuavx)
+ {
+ if (r->reg_type.bitfield.ymmword)
+ return (const reg_entry *) NULL;
+
+ if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
+ return (const reg_entry *) NULL;
+ }
+ }
if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
return (const reg_entry *) NULL;
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f-ymm.d
@@ -0,0 +1,14 @@
+#objdump: -dw
+#name: i386 AVX512F YMM registers
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <ymm>:
+[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 31 c0[ ]*vpmovzxbd %xmm0,%zmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 7d 48 33 c0[ ]*vpmovzxwd %ymm0,%zmm0
+[ ]*[a-f0-9]+:[ ]*62 f1 7c 48 5a c0[ ]*vcvtps2pd %ymm0,%zmm0
+[ ]*[a-f0-9]+:[ ]*62 f1 fd 48 5a c0[ ]*vcvtpd2ps %zmm0,%ymm0
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f-ymm.s
@@ -0,0 +1,9 @@
+ .text
+ .arch generic32
+ .arch .avx512f
+ymm:
+ vpmovzxbd %xmm0, %zmm0
+ vpmovzxwd %ymm0, %zmm0
+
+ vcvtps2pd %ymm0, %zmm0
+ vcvtpd2ps %zmm0, %ymm0
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -187,6 +187,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_list_test "noavx512-1" "-al"
run_list_test "noavx512-2" "-al"
run_dump_test "noextreg"
+ run_dump_test "xmmhi32"
run_dump_test "xsave"
run_dump_test "xsave-intel"
run_dump_test "aes"
@@ -209,6 +210,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "avx512f-opts-intel"
run_dump_test "avx512f-nondef"
run_list_test "avx512f-plain" "-al"
+ run_dump_test "avx512f-ymm"
run_dump_test "avx512cd"
run_dump_test "avx512cd-intel"
run_dump_test "avx512er"
--- /dev/null
+++ b/gas/testsuite/gas/i386/xmmhi32.d
@@ -0,0 +1,31 @@
+#objdump: -dwr
+#name: high/disabled XMM/mask registers in 32-bit mode
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <xmm>:
+[ ]*[a-f0-9]+: c5 f0 58 05 00 00 00 00 vaddps 0x0,%xmm1,%xmm0 [a-f0-9]+: R_386_32 xmm8
+[ ]*[a-f0-9]+: c5 f4 58 05 00 00 00 00 vaddps 0x0,%ymm1,%ymm0 [a-f0-9]+: R_386_32 ymm8
+[ ]*[a-f0-9]+: 62 f1 74 48 58 05 00 00 00 00 vaddps 0x0,%zmm1,%zmm0 [a-f0-9]+: R_386_32 zmm8
+[ ]*[a-f0-9]+: 62 f1 74 48 58 05 00 00 00 00 vaddps 0x0,%zmm1,%zmm0 [a-f0-9]+: R_386_32 zmm16
+[ ]*[a-f0-9]+: 62 f1 74 48 58 05 00 00 00 00 vaddps 0x0,%zmm1,%zmm0 [a-f0-9]+: R_386_32 zmm24
+[ ]*[a-f0-9]+: c5 f9 6f 05 00 00 00 00 vmovdqa 0x0,%xmm0 [a-f0-9]+: R_386_32 xmm8
+[ ]*[a-f0-9]+: c5 fd 6f 05 00 00 00 00 vmovdqa 0x0,%ymm0 [a-f0-9]+: R_386_32 ymm8
+[ ]*[a-f0-9]+: c5 f9 7f 05 00 00 00 00 vmovdqa %xmm0,0x0 [a-f0-9]+: R_386_32 xmm8
+[ ]*[a-f0-9]+: c5 fd 7f 05 00 00 00 00 vmovdqa %ymm0,0x0 [a-f0-9]+: R_386_32 ymm8
+[ ]*[a-f0-9]+: c5 f0 58 05 00 00 00 00 vaddps 0x0,%xmm1,%xmm0 [a-f0-9]+: R_386_32 xmm8
+[ ]*[a-f0-9]+: c5 f4 58 05 00 00 00 00 vaddps 0x0,%ymm1,%ymm0 [a-f0-9]+: R_386_32 ymm8
+[ ]*[a-f0-9]+: c5 f9 6f 05 00 00 00 00 vmovdqa 0x0,%xmm0 [a-f0-9]+: R_386_32 zmm0
+[ ]*[a-f0-9]+: c5 f9 6f 05 00 00 00 00 vmovdqa 0x0,%xmm0 [a-f0-9]+: R_386_32 k0
+[ ]*[a-f0-9]+: 0f 58 05 00 00 00 00 addps 0x0,%xmm0 [a-f0-9]+: R_386_32 xmm8
+[ ]*[a-f0-9]+: 0f 58 05 00 00 00 00 addps 0x0,%xmm0 [a-f0-9]+: R_386_32 ymm0
+[ ]*[a-f0-9]+: 0f 58 05 00 00 00 00 addps 0x0,%xmm0 [a-f0-9]+: R_386_32 ymm8
+[ ]*[a-f0-9]+: 0f 58 05 00 00 00 00 addps 0x0,%xmm0 [a-f0-9]+: R_386_32 zmm0
+[ ]*[a-f0-9]+: 0f 58 05 00 00 00 00 addps 0x0,%xmm0 [a-f0-9]+: R_386_32 k0
+[ ]*[a-f0-9]+: a1 00 00 00 00 mov 0x0,%eax [a-f0-9]+: R_386_32 xmm0
+[ ]*[a-f0-9]+: a1 00 00 00 00 mov 0x0,%eax [a-f0-9]+: R_386_32 ymm0
+[ ]*[a-f0-9]+: a1 00 00 00 00 mov 0x0,%eax [a-f0-9]+: R_386_32 zmm0
+[ ]*[a-f0-9]+: a1 00 00 00 00 mov 0x0,%eax [a-f0-9]+: R_386_32 k0
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/xmmhi32.s
@@ -0,0 +1,33 @@
+ .text
+ .intel_syntax noprefix
+ .code32
+xmm:
+ vaddps xmm0, xmm1, xmm8
+ vaddps ymm0, ymm1, ymm8
+ vaddps zmm0, zmm1, zmm8
+ vaddps zmm0, zmm1, zmm16
+ vaddps zmm0, zmm1, zmm24
+
+ vmovdqa xmm0, xmm8
+ vmovdqa ymm0, ymm8
+ vmovdqa xmm8, xmm0
+ vmovdqa ymm8, ymm0
+
+ .arch .noavx512f
+ vaddps xmm0, xmm1, xmm8
+ vaddps ymm0, ymm1, ymm8
+ vmovdqa xmm0, zmm0
+ vmovdqa xmm0, k0
+
+ .arch .noavx
+ addps xmm0, xmm8
+ addps xmm0, ymm0
+ addps xmm0, ymm8
+ addps xmm0, zmm0
+ addps xmm0, k0
+
+ .arch .nosse
+ mov eax, xmm0
+ mov eax, ymm0
+ mov eax, zmm0
+ mov eax, k0
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -116,9 +116,9 @@ static initializer cpu_flag_init[] =
{ "CPU_SYSCALL_FLAGS",
"CpuSYSCALL" },
{ "CPU_MMX_FLAGS",
- "CpuRegMMX|CpuMMX" },
+ "CpuMMX" },
{ "CPU_SSE_FLAGS",
- "CpuRegXMM|CpuSSE" },
+ "CpuSSE" },
{ "CPU_SSE2_FLAGS",
"CPU_SSE_FLAGS|CpuSSE2" },
{ "CPU_SSE3_FLAGS",
@@ -192,13 +192,11 @@ static initializer cpu_flag_init[] =
{ "CPU_ABM_FLAGS",
"CpuABM" },
{ "CPU_AVX_FLAGS",
- "CPU_SSE4_2_FLAGS|CpuRegYMM|CpuAVX" },
+ "CPU_SSE4_2_FLAGS|CpuAVX" },
{ "CPU_AVX2_FLAGS",
"CPU_AVX_FLAGS|CpuAVX2" },
- /* Don't use CPU_AVX2_FLAGS on CPU_AVX512F_FLAGS since AVX512F doesn't
- support YMM registers. */
{ "CPU_AVX512F_FLAGS",
- "CpuVREX|CPU_SSE4_2_FLAGS|CpuRegZMM|CpuRegMask|CpuAVX|CpuAVX2|CpuAVX512F" },
+ "CPU_AVX2_FLAGS|CpuVREX|CpuAVX512F" },
{ "CPU_AVX512CD_FLAGS",
"CPU_AVX512F_FLAGS|CpuAVX512CD" },
{ "CPU_AVX512ER_FLAGS",
@@ -210,9 +208,7 @@ static initializer cpu_flag_init[] =
{ "CPU_AVX512BW_FLAGS",
"CPU_AVX512F_FLAGS|CpuAVX512BW" },
{ "CPU_AVX512VL_FLAGS",
- /* Use CPU_AVX2_FLAGS on CPU_AVX512VL_FLAGS since AVX512VL supports YMM
- registers. */
- "CPU_AVX512F_FLAGS|CPU_AVX2_FLAGS|CpuAVX512VL" },
+ "CPU_AVX512F_FLAGS|CpuAVX512VL" },
{ "CPU_AVX512IFMA_FLAGS",
"CPU_AVX512F_FLAGS|CpuAVX512IFMA" },
{ "CPU_AVX512VBMI_FLAGS",
@@ -314,7 +310,7 @@ static initializer cpu_flag_init[] =
{ "CPU_ANY_AVX2_FLAGS",
"CpuAVX2" },
{ "CPU_ANY_AVX512F_FLAGS",
- "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512F" },
+ "CpuVREX|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512F" },
{ "CPU_ANY_AVX512CD_FLAGS",
"CpuAVX512CD" },
{ "CPU_ANY_AVX512ER_FLAGS",
@@ -581,11 +577,6 @@ static bitfield cpu_flags[] =
BITFIELD (CpuPCONFIG),
BITFIELD (CpuWAITPKG),
BITFIELD (CpuCLDEMOTE),
- BITFIELD (CpuRegMMX),
- BITFIELD (CpuRegXMM),
- BITFIELD (CpuRegYMM),
- BITFIELD (CpuRegZMM),
- BITFIELD (CpuRegMask),
#ifdef CpuUnused
BITFIELD (CpuUnused),
#endif
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -231,16 +231,6 @@ enum
CpuWAITPKG,
/* CLDEMOTE instruction required */
CpuCLDEMOTE,
- /* MMX register support required */
- CpuRegMMX,
- /* XMM register support required */
- CpuRegXMM,
- /* YMM register support required */
- CpuRegYMM,
- /* ZMM register support required */
- CpuRegZMM,
- /* Mask register support required */
- CpuRegMask,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
@@ -364,11 +354,6 @@ typedef union i386_cpu_flags
unsigned int cpupconfig:1;
unsigned int cpuwaitpkg:1;
unsigned int cpucldemote:1;
- unsigned int cpuregmmx:1;
- unsigned int cpuregxmm:1;
- unsigned int cpuregymm:1;
- unsigned int cpuregzmm:1;
- unsigned int cpuregmask:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused