This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH] RISC-V: Add new option -mrelax/-mno-relax.
- From: Kito Cheng <kito dot cheng at gmail dot com>
- To: Jim Wilson <jimw at sifive dot com>, Palmer Dabbelt <palmer at sifive dot com>, Andrew Waterman <andrew at sifive dot com>, patches at groups dot riscv dot org, binutils at sourceware dot org
- Date: Fri, 20 Apr 2018 13:59:27 +0800
- Subject: [PATCH] RISC-V: Add new option -mrelax/-mno-relax.
This patch add -mrelax and -mno-relax option to RISC-V assembler to
enable/disable relax optimization for input file.
2018-04-20 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (options): Add OPTION_RELAX and
OPTION_NO_RELAX.
(md_longopts): New option -mrelax and -mno-relax.
(md_parse_option): Handle -mrelax and -mno-relax.
* doc/c-riscv.texi: Document for -mrelax and -mno-relax.
* testsuite/gas/riscv/no-relax-reloc.d: New.
* testsuite/gas/riscv/no-relax-reloc.s: New.
* testsuite/gas/riscv/relax-reloc.d: New.
* testsuite/gas/riscv/relax-reloc.s: New.
From d7cec0102f1154ee815978f02705e9c657b2d4af Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng@gmail.com>
Date: Fri, 20 Apr 2018 11:36:13 +0800
Subject: [PATCH] RISC-V: Add new option -mrelax/-mno-relax.
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (options): Add OPTION_RELAX and
OPTION_NO_RELAX.
(md_longopts): New option -mrelax and -mno-relax.
(md_parse_option): Handle -mrelax and -mno-relax.
* doc/c-riscv.texi: Document for -mrelax and -mno-relax.
* testsuite/gas/riscv/no-relax-reloc.d: New.
* testsuite/gas/riscv/no-relax-reloc.s: New.
* testsuite/gas/riscv/relax-reloc.d: New.
* testsuite/gas/riscv/relax-reloc.s: New.
---
gas/config/tc-riscv.c | 14 ++++++++++++++
gas/doc/c-riscv.texi | 10 ++++++++++
gas/testsuite/gas/riscv/no-relax-reloc.d | 12 ++++++++++++
gas/testsuite/gas/riscv/no-relax-reloc.s | 8 ++++++++
gas/testsuite/gas/riscv/relax-reloc.d | 17 +++++++++++++++++
gas/testsuite/gas/riscv/relax-reloc.s | 8 ++++++++
6 files changed, 69 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/no-relax-reloc.d
create mode 100644 gas/testsuite/gas/riscv/no-relax-reloc.s
create mode 100644 gas/testsuite/gas/riscv/relax-reloc.d
create mode 100644 gas/testsuite/gas/riscv/relax-reloc.s
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index f65702383c..be32e6c979 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2136,6 +2136,8 @@ enum options
OPTION_PIC,
OPTION_NO_PIC,
OPTION_MABI,
+ OPTION_RELAX,
+ OPTION_NO_RELAX,
OPTION_END_OF_ENUM
};
@@ -2146,6 +2148,8 @@ struct option md_longopts[] =
{"fpic", no_argument, NULL, OPTION_PIC},
{"fno-pic", no_argument, NULL, OPTION_NO_PIC},
{"mabi", required_argument, NULL, OPTION_MABI},
+ {"mrelax", no_argument, NULL, OPTION_RELAX},
+ {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
{NULL, no_argument, NULL, 0}
};
@@ -2205,6 +2209,14 @@ md_parse_option (int c, const char *arg)
return 0;
break;
+ case OPTION_RELAX:
+ riscv_opts.relax = TRUE;
+ break;
+
+ case OPTION_NO_RELAX:
+ riscv_opts.relax = FALSE;
+ break;
+
default:
return 0;
}
@@ -2921,6 +2933,8 @@ RISC-V options:\n\
-fno-pic don't generate position-independent code (default)\n\
-march=ISA set the RISC-V architecture\n\
-mabi=ABI set the RISC-V ABI\n\
+ -mrelax enable relax (default)\n\
+ -mno-relax disable relax\n\
"));
}
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 30e61250d3..632c727ad1 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -48,6 +48,16 @@ by "f", "d", or "q" to indicate single-precision, double-precision, or
quad-precision floating-point calling convention, or none to indicate
the soft-float calling convention.
+@cindex @samp{-mrelax} option, RISC-V
+@item -mrelax
+Take advantage of linker relaxations to reduce the number of instructions
+required to materialize symbol addresses. (default)
+
+@cindex @samp{-mno-relax} option, RISC-V
+@item -mno-relax
+Don't do linker relaxations.
+
+
@end table
@c man end
diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.d b/gas/testsuite/gas/riscv/no-relax-reloc.d
new file mode 100644
index 0000000000..62f28e0927
--- /dev/null
+++ b/gas/testsuite/gas/riscv/no-relax-reloc.d
@@ -0,0 +1,12 @@
+#as: -mno-relax
+#objdump: -r
+
+.*:[ ]+file format .*
+
+RELOCATION RECORDS FOR .*
+.*
+0+0 R_RISCV_HI20.*
+0+4 R_RISCV_LO12_I.*
+0+8 R_RISCV_PCREL_HI20.*
+0+c R_RISCV_PCREL_LO12_I.*
+0+10 R_RISCV_CALL.*
diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.s b/gas/testsuite/gas/riscv/no-relax-reloc.s
new file mode 100644
index 0000000000..7f1a484fc2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/no-relax-reloc.s
@@ -0,0 +1,8 @@
+target:
+ lui a5,%hi(target)
+ lw a5,%lo(target)(a5)
+
+ .LA0: auipc a5,%pcrel_hi(bar)
+ lw a0,%pcrel_lo(.LA0)(a5)
+
+ call target
diff --git a/gas/testsuite/gas/riscv/relax-reloc.d b/gas/testsuite/gas/riscv/relax-reloc.d
new file mode 100644
index 0000000000..f5f592ce03
--- /dev/null
+++ b/gas/testsuite/gas/riscv/relax-reloc.d
@@ -0,0 +1,17 @@
+#as:
+#objdump: -r
+
+.*:[ ]+file format .*
+
+RELOCATION RECORDS FOR .*
+.*
+0+0 R_RISCV_HI20.*
+0+0 R_RISCV_RELAX.*
+0+4 R_RISCV_LO12_I.*
+0+4 R_RISCV_RELAX.*
+0+8 R_RISCV_PCREL_HI20.*
+0+8 R_RISCV_RELAX.*
+0+c R_RISCV_PCREL_LO12_I.*
+0+c R_RISCV_RELAX.*
+0+10 R_RISCV_CALL.*
+0+10 R_RISCV_RELAX.*
diff --git a/gas/testsuite/gas/riscv/relax-reloc.s b/gas/testsuite/gas/riscv/relax-reloc.s
new file mode 100644
index 0000000000..7f1a484fc2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/relax-reloc.s
@@ -0,0 +1,8 @@
+target:
+ lui a5,%hi(target)
+ lw a5,%lo(target)(a5)
+
+ .LA0: auipc a5,%pcrel_hi(bar)
+ lw a0,%pcrel_lo(.LA0)(a5)
+
+ call target
--
2.11.2