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Re: [PATCH 1/3] Enable Intel WAITPKG instructions.

From: "H.J. Lu" <hjl dot tools at gmail dot com>
To: Jan Beulich <jbeulich at suse dot com>
Cc: "Tsimbalist, Igor V" <igor dot v dot tsimbalist at intel dot com>, Binutils <binutils at sourceware dot org>
Date: Sun, 15 Apr 2018 06:01:02 -0700
Subject: Re: [PATCH 1/3] Enable Intel WAITPKG instructions.
References: <D511F25789BA7F4EBA64C8A63891A002AFB067DE@IRSMSX102.ger.corp.intel.com> <5AD337E3020000780012D258@prv1-mh.provo.novell.com> <CAMe9rOpwLODkzWSGL2CS6k1gxN=PXPZKXpHGaoqLaHtDy3N5rg@mail.gmail.com>

On Sun, Apr 15, 2018 at 5:16 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Sun, Apr 15, 2018 at 4:30 AM, Jan Beulich <jbeulich@suse.com> wrote:
>>>>> "Tsimbalist, Igor V" <igor.v.tsimbalist@intel.com> 04/09/18 3:41 PM >>>
>>>opcodes/
>>>* i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
>>>PREFIX_MOD_1_0FAE_REG_6.
>>>* i386-dis-evex.h (prefix_table):
>>>New instructions (see prefixes above).
>>>* i386-gen.c (cpu_flag_init): Add WAITPKG.
>>>(cpu_flags): Likewise.
>>>* i386-opc.h (enum): Likewise.
>>>(i386_cpu_flags): Likewise.
>>>* i386-opc.tbl: Add umonitor, umwait, tpause.
>>
>> After having read the instruction pages in full I disagree with the tpause and
>> umwait templates you've introduced: Arguably the instruction pages are slightly
>> ambiguous, but especially the fault conditions suggest that in 64-bit mode both
>> 32- and 64-bit registers can be specified as input operands. Hence both insns
>> should have just a single template with no Cpu64 or CpuNo64, and with
>> Reg32|Reg64 as permitted operands.
>>
>> Also, while H.J. may not like that, I think both should permit for l and q suffixes.
>>
>> Jan
>>
>
> They should be treated similar to pinsrw.   That is both r32/r64 are allowed and
> REX.W is skipped.   As for suffix, we shouldn't add them since these are new
> instructions.

Here is the path.

-- 
H.J.

From 228e9bd74b8c2c0cbd1bb65061ed21903b6defac Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Sun, 15 Apr 2018 05:49:22 -0700
Subject: [PATCH] x86: Allow 32-bit registers for tpause and umwait

Since only the first 32 bits of input operand are used for tpause and
umwait, the REX.W bit is skipped.  Both 32-bit registers and 64-bit
registers are allowed.

gas/

	* testsuite/gas/i386/x86-64-waitpkg.s: Add 32-bit registers
	tests for tpause and umwait.
	* testsuite/gas/i386/x86-64-waitpkg-intel.d: Updated.
	* testsuite/gas/i386/x86-64-waitpkg.d: Likewise.

opcodes/

	* i386-dis.c (prefix_table): Replace Em with Edq on tpause and
	umwait.
	* i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
	64-bit mode.
	* i386-tbl.h: Regenerated.
---
 gas/testsuite/gas/i386/x86-64-waitpkg-intel.d | 12 ++++++---
 gas/testsuite/gas/i386/x86-64-waitpkg.d       | 12 ++++++---
 gas/testsuite/gas/i386/x86-64-waitpkg.s       |  4 +++
 opcodes/i386-dis.c                            |  4 +--
 opcodes/i386-opc.tbl                          |  6 ++---
 opcodes/i386-tbl.h                            | 36 +++------------------------
 6 files changed, 28 insertions(+), 46 deletions(-)

diff --git a/gas/testsuite/gas/i386/x86-64-waitpkg-intel.d b/gas/testsuite/gas/i386/x86-64-waitpkg-intel.d
index e70be23c49..e0387dd1ad 100644
--- a/gas/testsuite/gas/i386/x86-64-waitpkg-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-waitpkg-intel.d
@@ -12,8 +12,12 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*f3 0f ae f0[ 	]*umonitor rax
 [ 	]*[a-f0-9]+:[ 	]*f3 41 0f ae f2[ 	]*umonitor r10
 [ 	]*[a-f0-9]+:[ 	]*67 f3 41 0f ae f2[ 	]*umonitor r10d
-[ 	]*[a-f0-9]+:[ 	]*f2 0f ae f1[ 	]*umwait rcx
-[ 	]*[a-f0-9]+:[ 	]*f2 41 0f ae f2[ 	]*umwait r10
-[ 	]*[a-f0-9]+:[ 	]*66 0f ae f1[ 	]*tpause rcx
-[ 	]*[a-f0-9]+:[ 	]*66 41 0f ae f2[ 	]*tpause r10
+[ 	]*[a-f0-9]+:[ 	]*f2 0f ae f1[ 	]*umwait ecx
+[ 	]*[a-f0-9]+:[ 	]*f2 0f ae f1[ 	]*umwait ecx
+[ 	]*[a-f0-9]+:[ 	]*f2 41 0f ae f2[ 	]*umwait r10d
+[ 	]*[a-f0-9]+:[ 	]*f2 41 0f ae f2[ 	]*umwait r10d
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae f1[ 	]*tpause ecx
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae f1[ 	]*tpause ecx
+[ 	]*[a-f0-9]+:[ 	]*66 41 0f ae f2[ 	]*tpause r10d
+[ 	]*[a-f0-9]+:[ 	]*66 41 0f ae f2[ 	]*tpause r10d
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-waitpkg.d b/gas/testsuite/gas/i386/x86-64-waitpkg.d
index 0930aa2829..a10a8cde31 100644
--- a/gas/testsuite/gas/i386/x86-64-waitpkg.d
+++ b/gas/testsuite/gas/i386/x86-64-waitpkg.d
@@ -12,8 +12,12 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*f3 0f ae f0[ 	]*umonitor %rax
 [ 	]*[a-f0-9]+:[ 	]*f3 41 0f ae f2[ 	]*umonitor %r10
 [ 	]*[a-f0-9]+:[ 	]*67 f3 41 0f ae f2[ 	]*umonitor %r10d
-[ 	]*[a-f0-9]+:[ 	]*f2 0f ae f1[ 	]*umwait %rcx
-[ 	]*[a-f0-9]+:[ 	]*f2 41 0f ae f2[ 	]*umwait %r10
-[ 	]*[a-f0-9]+:[ 	]*66 0f ae f1[ 	]*tpause %rcx
-[ 	]*[a-f0-9]+:[ 	]*66 41 0f ae f2[ 	]*tpause %r10
+[ 	]*[a-f0-9]+:[ 	]*f2 0f ae f1[ 	]*umwait %ecx
+[ 	]*[a-f0-9]+:[ 	]*f2 0f ae f1[ 	]*umwait %ecx
+[ 	]*[a-f0-9]+:[ 	]*f2 41 0f ae f2[ 	]*umwait %r10d
+[ 	]*[a-f0-9]+:[ 	]*f2 41 0f ae f2[ 	]*umwait %r10d
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae f1[ 	]*tpause %ecx
+[ 	]*[a-f0-9]+:[ 	]*66 0f ae f1[ 	]*tpause %ecx
+[ 	]*[a-f0-9]+:[ 	]*66 41 0f ae f2[ 	]*tpause %r10d
+[ 	]*[a-f0-9]+:[ 	]*66 41 0f ae f2[ 	]*tpause %r10d
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-waitpkg.s b/gas/testsuite/gas/i386/x86-64-waitpkg.s
index 7899c39ba8..9c6484894b 100644
--- a/gas/testsuite/gas/i386/x86-64-waitpkg.s
+++ b/gas/testsuite/gas/i386/x86-64-waitpkg.s
@@ -5,7 +5,11 @@ _start:
 	umonitor %rax
 	umonitor %r10
 	umonitor %r10d
+	umwait %ecx
 	umwait %rcx
 	umwait %r10
+	umwait %r10d
+	tpause %ecx
 	tpause %rcx
 	tpause %r10
+	tpause %r10d
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index d6fb42a1de..7416569d0d 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -4206,8 +4206,8 @@ static const struct dis386 prefix_table[][4] = {
   {
     { RM_TABLE (RM_0FAE_REG_6) },
     { "umonitor",	{ Eva }, PREFIX_OPCODE },
-    { "tpause",	{ Em }, PREFIX_OPCODE },
-    { "umwait",	{ Em }, PREFIX_OPCODE },
+    { "tpause",	{ Edq }, PREFIX_OPCODE },
+    { "umwait",	{ Edq }, PREFIX_OPCODE },
   },
 
   /* PREFIX_0FAE_REG_7 */
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 279a69762e..0f7c64d08b 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -5904,10 +5904,8 @@ pconfig, 0, 0x0f01c5, None, 3, CpuPCONFIG, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS
 umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOp0, { Reg16|Reg32 }
 umonitor, 1, 0xf30fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|AddrPrefixOp0|NoRex64, { Reg32|Reg64 }
 
-tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
-tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
+tpause, 1, 0x660fae, 0x6, 2, CpuWAITPKG, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64 }
 
-umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
-umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
+umwait, 1, 0xf20fae, 0x6, 2, CpuWAITPKG, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32|Reg64 }
 
 // WAITPKG instructions end.
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index f4bd25e8b0..0eb123a3a6 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -93810,41 +93810,13 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
-        0, 0, 0, 0, 0, 1, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      0, 0, 0 },
-    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
-	  0, 0, 0 } } } },
-  { "tpause", 1, 0x660fae, 0x6, 2,
-    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
-        0, 0, 0, 0, 1, 0, 0 } },
+        0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
-	  0, 0, 0 } } } },
-  { "umwait", 1, 0xf20fae, 0x6, 2,
-    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
-        0, 0, 0, 0, 0, 1, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
-      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      0, 0, 0 },
-    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0 } } } },
   { "umwait", 1, 0xf20fae, 0x6, 2,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -93852,13 +93824,13 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
-        0, 0, 0, 0, 1, 0, 0 } },
+        0, 0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0 } } } },
   { NULL, 0, 0, 0, 0,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-- 
2.14.3

Follow-Ups:
- Re: [PATCH 1/3] Enable Intel WAITPKG instructions.
  - From: Jan Beulich

References:
- [PATCH 1/3] Enable Intel WAITPKG instructions.
  - From: Tsimbalist, Igor V
- Re: [PATCH 1/3] Enable Intel WAITPKG instructions.
  - From: Jan Beulich
- Re: [PATCH 1/3] Enable Intel WAITPKG instructions.
  - From: H.J. Lu

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