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Re: Specify architecture for SPARC gas tests


    
    > I just checked and you can set OBJDUMPFLAGS before running
    > run_dump_test.  What about doing something like this in sparc.exp:
    >
    > proc set_tests_arch {arch} {
    >   global OBJDUMPFLAGS
    >
    >   if [istarget "sparc-solaris*"] {
    >      set OBJDUMPFLAGS "-msparc:$arch"
    >   }
    > }
    >
    > [...]
    >
    > set_tests_mach v9m8
    > run_dump_test "on"
    > run_list_test "on-diag" "-64"
    > ; ... other M8 tests
    >
    > set_tests_mach v9m
    > run_dump_test "xcrypto"
    > ; ... other M7 tests
    >
    > wdyt?
    
    works for me.  The following patch passed testing on both
    sparc-sun-solaris2.11 and sparcv9-sun-solaris2.11.
    
    At the occasion, I noticed that the ldtxa hadn't been run at all
    before.  It's now included as well.
    
    Ok for mainline?

Ok.  Thanks.
    
    Now, only two (quite weird) failures remain:
    
    FAIL: sparc LDM/STM/LDMA/STMA
    
    regexp_diff match failure
    regexp "^  1c:  c7 88 64 66     ldmuh  \[ %g1 \+ 0x66 \], %g3$"
    line   "  1c:   c7 88 64 66     ldmuh  [ 0x66 + %g1 ], %g3"
    regexp_diff match failure
    regexp "^  20:  c7 88 64 66     ldmuh  \[ %g1 \+ 0x66 \], %g3$"
    line   "  20:   c7 88 64 66     ldmuh  [ 0x66 + %g1 ], %g3"
    regexp_diff match failure
    regexp "^  30:  c7 88 68 66     ldmsw  \[ %g1 \+ 0x66 \], %g3$"
    line   "  30:   c7 88 68 66     ldmsw  [ 0x66 + %g1 ], %g3"
    regexp_diff match failure
    regexp "^  34:  c7 88 68 66     ldmsw  \[ %g1 \+ 0x66 \], %g3$"
    line   "  34:   c7 88 68 66     ldmsw  [ 0x66 + %g1 ], %g3"
    regexp_diff match failure
    regexp "^  44:  c7 88 6c 66     ldmuw  \[ %g1 \+ 0x66 \], %g3$"
    line   "  44:   c7 88 6c 66     ldmuw  [ 0x66 + %g1 ], %g3"
    regexp_diff match failure
    regexp "^  48:  c7 88 6c 66     ldmuw  \[ %g1 \+ 0x66 \], %g3$"
    line   "  48:   c7 88 6c 66     ldmuw  [ 0x66 + %g1 ], %g3"
    
    FAIL: sparc LDMF/STMF/LDMFA/STMFA
    
    regexp_diff match failure
    regexp "^  54:  c3 a8 7c 66     stmfd  %f32, \[ %g1 \+ 0x66 \]$"
    line   "  54:   c3 a8 7c 66     stmfd  %f32, [ 0x66 + %g1 ]"
    regexp_diff match failure
    regexp "^  58:  c3 a8 7c 66     stmfd  %f32, \[ %g1 \+ 0x66 \]$"
    line   "  58:   c3 a8 7c 66     stmfd  %f32, [ 0x66 + %g1 ]"
    
    I can see no pattern here: in the first case, ldmsh, ldmx, and st* are
    correct, in the second stmfs is.
    

I can't reproduce these two failures with a cross binutils...

It is indeed weird... the way the opcodes are organized in sparc-opc.c
should guarantee that the [d + i] variant is chosen by the disassembler,
provided the right architecture level is selected:

#define ldm(width,opm,flags)                                                 \
  { "ldm" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0), "[1+2],d", (flags), 0, HWCAP2_SPARC6, m8 }, \
  { "ldm" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, "[1],d", (flags), 0, HWCAP2_SPARC6, m8 }, /* ldm [rs1+%g0],d */ \
  { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[1+j],d", (flags), 0, HWCAP2_SPARC6, m8 }, \
  { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[j+1],d", (flags), 0, HWCAP2_SPARC6, m8 }, /* ldm [rs1+j],d  */ \
  { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|RS1_G0, "[j],d", (flags), 0, HWCAP2_SPARC6, m8 }, \
  { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|SIMM10(~0), "[1],d", (flags), 0, HWCAP2_SPARC6, m8 } /* ldm [rs1+0],d  */

You may want to debug what happens in the main `for' loop in
opcodes/sparc-dis.c:print_insn_sparc and why it is the "[j+1],d" entry
that is chosen.  I would do it myself but again I seem unable to
reproduce it :/


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