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[PATCH] RISC-V: Add support for addi that compresses to c.nop.
- From: Jim Wilson <jimw at sifive dot com>
- To: binutils at sourceware dot org
- Cc: Jim Wilson <jimw at sifive dot com>
- Date: Mon, 15 Jan 2018 14:57:29 -0800
- Subject: [PATCH] RISC-V: Add support for addi that compresses to c.nop.
- Authentication-results: sourceware.org; auth=none
This fixes a bug reported against the github riscv/riscv-binutils-gdb project.
https://github.com/riscv/riscv-binutils-gdb/issues/135
This fixes a minor oversight. An addi x0,x0,0 is a nop, and should compress
to c.nop when RVC support is enabled, but without this patch we always get
a 4-byte nop. With this patch, we get the expected 2-byte nop.
This was tested with rv{32,64}-{elf,linux} make check-{binutils,gas,ld}. There
were no regressions.
Committed.
Jim
gas/
* testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
* testsuite/gas/riscv/c-zero-imm.d: Likewise.
opcodes/
* riscv-opc.c (match_c_nop): New.
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
---
gas/testsuite/gas/riscv/c-zero-imm.d | 5 +++--
gas/testsuite/gas/riscv/c-zero-imm.s | 1 +
opcodes/riscv-opc.c | 8 ++++++++
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/gas/testsuite/gas/riscv/c-zero-imm.d b/gas/testsuite/gas/riscv/c-zero-imm.d
index ac47e8061d..c1389662e8 100644
--- a/gas/testsuite/gas/riscv/c-zero-imm.d
+++ b/gas/testsuite/gas/riscv/c-zero-imm.d
@@ -11,6 +11,7 @@ Disassembly of section .text:
[ ]+2:[ ]+4581[ ]+li[ ]+a1,0
[ ]+4:[ ]+8a01[ ]+andi[ ]+a2,a2,0
[ ]+6:[ ]+8a81[ ]+andi[ ]+a3,a3,0
-[ ]+8:[ ]+00070713[ ]+mv[ ]+a4,a4
-[ ]+c:[ ]+0781[ ]+addi[ ]+a5,a5,0
+[ ]+8:[ ]+0001[ ]+nop
+[ ]+a:[ ]+00070713[ ]+mv[ ]+a4,a4
+[ ]+e:[ ]+0781[ ]+addi[ ]+a5,a5,0
#...
diff --git a/gas/testsuite/gas/riscv/c-zero-imm.s b/gas/testsuite/gas/riscv/c-zero-imm.s
index 650313d7cb..a07baa4995 100644
--- a/gas/testsuite/gas/riscv/c-zero-imm.s
+++ b/gas/testsuite/gas/riscv/c-zero-imm.s
@@ -4,6 +4,7 @@
c.li a1,0
andi a2,a2,0
c.andi a3,0
+ addi x0,x0,0
# Don't let this compress to a hint.
addi a4,a4,0
# These are hints.
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 79e7214835..a4e4b26598 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -122,6 +122,13 @@ match_c_add_with_hint (const struct riscv_opcode *op, insn_t insn)
return match_opcode (op, insn) && ((insn & MASK_CRS2) != 0);
}
+static int
+match_c_nop (const struct riscv_opcode *op, insn_t insn)
+{
+ return (match_opcode (op, insn)
+ && (((insn & MASK_RD) >> OP_SH_RD) == 0));
+}
+
static int
match_c_addi16sp (const struct riscv_opcode *op, insn_t insn)
{
@@ -225,6 +232,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 },
{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
{"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
+{"addi", "C", "d,CU,0", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
{"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
--
2.14.1