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[committed] MIPS/BFD: Consistently mark the LSI CW4010 as a MIPS II processor
- From: "Maciej W. Rozycki" <macro at imgtec dot com>
- To: <binutils at sourceware dot org>
- Date: Mon, 26 Jun 2017 19:31:37 +0100
- Subject: [committed] MIPS/BFD: Consistently mark the LSI CW4010 as a MIPS II processor
- Authentication-results: sourceware.org; auth=none
Make BFD agree with GAS and mark the LSI MiniRISC CW4010 processor core
(for an odd reason referred to as LSI R4010 across our code base) as a
MIPS II processor in BFD as well, fixing a bug that has been there since
forever and addressing linker warnings like:
$ as -m4010 empty.s -o 4010.o
$ ld -r 4010.o -o 4010-r.o
ld: 4010.o: warning: Inconsistent ISA between e_flags and .MIPS.abiflags
$
due to the ISA level being recorded as MIPS III in ELF file header's
`e_flags' vs MIPS II in the MIPS ABI Flags section:
$ readelf -Ah 4010.o
ELF Header:
Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, big endian
Version: 1 (current)
OS/ABI: UNIX - System V
ABI Version: 0
Type: REL (Relocatable file)
Machine: MIPS R3000
Version: 0x1
Entry point address: 0x0
Start of program headers: 0 (bytes into file)
Start of section headers: 348 (bytes into file)
Flags: 0x20821000, 4010, o32, mips3
Size of this header: 52 (bytes)
Size of program headers: 0 (bytes)
Number of program headers: 0
Size of section headers: 40 (bytes)
Number of section headers: 11
Section header string table index: 10
Attribute Section: gnu
File Attributes
Tag_GNU_MIPS_ABI_FP: Hard float (double precision)
MIPS ABI Flags Version: 0
ISA: MIPS2
GPR size: 32
CPR1 size: 32
CPR2 size: 0
FP ABI: Hard float (double precision)
ISA Extension: LSI R4010
ASEs:
None
FLAGS 1: 00000000
FLAGS 2: 00000000
$
Available documentation[1][2] clearly indicates the LSI CW4010 processor
is only backwards compatible with the MIPS R4000 processor as far as the
latter's 32-bit instructions are concerned and consequently can only be
considered a MIPS II ISA implementation (with vendor extensions).
This fixes an LD testsuite failure:
FAIL: MIPS incompatible objects: "-march=r4010 -32" "-march=r4650 -32"
triggered for the `mips-sgi-irix5' and `mips-sgi-irix6' targets.
References:
[1] Paul Cobb, Bob Caulk, Joe Cesana, "The MiniRISC CW4010: A
Superscalar MIPS Processor ASIC Core", LSI Logic, July 1995,
presented at Hot Chips VII, Stanford University, Stanford,
California, August 1995
[2] "MiniRISC MR4010 Superscalar Microprocessor Reference Device", LSI
Logic, November 1996, Doc. No. DB09-000028-00, Order No. C15017
bfd/
* cpu-mips.c (arch_info_struct): Mark the 4010 32-bit.
* elfxx-mips.c (mips_set_isa_flags) <bfd_mach_mips4010>: Set
E_MIPS_ARCH_2 rather than E_MIPS_ARCH_3 in `e_flags'.
(mips_mach_extensions): Mark `bfd_mach_mips4010' as extending
`bfd_mach_mips6000' rather than `bfd_mach_mips4000'.
ld/
* testsuite/ld-mips-elf/lsi-4010-isa.d: New test.
* ld/testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
---
I have discovered it in the course of preparing the test suite part of an
upcoming feature and decided to fix rather than avoiding or papering over,
even though after these many years there is clearly little if any interest
still left in CW4010 support, which hasn't been ever made complete even,
e.g. the MAX and MIN vendor-specific instructions have never made it to
our opcode table.
Maciej
binutils-mips-bfd-r4010-isa2.diff
Index: binutils/bfd/cpu-mips.c
===================================================================
--- binutils.orig/bfd/cpu-mips.c 2017-06-26 15:55:29.493674836 +0100
+++ binutils/bfd/cpu-mips.c 2017-06-26 15:55:35.064036622 +0100
@@ -114,7 +114,7 @@ static const bfd_arch_info_type arch_inf
N (32, 32, bfd_mach_mips3000, "mips:3000", FALSE, NN(I_mips3000)),
N (32, 32, bfd_mach_mips3900, "mips:3900", FALSE, NN(I_mips3900)),
N (64, 64, bfd_mach_mips4000, "mips:4000", FALSE, NN(I_mips4000)),
- N (64, 64, bfd_mach_mips4010, "mips:4010", FALSE, NN(I_mips4010)),
+ N (32, 32, bfd_mach_mips4010, "mips:4010", FALSE, NN(I_mips4010)),
N (64, 64, bfd_mach_mips4100, "mips:4100", FALSE, NN(I_mips4100)),
N (64, 64, bfd_mach_mips4111, "mips:4111", FALSE, NN(I_mips4111)),
N (64, 64, bfd_mach_mips4120, "mips:4120", FALSE, NN(I_mips4120)),
Index: binutils/bfd/elfxx-mips.c
===================================================================
--- binutils.orig/bfd/elfxx-mips.c 2017-06-26 15:55:29.507814474 +0100
+++ binutils/bfd/elfxx-mips.c 2017-06-26 15:55:35.076324394 +0100
@@ -11863,6 +11863,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_2;
break;
+ case bfd_mach_mips4010:
+ val = E_MIPS_ARCH_2 | E_MIPS_MACH_4010;
+ break;
+
case bfd_mach_mips4000:
case bfd_mach_mips4300:
case bfd_mach_mips4400:
@@ -11870,10 +11874,6 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_3;
break;
- case bfd_mach_mips4010:
- val = E_MIPS_ARCH_3 | E_MIPS_MACH_4010;
- break;
-
case bfd_mach_mips4100:
val = E_MIPS_ARCH_3 | E_MIPS_MACH_4100;
break;
@@ -14024,7 +14024,6 @@ static const struct mips_mach_extension
{ bfd_mach_mips4400, bfd_mach_mips4000 },
{ bfd_mach_mips4300, bfd_mach_mips4000 },
{ bfd_mach_mips4100, bfd_mach_mips4000 },
- { bfd_mach_mips4010, bfd_mach_mips4000 },
{ bfd_mach_mips5900, bfd_mach_mips4000 },
/* MIPS32 extensions. */
@@ -14033,6 +14032,7 @@ static const struct mips_mach_extension
/* MIPS II extensions. */
{ bfd_mach_mips4000, bfd_mach_mips6000 },
{ bfd_mach_mipsisa32, bfd_mach_mips6000 },
+ { bfd_mach_mips4010, bfd_mach_mips6000 },
/* MIPS I extensions. */
{ bfd_mach_mips6000, bfd_mach_mips3000 },
Index: binutils/ld/testsuite/ld-mips-elf/lsi-4010-isa.d
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ binutils/ld/testsuite/ld-mips-elf/lsi-4010-isa.d 2017-06-26 15:55:38.904335536 +0100
@@ -0,0 +1,23 @@
+#readelf: -Ah
+#name: LSI 4010 processor ISA level
+#source: empty.s
+#as: -EB -32 -m4010
+#ld: -EB -r
+
+ELF Header:
+#...
+ Flags: 0x1082[01]000, 4010(?:, o32)?, mips2
+#...
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS2
+GPR size: 32
+CPR1 size: 32
+CPR2 size: 0
+FP ABI: .*
+ISA Extension: LSI R4010
+ASEs:
+ None
+FLAGS 1: .*
+FLAGS 2: .*
Index: binutils/ld/testsuite/ld-mips-elf/mips-elf.exp
===================================================================
--- binutils.orig/ld/testsuite/ld-mips-elf/mips-elf.exp 2017-06-26 15:55:29.340687376 +0100
+++ binutils/ld/testsuite/ld-mips-elf/mips-elf.exp 2017-06-26 15:55:38.913540503 +0100
@@ -1176,3 +1176,6 @@ run_ld_link_tests [list \
{{objdump {-d --prefix-addresses} pr21334.dd} \
{readelf -A pr21334.gd}} \
"pr21334"]]
+
+# Check that the ISA level is consistently II for the LSI 4010.
+run_dump_test "lsi-4010-isa" [list [list ld $abi_ldflags(o32)]]