Re: [PATCH] PowerPC VLE changes

[Alan Modra <amodra at gmail dot com>]

On Tue, Apr 04, 2017 at 01:33:44PM +0300, Alexander Fedotov wrote:
> Another one is related to VLE also:

Neither of these patches applied, because your mail client wrapped
lines and converted tabs to spaces.  The second didn't compile,
lacking a definition for ELEV, and ChangeLog entries were missing.
I've fixed these problems and added to the VLE gas testsuite.
Committed.

opcodes/
	* ppc-opc.c (ELEV): Define.
	(vle_opcodes): Add se_rfgi and e_sc.
	(powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
	for E200Z4.
gas/
	* testsuite/gas/ppc/vle.s: Format.  Add se_rfgi and e_sc.
	* testsuite/gas/ppc/vle.d: Update.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index a31c799..c5531a7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2017-04-22  Alan Modra  <amodra@gmail.com>
+
+	* testsuite/gas/ppc/vle.s: Format.  Add se_rfgi and e_sc.
+	* testsuite/gas/ppc/vle.d: Update.
+
 2017-04-21  Nick Clifton  <nickc@redhat.com>
 
 	PR binutils/21380
diff --git a/gas/testsuite/gas/ppc/vle.d b/gas/testsuite/gas/ppc/vle.d
index ea75658..dcc2cc3 100644
--- a/gas/testsuite/gas/ppc/vle.d
+++ b/gas/testsuite/gas/ppc/vle.d
@@ -148,3 +148,7 @@ Disassembly of section \.text:
  194:	e9 c2       	se_bl   118 <middle_label>
  196:	79 ff ff 82 	e_b     118 <middle_label>
  19a:	79 ff fe 67 	e_bl    0 <start_label>
+ 19e:	00 0c       	se_rfgi
+ 1a0:	7c 00 00 48 	e_sc    
+ 1a4:	7c 00 00 48 	e_sc    
+ 1a8:	7c 00 08 48 	e_sc    1
diff --git a/gas/testsuite/gas/ppc/vle.s b/gas/testsuite/gas/ppc/vle.s
index cab6120..4354c1f 100644
--- a/gas/testsuite/gas/ppc/vle.s
+++ b/gas/testsuite/gas/ppc/vle.s
@@ -41,144 +41,148 @@
 	.equ	r31,31
 	.equ	r32,32
 	.equ	rsp,r1
- 
 
-start_label:	
+
+start_label:
 	e_add16i	r4,r3,27
-	e_add2i. 	r0,0x3456
-	e_add2is 	r1,0x4321
-	e_addi. 	r2,r6,SCI0
-	e_addi 		r3,r5,SCI1
-	e_addic. 	r4,r4,SCI2
-	e_addic 	r7,r8,SCI3
-	e_and2i. 	r9,0xfeed
-	e_and2is. 	r10,5
-	e_andi. 	r11,r13,0x39
-	e_andi 		r12,r15,SCI2
-	e_b 		middle_label
-	e_bl 		extern_subr
-	e_bc 		0,3,start_label
-	e_bcl 		1,15,extern_subr
+	e_add2i.	r0,0x3456
+	e_add2is	r1,0x4321
+	e_addi.		r2,r6,SCI0
+	e_addi		r3,r5,SCI1
+	e_addic.	r4,r4,SCI2
+	e_addic		r7,r8,SCI3
+	e_and2i.	r9,0xfeed
+	e_and2is.	r10,5
+	e_andi.		r11,r13,0x39
+	e_andi		r12,r15,SCI2
+	e_b		middle_label
+	e_bl		extern_subr
+	e_bc		0,3,start_label
+	e_bcl		1,15,extern_subr
 	e_cmp16i	r2,0x3333
 	e_cmpi		2,r6,SCI1
 	e_cmph		1,r7,r11
 	e_cmph16i	r12,0xfdef
 	e_cmphl		0,r6,r8
 	e_cmphl16i	r13,0x1234
-	e_cmpl16i 	r1, 0xfee0
-	e_cmpli 	1,r3,SCI3
-	e_crand 	0x1d,3,0
-	e_crandc 	0,2,0x1d
-	e_creqv 	15,16,17
-	e_crnand 	0xf,0,3
-	e_crnor 	0xf,0,3
-	e_cror 		12,13,14
-	e_crorc 	19,18,17
-	e_crxor 	0,0,0
-	e_lbz 		r7,0xffffcc0d(r3)
-	e_lbzu 		r7,-52(r5)
-	e_lha 		r8,0x1ff(r10)
-	e_lhau 		r8,-1(r1)
+	e_cmpl16i	r1, 0xfee0
+	e_cmpli		1,r3,SCI3
+	e_crand		0x1d,3,0
+	e_crandc	0,2,0x1d
+	e_creqv		15,16,17
+	e_crnand	0xf,0,3
+	e_crnor		0xf,0,3
+	e_cror		12,13,14
+	e_crorc		19,18,17
+	e_crxor		0,0,0
+	e_lbz		r7,0xffffcc0d(r3)
+	e_lbzu		r7,-52(r5)
+	e_lha		r8,0x1ff(r10)
+	e_lhau		r8,-1(r1)
 	e_lhz		r7,6200(r0)
 	e_lhzu		r7,62(r0)
-	e_li 		r0,0x33333
-	e_lis 		r1,0x3333
-	e_lmw 		r5,24(r3)
-	e_lwz 		r5,10024(r3)
-	e_lwzu 		r6,0x72(r2)
-	e_mcrf 		1,6
-	e_mulli 	r9,r10,SCI0
-	e_mull2i 	r1,0x668
-	e_or2i 		r5,0x2345
-	e_or2is 	r5,0xa345
-	e_ori. 		r7,r9,SCI0
-	e_ori 		r7,r8,SCI1
-	e_rlw 		r18, r22,r0
-	e_rlw. 		r8, r2,r0
-	e_rlwi 		r20,r3,21
-	e_rlwi. 	r2,r3,21
-	e_rlwimi 	r4,r19,13,8,15
-	e_rlwinm 	r4,r1,13,1,17
-	e_slwi 		r12,r19,6
-	e_slwi. 	r12,r10,20
-	e_srwi 		r0,r1,16
-	e_srwi. 	r0,r1,11
-	e_stb 		r3,22000(r1)
-	e_stbu 		r19,-4(r22)
-	e_sth 		r0,666(r21)
-	e_sthu 		r1,-1(r23)
-	e_stmw 		r0,4(r3)
-	e_stw 		r3,16161(r0)
-	e_stwu 		r22,0xffffffee(r4)
-	e_subfic 	r0,r21,SCI2
-	e_subfic. 	r22,r0,SCI3
-	e_xori 		r21,r3,SCI1
-	e_xori. 	r0,r20,SCI0
-middle_label:	
-	se_add 		r31,r7
-	se_addi 	r28,0x1f
-	se_and 		r0,r1
-	se_and. 	r1,r0
-	se_andc 	r2, r3
-	se_andi 	r4,0x11
-	se_b 		middle_label
-	se_bl 		extern_subr
-	se_bc 		1,3,not_end_label
-	se_bclri 	r27,0x12
-	se_bctr 
-	se_bctrl 
-	se_bgeni 	r7,17
-	se_blr 
-	se_blrl 
-	se_bmaski 	r6,0
-	se_bseti 	r0,1
-	se_btsti 	r4,7
-	se_cmp 		r0,r1
-	se_cmph 	r31,r28
-	se_cmphl 	r1,r25
-	se_cmpi 	r3,22
-	se_cmpl 	r6,r7
-	se_cmpli 	r28,0xc
-	se_extsb 	r1
-	se_extsh 	r2
-	se_extzb 	r30
-	se_extzh 	r24
+	e_li		r0,0x33333
+	e_lis		r1,0x3333
+	e_lmw		r5,24(r3)
+	e_lwz		r5,10024(r3)
+	e_lwzu		r6,0x72(r2)
+	e_mcrf		1,6
+	e_mulli		r9,r10,SCI0
+	e_mull2i	r1,0x668
+	e_or2i		r5,0x2345
+	e_or2is		r5,0xa345
+	e_ori.		r7,r9,SCI0
+	e_ori		r7,r8,SCI1
+	e_rlw		r18, r22,r0
+	e_rlw.		r8, r2,r0
+	e_rlwi		r20,r3,21
+	e_rlwi.		r2,r3,21
+	e_rlwimi	r4,r19,13,8,15
+	e_rlwinm	r4,r1,13,1,17
+	e_slwi		r12,r19,6
+	e_slwi.		r12,r10,20
+	e_srwi		r0,r1,16
+	e_srwi.		r0,r1,11
+	e_stb		r3,22000(r1)
+	e_stbu		r19,-4(r22)
+	e_sth		r0,666(r21)
+	e_sthu		r1,-1(r23)
+	e_stmw		r0,4(r3)
+	e_stw		r3,16161(r0)
+	e_stwu		r22,0xffffffee(r4)
+	e_subfic	r0,r21,SCI2
+	e_subfic.	r22,r0,SCI3
+	e_xori		r21,r3,SCI1
+	e_xori.		r0,r20,SCI0
+middle_label:
+	se_add		r31,r7
+	se_addi		r28,0x1f
+	se_and		r0,r1
+	se_and.		r1,r0
+	se_andc		r2, r3
+	se_andi		r4,0x11
+	se_b		middle_label
+	se_bl		extern_subr
+	se_bc		1,3,not_end_label
+	se_bclri	r27,0x12
+	se_bctr
+	se_bctrl
+	se_bgeni	r7,17
+	se_blr
+	se_blrl
+	se_bmaski	r6,0
+	se_bseti	r0,1
+	se_btsti	r4,7
+	se_cmp		r0,r1
+	se_cmph		r31,r28
+	se_cmphl	r1,r25
+	se_cmpi		r3,22
+	se_cmpl		r6,r7
+	se_cmpli	r28,0xc
+	se_extsb	r1
+	se_extsh	r2
+	se_extzb	r30
+	se_extzh	r24
 not_end_label:
-	se_illegal 
-	se_isync 
-	se_lbz 		r1,8(r24)
-	se_lhz 		r24,18(r4)
+	se_illegal
+	se_isync
+	se_lbz		r1,8(r24)
+	se_lhz		r24,18(r4)
 	se_li		r4,0x4f
-	se_lwz 		r6,60(r0)
-	se_mfar 	r7,r8
-	se_mfctr 	r3
-	se_mflr 	r4
-	se_mr 		r31,r0
-	se_mtar 	r23,r2
-	se_mtctr 	r6
-	se_mtlr 	r31
+	se_lwz		r6,60(r0)
+	se_mfar		r7,r8
+	se_mfctr	r3
+	se_mflr		r4
+	se_mr		r31,r0
+	se_mtar		r23,r2
+	se_mtctr	r6
+	se_mtlr		r31
 	se_mullw	r3,r4
-	se_neg 		r24
-	se_not 		r25
-	se_or		r0,r1 
-	se_rfci 
-	se_rfdi 
-	se_rfi 
-	se_sc 
-	se_slw 		r5,r6
-	se_slwi 	r7,7
-	se_sraw 	r6,r30
-	se_srawi 	r25,8
-	se_srw 		r30,r0
-	se_srwi 	r29,25
-	se_stb 		r0,10(r2)
-	se_sth 		r1,12(r30)
-	se_stw 		r7,0(r29)
-	se_sub 		r1,r2
-	se_subf 	r29,r26
-	se_subi 	r7,24
+	se_neg		r24
+	se_not		r25
+	se_or		r0,r1
+	se_rfci
+	se_rfdi
+	se_rfi
+	se_sc
+	se_slw		r5,r6
+	se_slwi		r7,7
+	se_sraw		r6,r30
+	se_srawi	r25,8
+	se_srw		r30,r0
+	se_srwi		r29,25
+	se_stb		r0,10(r2)
+	se_sth		r1,12(r30)
+	se_stw		r7,0(r29)
+	se_sub		r1,r2
+	se_subf		r29,r26
+	se_subi		r7,24
 end_label:
-	se_subi. 	r25,19
-	se_bl 		middle_label
-	e_b 		middle_label
-	e_bl 		start_label
+	se_subi.	r25,19
+	se_bl		middle_label
+	e_b		middle_label
+	e_bl		start_label
+	se_rfgi
+	e_sc
+	e_sc		0
+	e_sc		1
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8595f2d..53ebe54 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2017-04-22  Alexander Fedotov  <alfedotov@gmail.com>
+	    Alan Modra  <amodra@gmail.com>
+
+	* ppc-opc.c (ELEV): Define.
+	(vle_opcodes): Add se_rfgi and e_sc.
+	(powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
+	for E200Z4.
+
 2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
 	* sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 55e6bed..426261a 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -652,8 +652,10 @@ const struct powerpc_operand powerpc_operands[] =
 #define SH6_MASK ((0x1f << 11) | (1 << 1))
   { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
 
-  /* The SH field of the tlbwe instruction, which is optional.  */
+  /* The SH field of some variants of the tlbre and tlbwe
+     instructions, and the ELEV field of the e_sc instruction.  */
 #define SHO SH6 + 1
+#define ELEV SHO
   { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
   /* The SI field in a D form instruction.  */
@@ -5874,7 +5876,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mcrxr",	X(31,512),	XBFRARB_MASK, COM,	POWER7,		{BF}},
 
 {"lbdcbx",	X(31,514),	X_MASK,      E200Z4,	0,		{RT, RA, RB}},
-{"lbdx",	X(31,515),	X_MASK,	     E500MC,	0,		{RT, RA, RB}},
+{"lbdx",	X(31,515),	X_MASK,	 E500MC|E200Z4,	0,		{RT, RA, RB}},
 
 {"bblels",	X(31,518),	X_MASK,	     PPCBRLK,	0,		{0}},
 
@@ -5925,7 +5927,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"maskir.",	XRC(31,541,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
 
 {"lhdcbx",	X(31,546),	X_MASK,      E200Z4,	0,		{RT, RA, RB}},
-{"lhdx",	X(31,547),	X_MASK,	     E500MC,	0,		{RT, RA, RB}},
+{"lhdx",	X(31,547),	X_MASK,	 E500MC|E200Z4,	0,		{RT, RA, RB}},
 
 {"lvtrx",	X(31,549),	X_MASK,	     E6500,	0,		{VD, RA0, RB}},
 
@@ -5949,7 +5951,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mcrxrx",	X(31,576),     XBFRARB_MASK, POWER9,	0,		{BF}},
 
 {"lwdcbx",	X(31,578),	X_MASK,      E200Z4,	0,		{RT, RA, RB}},
-{"lwdx",	X(31,579),	X_MASK,	     E500MC,	0,		{RT, RA, RB}},
+{"lwdx",	X(31,579),	X_MASK,	 E500MC|E200Z4,	0,		{RT, RA, RB}},
 
 {"lvtlx",	X(31,581),	X_MASK,	     E6500,	0,		{VD, RA0, RB}},
 
@@ -6000,7 +6002,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"lfdux",	X(31,631),	X_MASK,	     COM,	PPCEFS,		{FRT, RAS, RB}},
 
 {"stbdcbx",	X(31,642),	X_MASK,      E200Z4,	0,		{RS, RA, RB}},
-{"stbdx",	X(31,643),	X_MASK,	     E500MC,	0,		{RS, RA, RB}},
+{"stbdx",	X(31,643),	X_MASK,	 E500MC|E200Z4,	0,		{RS, RA, RB}},
 
 {"stvlx",	X(31,647),	X_MASK,	     CELL,	0,		{VS, RA0, RB}},
 {"stbfcmux",	APU(31,647,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},
@@ -6038,7 +6040,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sre.",	XRC(31,665,1),	X_MASK,	     M601,	0,		{RA, RS, RB}},
 
 {"sthdcbx",	X(31,674),	X_MASK,      E200Z4,	0,		{RS, RA, RB}},
-{"sthdx",	X(31,675),	X_MASK,	     E500MC,	0,		{RS, RA, RB}},
+{"sthdx",	X(31,675),	X_MASK,	 E500MC|E200Z4,	0,		{RS, RA, RB}},
 
 {"stvfrx",	X(31,677),	X_MASK,	     E6500,	0,		{VS, RA0, RB}},
 
@@ -6056,7 +6058,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"sriq.",	XRC(31,696,1),	X_MASK,	     M601,	0,		{RA, RS, SH}},
 
 {"stwdcbx",	X(31,706),	X_MASK,	     E200Z4,	0,		{RS, RA, RB}},
-{"stwdx",	X(31,707),	X_MASK,	     E500MC,	0,		{RS, RA, RB}},
+{"stwdx",	X(31,707),	X_MASK,	 E500MC|E200Z4,	0,		{RS, RA, RB}},
 
 {"stvflx",	X(31,709),	X_MASK,	     E6500,	0,		{VS, RA0, RB}},
 
@@ -7109,6 +7111,7 @@ const struct powerpc_opcode vle_opcodes[] = {
 {"se_rfci",	C(9),		C_MASK,		PPCVLE,	0,		{}},
 {"se_rfdi",	C(10),		C_MASK,		PPCVLE,	0,		{}},
 {"se_rfmci",	C(11),		C_MASK, PPCRFMCI|PPCVLE, 0,		{}},
+{"se_rfgi",	C(12),		C_MASK,		PPCVLE,	0,		{}},
 {"se_not",	SE_R(0,2),	SE_R_MASK,	PPCVLE,	0,		{RX}},
 {"se_neg",	SE_R(0,3),	SE_R_MASK,	PPCVLE,	0,		{RX}},
 {"se_mflr",	SE_R(0,8),	SE_R_MASK,	PPCVLE,	0,		{RX}},
@@ -7266,6 +7269,7 @@ const struct powerpc_opcode vle_opcodes[] = {
 {"e_btl",	EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0,		{BI32,B15}},
 
 {"e_cmph",	X(31,14),	X_MASK,		PPCVLE,	0,		{CRD, RA, RB}},
+{"e_sc",	X(31,36),	XRTRA_MASK,	PPCVLE,	0,		{ELEV}},
 {"e_cmphl",	X(31,46),	X_MASK,		PPCVLE,	0,		{CRD, RA, RB}},
 {"e_crandc",	XL(31,129),	XL_MASK,	PPCVLE,	0,		{BT, BA, BB}},
 {"e_crnand",	XL(31,225),	XL_MASK,	PPCVLE,	0,		{BT, BA, BB}},


-- 
Alan Modra
Australia Development Lab, IBM