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Re: [PATCHv2] [Bug 20868] ld: aarch64: fix GD->IE relaxation in ilp32 mode

On Tue, Nov 29, 2016 at 04:45:12PM +0000, Jiong Wang wrote:
> On 28/11/16 17:45, Yury Norov wrote:
> >LD detects the access to TLS that it can optimize, but does it wrong
> >in ilp32 mode - actual address differs from expected.
> >
> >It's because ld it calculates the address with "ldr  x0, [x0, #:gottprel_lo12:var]"
> >which is correct for lp64, but for ilp32 it should be "ldr  w0, [x0, #:gottprel_lo12:var]".
> >This patch fixes it by checking arch info. Also it replaces "add x0, x1, x0" with
> >"add  w0, w1, w0".  This instruction doesn't make troubles now, but in ilp32 mode
> >32-bit registers should be used in this case.
> >
> >Test that reproduses the bug is here:
> >
> >
> >v2: add test to the testsuite.
> >
> >	* bfd/elfnn-aarch64.c: Fix gd-ie relocation in ilp32 mode
> >	* ld/testsuite/ld-aarch64/aarch64-elf.exp: Add new test
> >	* ld/testsuite/ld-aarch64/relocs-ilp32.ld: New file
> >	* ld/testsuite/ld-aarch64/tls-relax-gd-ie-ilp32.d: Likewise.
> Looks good to me though I can't approve,  just don't forget add PR
> target/20868 in your changelog.

Great. It's important for ILP32 as it fixes 5 extra failures of ~23
in glibc testsuite. Who can take it? I'd ping him personally.

Is my understanding correct that I have your ack?


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