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... just like is already the case for 16- and 32-bit movzb: I can't see
why omitting suffixes on this (and movs{b,w,l}) is not allowed, when it
is allowed for all other instructions where the suffix is redundant
with (one of) the operands.
gas/testsuite/
2016-06-30 Jan Beulich <jbeulich@suse.com>
* gas/i386/movz.s: New.
* gas/i386/movz32.d: New.
* gas/i386/movz64.d: New.
* gas/i386/i386.exp: Run new tests. Invoke as for 64-bits tests
with "--defsym x86_64=1 --strip-local-absolute".
opcodes/
2016-06-30 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
(movzb): Adjust to cover all permitted suffixes.
(movzw): New.
* i386-tbl.h: Re-generate.
--- 2016-06-30/gas/testsuite/gas/i386/i386.exp 2016-06-30 11:25:50.000000000 +0200
+++ 2016-06-30/gas/testsuite/gas/i386/i386.exp 2016-06-30 12:04:26.000000000 +0200
@@ -59,6 +59,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "amd"
run_dump_test "katmai"
run_dump_test "jump"
+ run_dump_test "movz32"
run_dump_test "relax-1"
run_dump_test "relax-2"
run_dump_test "ssemmx2"
@@ -482,7 +483,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
global ASFLAGS
set old_ASFLAGS "$ASFLAGS"
- set ASFLAGS "$ASFLAGS --64"
+ set ASFLAGS "$ASFLAGS --64 --defsym x86_64=1 --strip-local-absolute"
run_dump_test "x86_64"
run_dump_test "x86_64-intel"
@@ -506,6 +507,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-segovr"
run_list_test "x86-64-inval-seg" "-al"
run_dump_test "x86-64-branch"
+ run_dump_test "movz64"
run_dump_test "x86-64-relax-1"
run_dump_test "svme64"
run_dump_test "x86-64-amdfam10"
--- 2016-06-30/gas/testsuite/gas/i386/movz.s 1970-01-01 01:00:00.000000000 +0100
+++ 2016-06-30/gas/testsuite/gas/i386/movz.s 2016-06-30 12:04:26.000000000 +0200
@@ -0,0 +1,33 @@
+ .text
+movz:
+ movzb %al,%ax
+ movzb (%eax),%ax
+ movzb %al,%eax
+ movzb (%eax),%eax
+.ifdef x86_64
+ movzb %al,%rax
+ movzb (%rax),%rax
+.endif
+
+ movzbw %al,%ax
+ movzbw (%eax),%ax
+ movzbl %al,%eax
+ movzbl (%eax),%eax
+.ifdef x86_64
+ movzbq %al,%rax
+ movzbq (%rax),%rax
+.endif
+
+ movzw %ax,%eax
+ movzw (%eax),%eax
+.ifdef x86_64
+ movzw %ax,%rax
+ movzw (%rax),%rax
+.endif
+
+ movzwl %ax,%eax
+ movzwl (%eax),%eax
+.ifdef x86_64
+ movzwq %ax,%rax
+ movzwq (%rax),%rax
+.endif
--- 2016-06-30/gas/testsuite/gas/i386/movz32.d 1970-01-01 01:00:00.000000000 +0100
+++ 2016-06-30/gas/testsuite/gas/i386/movz32.d 2016-06-30 12:04:26.000000000 +0200
@@ -0,0 +1,22 @@
+#objdump: -d
+#source: movz.s
+#name: x86 mov with zero-extend (32-bit object)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <movz>:
+[ ]*[a-f0-9]+: 66 0f b6 c0 * movzbw? %al,%ax
+[ ]*[a-f0-9]+: 66 0f b6 00 * movzbw? \(%eax\),%ax
+[ ]*[a-f0-9]+: 0f b6 c0 * movzbl? %al,%eax
+[ ]*[a-f0-9]+: 0f b6 00 * movzbl? \(%eax\),%eax
+[ ]*[a-f0-9]+: 66 0f b6 c0 * movzbw? %al,%ax
+[ ]*[a-f0-9]+: 66 0f b6 00 * movzbw? \(%eax\),%ax
+[ ]*[a-f0-9]+: 0f b6 c0 * movzbl? %al,%eax
+[ ]*[a-f0-9]+: 0f b6 00 * movzbl? \(%eax\),%eax
+[ ]*[a-f0-9]+: 0f b7 c0 * movzwl? %ax,%eax
+[ ]*[a-f0-9]+: 0f b7 00 * movzwl? \(%eax\),%eax
+[ ]*[a-f0-9]+: 0f b7 c0 * movzwl? %ax,%eax
+[ ]*[a-f0-9]+: 0f b7 00 * movzwl? \(%eax\),%eax
+#pass
--- 2016-06-30/gas/testsuite/gas/i386/movz64.d 1970-01-01 01:00:00.000000000 +0100
+++ 2016-06-30/gas/testsuite/gas/i386/movz64.d 2016-06-30 12:04:26.000000000 +0200
@@ -0,0 +1,30 @@
+#objdump: -d
+#source: movz.s
+#name: x86 mov with zero-extend (64-bit object)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <movz>:
+[ ]*[a-f0-9]+: 66 0f b6 c0 * movzbw? %al,%ax
+[ ]*[a-f0-9]+: 67 66 0f b6 00 * movzbw? \(%eax\),%ax
+[ ]*[a-f0-9]+: 0f b6 c0 * movzbl? %al,%eax
+[ ]*[a-f0-9]+: 67 0f b6 00 * movzbl? \(%eax\),%eax
+[ ]*[a-f0-9]+: 48 0f b6 c0 * movzbq? %al,%rax
+[ ]*[a-f0-9]+: 48 0f b6 00 * movzbq? \(%rax\),%rax
+[ ]*[a-f0-9]+: 66 0f b6 c0 * movzbw? %al,%ax
+[ ]*[a-f0-9]+: 67 66 0f b6 00 * movzbw? \(%eax\),%ax
+[ ]*[a-f0-9]+: 0f b6 c0 * movzbl? %al,%eax
+[ ]*[a-f0-9]+: 67 0f b6 00 * movzbl? \(%eax\),%eax
+[ ]*[a-f0-9]+: 48 0f b6 c0 * movzbq? %al,%rax
+[ ]*[a-f0-9]+: 48 0f b6 00 * movzbq? \(%rax\),%rax
+[ ]*[a-f0-9]+: 0f b7 c0 * movzwl? %ax,%eax
+[ ]*[a-f0-9]+: 67 0f b7 00 * movzwl? \(%eax\),%eax
+[ ]*[a-f0-9]+: 48 0f b7 c0 * movzwq? %ax,%rax
+[ ]*[a-f0-9]+: 48 0f b7 00 * movzwq? \(%rax\),%rax
+[ ]*[a-f0-9]+: 0f b7 c0 * movzwl? %ax,%eax
+[ ]*[a-f0-9]+: 67 0f b7 00 * movzwl? \(%eax\),%eax
+[ ]*[a-f0-9]+: 48 0f b7 c0 * movzwq? %ax,%rax
+[ ]*[a-f0-9]+: 48 0f b7 00 * movzwq? \(%rax\),%rax
+#pass
--- 2016-06-30/opcodes/i386-opc.tbl 2016-06-30 11:25:51.000000000 +0200
+++ 2016-06-30/opcodes/i386-opc.tbl 2016-06-30 12:04:26.000000000 +0200
@@ -74,18 +74,9 @@ movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|
movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
-// Move with zero extend. We can't remove "movzb" since existing
-// assembly codes may use it.
-movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
-// "movzbl" & "movzbw" should not be unified into "movzb" for
-// consistency with the sign extending moves above.
-movzbl, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
-movzbw, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 }
-movzwl, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
-// These instructions are not particulary useful, since the zero extend
-// 32->64 is implicit, but we can encode them.
-movzbq, 2, 0xfb6, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
-movzwq, 2, 0xfb7, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
+// Move with zero extend.
+movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
+movzw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
// Intel Syntax next 2 insns (the 64-bit variants are not particulary
// useful since the zero extend 32->64 is implicit, but we can encode them).
movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
Attachment:
binutils-master-x86-movz.patch
Description: Text document
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