From 57376f89b5d7f70056da13fff905176b2bac4933 Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu <claziss@synopsys.com>
Date: Sat, 12 Mar 2016 11:10:54 +0100
Subject: [PATCH] [ARC] Add support for Quarkse opcodes.

Add new ARC EM opcodes.

gas/
2016-03-11  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/ext2op.d: New file.
	* testsuite/gas/arc/ext2op.s: Likewise.
	* testsuite/gas/arc/ext3op.d: Likewise.
	* testsuite/gas/arc/ext3op.s: Likewise.

opcodes/
2016-03-11  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-tbl.h (invld07): Remove.
	* arc-ext-tbl.h: New file.
	* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
	* arc-opc.c (FLAGS_NONE, FLAGS_F, FLAGS_CC, FLAGS_CCF, ARG_NONE)
	(ARG_32BIT_RARBRC, ARG_32BIT_ZARBRC, ARG_32BIT_RBRBRC)
	(ARG_32BIT_RARBU6, ARG_32BIT_ZARBU6, ARG_32BIT_RBRBU6)
	(ARG_32BIT_RBRBS12, ARG_32BIT_RALIMMRC, ARG_32BIT_RARBLIMM)
	(ARG_32BIT_ZALIMMRC, ARG_32BIT_ZARBLIMM, ARG_32BIT_RBRBLIMM)
	(ARG_32BIT_RALIMMU6, ARG_32BIT_ZALIMMU6, ARG_32BIT_ZALIMMS12)
	(ARG_32BIT_RALIMMLIMM, ARG_32BIT_ZALIMMLIMM, ARG_32BIT_RBRC)
	(ARG_32BIT_ZARC, ARG_32BIT_RBU6, ARG_32BIT_ZAU6, ARG_32BIT_RBLIMM)
	(ARG_32BIT_ZALIMM, EXTINSN2OP, EXTINSN3OP): Define.

include/
2016-03-11  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
	(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
	(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
	(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
	(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
	(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
	(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
	(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
	(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
	(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
	(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
	(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
	(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
	(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
---
 gas/testsuite/gas/arc/ext2op.d | 25 +++++++++++
 gas/testsuite/gas/arc/ext2op.s | 21 ++++++++++
 gas/testsuite/gas/arc/ext3op.d | 65 +++++++++++++++++++++++++++++
 gas/testsuite/gas/arc/ext3op.s | 64 ++++++++++++++++++++++++++++
 include/opcode/arc.h           | 72 ++++++++++++++++++++++++++++++++
 opcodes/arc-dis.c              |  3 --
 opcodes/arc-ext-tbl.h          | 28 +++++++++++++
 opcodes/arc-opc.c              | 95 ++++++++++++++++++++++++++++++++++++++++++
 opcodes/arc-tbl.h              |  3 --
 9 files changed, 370 insertions(+), 6 deletions(-)
 create mode 100644 gas/testsuite/gas/arc/ext2op.d
 create mode 100644 gas/testsuite/gas/arc/ext2op.s
 create mode 100644 gas/testsuite/gas/arc/ext3op.d
 create mode 100644 gas/testsuite/gas/arc/ext3op.s
 create mode 100644 opcodes/arc-ext-tbl.h

diff --git a/gas/testsuite/gas/arc/ext2op.d b/gas/testsuite/gas/arc/ext2op.d
new file mode 100644
index 0000000..144989e
--- /dev/null
+++ b/gas/testsuite/gas/arc/ext2op.d
@@ -0,0 +1,25 @@
+#as: -mcpu=arcem
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	382f 006d           	dsp_fp_sqrt	r0,r1
+   4:	3b2f 372d           	dsp_fp_sqrt	fp,sp
+   8:	386f 002d           	dsp_fp_sqrt	r0,0
+   c:	392f 0fad ffff ffff 	dsp_fp_sqrt	r1,0xffffffff
+  14:	3e2f 70ad           	dsp_fp_sqrt	0,r2
+  18:	3c2f 0fad 0000 00ff 	dsp_fp_sqrt	r4,0xff
+  20:	3e2f 0fad ffff ff00 	dsp_fp_sqrt	r6,0xffffff00
+  28:	382f 1fad 0000 0100 	dsp_fp_sqrt	r8,0x100
+  30:	392f 1fad ffff feff 	dsp_fp_sqrt	r9,0xfffffeff
+  38:	3b2f 1fad 4242 4242 	dsp_fp_sqrt	r11,0x42424242
+  40:	382f 0fad 0000 0000 	dsp_fp_sqrt	r0,0
+			44: R_ARC_32_ME	foo
+  48:	382f 806d           	dsp_fp_sqrt.f	r0,r1
+  4c:	3a6f 806d           	dsp_fp_sqrt.f	r2,0x1
+  50:	3e2f f12d           	dsp_fp_sqrt.f	0,r4
+  54:	3d2f 8fad 0000 0200 	dsp_fp_sqrt.f	r5,0x200
diff --git a/gas/testsuite/gas/arc/ext2op.s b/gas/testsuite/gas/arc/ext2op.s
new file mode 100644
index 0000000..f99009d
--- /dev/null
+++ b/gas/testsuite/gas/arc/ext2op.s
@@ -0,0 +1,21 @@
+# 2 operand insn test
+
+        dsp_fp_sqrt r0,r1
+        dsp_fp_sqrt fp,sp
+
+        dsp_fp_sqrt r0,0
+        dsp_fp_sqrt r1,-1
+        dsp_fp_sqrt 0,r2
+        dsp_fp_sqrt r4,255
+        dsp_fp_sqrt r6,-256
+
+        dsp_fp_sqrt r8,256
+        dsp_fp_sqrt r9,-257
+        dsp_fp_sqrt r11,0x42424242
+
+        dsp_fp_sqrt r0,foo
+
+        dsp_fp_sqrt.f r0,r1
+        dsp_fp_sqrt.f r2,1
+        dsp_fp_sqrt.f 0,r4
+        dsp_fp_sqrt.f r5,512
diff --git a/gas/testsuite/gas/arc/ext3op.d b/gas/testsuite/gas/arc/ext3op.d
new file mode 100644
index 0000000..926a13c
--- /dev/null
+++ b/gas/testsuite/gas/arc/ext3op.d
@@ -0,0 +1,65 @@
+#as: -mcpu=arcem
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	392a 0080           	dsp_fp_div	r0,r1,r2
+   4:	3b2a 371a           	dsp_fp_div	gp,fp,sp
+   8:	3d2a 37dd           	dsp_fp_div	ilink,ilink,blink
+   c:	396a 0000           	dsp_fp_div	r0,r1,0
+  10:	3e2a 7080 0000 0000 	dsp_fp_div	r0,0,r2
+  18:	392a 00be           	dsp_fp_div	0,r1,r2
+  1c:	392a 0f80 ffff ffff 	dsp_fp_div	r0,r1,0xffffffff
+  24:	3e2a 7080 ffff ffff 	dsp_fp_div	r0,0xffffffff,r2
+  2c:	392a 0f80 0000 00ff 	dsp_fp_div	r0,r1,0xff
+  34:	3e2a 7080 0000 00ff 	dsp_fp_div	r0,0xff,r2
+  3c:	392a 0f80 ffff ff00 	dsp_fp_div	r0,r1,0xffffff00
+  44:	3e2a 7080 ffff ff00 	dsp_fp_div	r0,0xffffff00,r2
+  4c:	39aa 0004           	dsp_fp_div	r1,r1,256
+  50:	396a 0fc0           	dsp_fp_div	r0,r1,0x3f
+  54:	3e2a 7080 ffff feff 	dsp_fp_div	r0,0xfffffeff,r2
+  5c:	3e2a 7f80 0000 0100 	dsp_fp_div	r0,0x100,0x100
+  64:	392a 0f80 0000 0000 	dsp_fp_div	r0,r1,0
+			68: R_ARC_32_ME	foo
+  6c:	38ea 0080           	dsp_fp_div	r0,r0,r2
+  70:	3bea 0140           	dsp_fp_div	r3,r3,r5
+  74:	3eea 0201           	dsp_fp_div.eq	r6,r6,r8
+  78:	39ea 12c1           	dsp_fp_div.eq	r9,r9,r11
+  7c:	3cea 1382           	dsp_fp_div.ne	r12,r12,r14
+  80:	3fea 1442           	dsp_fp_div.ne	r15,r15,r17
+  84:	3aea 2503           	dsp_fp_div.p	r18,r18,r20
+  88:	3dea 25c3           	dsp_fp_div.p	r21,r21,r23
+  8c:	38ea 3684           	dsp_fp_div.n	r24,r24,gp
+  90:	3bea 3744           	dsp_fp_div.n	fp,fp,ilink
+  94:	3eea 37c5           	dsp_fp_div.c	r30,r30,blink
+  98:	3bea 00c5           	dsp_fp_div.c	r3,r3,r3
+  9c:	3bea 0205           	dsp_fp_div.c	r3,r3,r8
+  a0:	3bea 0106           	dsp_fp_div.nc	r3,r3,r4
+  a4:	3cea 0106           	dsp_fp_div.nc	r4,r4,r4
+  a8:	3cea 01c6           	dsp_fp_div.nc	r4,r4,r7
+  ac:	3cea 0147           	dsp_fp_div.v	r4,r4,r5
+  b0:	3dea 0147           	dsp_fp_div.v	r5,r5,r5
+  b4:	3dea 0148           	dsp_fp_div.nv	r5,r5,r5
+  b8:	3dea 0148           	dsp_fp_div.nv	r5,r5,r5
+  bc:	3eea 0009           	dsp_fp_div.gt	r6,r6,r0
+  c0:	38ea 002a           	dsp_fp_div.ge	r0,r0,0
+  c4:	39ea 006b           	dsp_fp_div.lt	r1,r1,0x1
+  c8:	3bea 00ed           	dsp_fp_div.hi	r3,r3,0x3
+  cc:	3cea 012e           	dsp_fp_div.ls	r4,r4,0x4
+  d0:	3dea 016f           	dsp_fp_div.pnz	r5,r5,0x5
+  d4:	392a 8080           	dsp_fp_div.f	r0,r1,r2
+  d8:	396a 8040           	dsp_fp_div.f	r0,r1,0x1
+  dc:	3e2a f080 0000 0001 	dsp_fp_div.f	r0,0x1,r2
+  e4:	392a 80be           	dsp_fp_div.f	0,r1,r2
+  e8:	392a 8f80 0000 0200 	dsp_fp_div.f	r0,r1,0x200
+  f0:	3e2a f080 0000 0200 	dsp_fp_div.f	r0,0x200,r2
+  f8:	39ea 8081           	dsp_fp_div.eq.f	r1,r1,r2
+  fc:	38ea 8022           	dsp_fp_div.ne.f	r0,r0,0
+ 100:	3aea 808b           	dsp_fp_div.lt.f	r2,r2,r2
+ 104:	3eea f0a9 0000 0001 	dsp_fp_div.gt.f	0,0x1,0x2
+ 10c:	3eea ff8c 0000 0200 	dsp_fp_div.le.f	0,0x200,0x200
+ 114:	3eea f0aa 0000 0200 	dsp_fp_div.ge.f	0,0x200,0x2
diff --git a/gas/testsuite/gas/arc/ext3op.s b/gas/testsuite/gas/arc/ext3op.s
new file mode 100644
index 0000000..ccb3d4c
--- /dev/null
+++ b/gas/testsuite/gas/arc/ext3op.s
@@ -0,0 +1,64 @@
+# 3 operand insn test
+
+	dsp_fp_div r0,r1,r2
+	dsp_fp_div gp,fp,sp
+	dsp_fp_div ilink,ilink,blink
+
+	dsp_fp_div r0,r1,0
+	dsp_fp_div r0,0,r2
+	dsp_fp_div 0,r1,r2
+
+	dsp_fp_div r0,r1,-1
+	dsp_fp_div r0,-1,r2
+	dsp_fp_div r0,r1,255
+	dsp_fp_div r0,255,r2
+	dsp_fp_div r0,r1,-256
+	dsp_fp_div r0,-256,r2
+
+	dsp_fp_div r1,r1,256
+	dsp_fp_div r0,r1,0x3F
+	dsp_fp_div r0,-257,r2
+
+	dsp_fp_div r0,256,256
+
+	dsp_fp_div r0,r1,foo
+
+	dsp_fp_div.al r0,r0,r2
+	dsp_fp_div.ra r3,r3,r5
+	dsp_fp_div.eq r6,r6,r8
+	dsp_fp_div.z  r9,r9,r11
+	dsp_fp_div.ne r12,r12,r14
+	dsp_fp_div.nz r15,r15,r17
+	dsp_fp_div.pl r18,r18,r20
+	dsp_fp_div.p  r21,r21,r23
+	dsp_fp_div.mi r24,r24,r26
+	dsp_fp_div.n  r27,r27,r29
+	dsp_fp_div.cs r30,r30,r31
+	dsp_fp_div.c  r3,r3,r3
+	dsp_fp_div.lo r3,r3,r8
+	dsp_fp_div.cc r3,r3,r4
+	dsp_fp_div.nc r4,r4,r4
+	dsp_fp_div.hs r4,r4,r7
+	dsp_fp_div.vs r4,r4,r5
+	dsp_fp_div.v  r5,r5,r5
+	dsp_fp_div.vc r5,r5,r5
+	dsp_fp_div.nv r5,r5,r5
+	dsp_fp_div.gt r6,r6,r0
+	dsp_fp_div.ge r0,r0,0
+	dsp_fp_div.lt r1,r1,1
+	dsp_fp_div.hi r3,r3,3
+	dsp_fp_div.ls r4,r4,4
+	dsp_fp_div.pnz r5,r5,5
+	dsp_fp_div.f r0,r1,r2
+	dsp_fp_div.f r0,r1,1
+	dsp_fp_div.f r0,1,r2
+	dsp_fp_div.f 0,r1,r2
+	dsp_fp_div.f r0,r1,512
+	dsp_fp_div.f r0,512,r2
+
+	dsp_fp_div.eq.f r1,r1,r2
+	dsp_fp_div.ne.f r0,r0,0
+	dsp_fp_div.lt.f r2,r2,r2
+	dsp_fp_div.gt.f 0,1,2
+	dsp_fp_div.le.f 0,512,512
+	dsp_fp_div.ge.f 0,512,2
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 6f5bc98..ba24f1a 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -63,6 +63,7 @@ typedef enum
     MPY7E,
     MPY8E,
     MPY9E,
+    QUARKSE,
     SHFT1,
     SHFT2,
     SWAP,
@@ -418,4 +419,75 @@ extern const unsigned arc_num_aux_regs;
 extern const struct arc_opcode arc_relax_opcodes[];
 extern const unsigned arc_num_relax_opcodes;
 
+/* Macros to help generating regular pattern instructions.  */
+#define FIELDA(word) (word & 0x3F)
+#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
+#define FIELDC(word) ((word & 0x3F) << 6)
+#define FIELDF	     (0x01 << 15)
+#define FIELDQ	     (0x1F)
+
+#define INSN3OP(MOP,SOP)	(((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
+#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
+#define INSN2OP(MOP,SOP)	(INSN2OPX (MOP,0x2F,SOP))
+
+#define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
+#define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
+#define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
+#define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
+#define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
+#define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
+#define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
+#define INSN3OP_0LL(MOP,SOP)					\
+  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
+#define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
+#define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
+#define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
+#define INSN3OP_0LU(MOP,SOP)					\
+  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
+#define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
+#define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
+#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
+#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
+#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
+#define INSN3OP_C0LL(MOP,SOP)					\
+  (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
+#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
+#define INSN3OP_C0LU(MOP,SOP)					\
+  (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
+
+#define MINSN3OP_ABC  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
+#define MINSN3OP_ALC  (~(FIELDF | FIELDA (63) | FIELDC (63)))
+#define MINSN3OP_ABL  (~(FIELDF | FIELDA (63) | FIELDB (63)))
+#define MINSN3OP_ALL  (~(FIELDF | FIELDA (63)))
+#define MINSN3OP_0BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
+#define MINSN3OP_0LC  (~(FIELDF | FIELDC (63)))
+#define MINSN3OP_0BL  (~(FIELDF | FIELDB (63)))
+#define MINSN3OP_0LL  (~(FIELDF))
+#define MINSN3OP_ABU  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
+#define MINSN3OP_ALU  (~(FIELDF | FIELDA (63) | FIELDC (63)))
+#define MINSN3OP_0BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
+#define MINSN3OP_0LU  (~(FIELDF | FIELDC (63)))
+#define MINSN3OP_BBS  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
+#define MINSN3OP_0LS  (~(FIELDF | FIELDA (63) | FIELDC (63)))
+#define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
+#define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
+#define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
+#define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
+#define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
+#define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
+
+#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
+#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
+#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
+#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
+#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
+#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
+
+#define MINSN2OP_BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
+#define MINSN2OP_BL  (~(FIELDF | FIELDB (63)))
+#define MINSN2OP_0C  (~(FIELDF | FIELDC (63)))
+#define MINSN2OP_0L  (~(FIELDF))
+#define MINSN2OP_BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
+#define MINSN2OP_0U  (~(FIELDF | FIELDC (63)))
+
 #endif /* OPCODE_ARC_H */
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 7320c9f..b33e9bc 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -59,9 +59,6 @@ static const char * const regnames[64] =
 #define BITS(word,s,e)  (((word) << (sizeof (word) * 8 - 1 - e)) >>	\
 			 (s + (sizeof (word) * 8 - 1 - e)))
 #define OPCODE(word)	(BITS ((word), 27, 31))
-#define FIELDA(word)	(BITS ((word), 21, 26))
-#define FIELDB(word)	(BITS ((word), 15, 20))
-#define FIELDC(word)	(BITS ((word),  9, 14))
 
 #define OPCODE_AC(word)   (BITS ((word), 11, 15))
 
diff --git a/opcodes/arc-ext-tbl.h b/opcodes/arc-ext-tbl.h
new file mode 100644
index 0000000..f07391e
--- /dev/null
+++ b/opcodes/arc-ext-tbl.h
@@ -0,0 +1,28 @@
+/* ARC instruction defintions.
+   Copyright (C) 2016 Free Software Foundation, Inc.
+
+   Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+   This file is part of libopcodes.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+EXTINSN2OP ("dsp_fp_flt2i",  ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 43)
+EXTINSN2OP ("dsp_fp_isflt",  ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 44)
+EXTINSN2OP ("dsp_fp_sqrt",   ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 45)
+
+EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 42)
+EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 43)
+
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 9a674d5..cb9dbdf 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -867,6 +867,12 @@ const struct arc_flag_class arc_flag_classes[] =
   { CND, { F_NE, F_NULL}},
 };
 
+/* Common combinations of FLAGS.  */
+#define FLAGS_NONE { 0 }
+#define FLAGS_F    { C_F }
+#define FLAGS_CC   { C_CC }
+#define FLAGS_CCF  { C_CC, C_F }
+
 /* The operands table.
 
    The format of the operands table is:
@@ -1190,6 +1196,93 @@ const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
 const unsigned arc_Toperand = FKT_T;
 const unsigned arc_NToperand = FKT_NT;
 
+/* Common combination of arguments.  */
+#define ARG_NONE		{ 0 }
+#define ARG_32BIT_RARBRC	{ RA, RB, RC }
+#define ARG_32BIT_ZARBRC	{ ZA, RB, RC }
+#define ARG_32BIT_RBRBRC	{ RB, RBdup, RC }
+#define ARG_32BIT_RARBU6	{ RA, RB, UIMM6_20 }
+#define ARG_32BIT_ZARBU6	{ ZA, RB, UIMM6_20 }
+#define ARG_32BIT_RBRBU6	{ RB, RBdup, UIMM6_20 }
+#define ARG_32BIT_RBRBS12	{ RB, RBdup, SIMM12_20 }
+#define ARG_32BIT_RALIMMRC	{ RA, LIMM, RC }
+#define ARG_32BIT_RARBLIMM	{ RA, RB, LIMM }
+#define ARG_32BIT_ZALIMMRC	{ ZA, LIMM, RC }
+#define ARG_32BIT_ZARBLIMM	{ ZA, RB, LIMM }
+
+#define ARG_32BIT_RBRBLIMM	{ RB, RBdup, LIMM }
+#define ARG_32BIT_RALIMMU6	{ RA, LIMM, UIMM6_20 }
+#define ARG_32BIT_ZALIMMU6	{ ZA, LIMM, UIMM6_20 }
+
+#define ARG_32BIT_ZALIMMS12	{ ZA, LIMM, SIMM12_20 }
+#define ARG_32BIT_RALIMMLIMM	{ RA, LIMM, LIMMdup }
+#define ARG_32BIT_ZALIMMLIMM	{ ZA, LIMM, LIMMdup }
+
+#define ARG_32BIT_RBRC   { RB, RC }
+#define ARG_32BIT_ZARC   { ZA, RC }
+#define ARG_32BIT_RBU6   { RB, UIMM6_20 }
+#define ARG_32BIT_ZAU6   { ZA, UIMM6_20 }
+#define ARG_32BIT_RBLIMM { RB, LIMM }
+#define ARG_32BIT_ZALIMM { ZA, LIMM }
+
+/* Macro to generate 2 operand extension instruction.  */
+#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP)		 \
+  { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
+      ARG_32BIT_RBRC,   FLAGS_F },				 \
+  { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
+      ARG_32BIT_ZARC,   FLAGS_F },				 \
+  { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
+      ARG_32BIT_RBU6,   FLAGS_F },				 \
+  { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
+      ARG_32BIT_ZAU6,   FLAGS_F },				 \
+  { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
+      ARG_32BIT_RBLIMM, FLAGS_F },				 \
+  { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
+      ARG_32BIT_ZALIMM, FLAGS_F },
+
+/* Macro to generate 3 operand extesion instruction.  */
+#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP)			\
+  { NAME, INSN3OP_ABC (MOP,SOP),  MINSN3OP_ABC,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_RARBRC,     FLAGS_F },					\
+  { NAME, INSN3OP_0BC (MOP,SOP),  MINSN3OP_0BC,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_ZARBRC,     FLAGS_F   },				\
+  { NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS,	\
+      ARG_32BIT_RBRBRC,     FLAGS_CCF },				\
+  { NAME, INSN3OP_ABU (MOP,SOP),  MINSN3OP_ABU,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_RARBU6,     FLAGS_F   },				\
+  { NAME, INSN3OP_0BU (MOP,SOP),  MINSN3OP_0BU,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_ZARBU6,     FLAGS_F   },				\
+  { NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS,	\
+      ARG_32BIT_RBRBU6,     FLAGS_CCF },				\
+  { NAME, INSN3OP_BBS (MOP,SOP),  MINSN3OP_BBS,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_RBRBS12,    FLAGS_F   },				\
+  { NAME, INSN3OP_ALC (MOP,SOP),  MINSN3OP_ALC,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_RALIMMRC,   FLAGS_F   },				\
+  { NAME, INSN3OP_ABL (MOP,SOP),  MINSN3OP_ABL,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_RARBLIMM,   FLAGS_F   },				\
+  { NAME, INSN3OP_0LC (MOP,SOP),  MINSN3OP_0LC,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_ZALIMMRC,   FLAGS_F   },				\
+  { NAME, INSN3OP_0BL (MOP,SOP),  MINSN3OP_0BL,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_ZARBLIMM,   FLAGS_F   },				\
+  { NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS,	\
+      ARG_32BIT_ZALIMMRC,   FLAGS_CCF },				\
+  { NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS,	\
+      ARG_32BIT_RBRBLIMM,   FLAGS_CCF },				\
+  { NAME, INSN3OP_ALU (MOP,SOP),  MINSN3OP_ALU,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_RALIMMU6,   FLAGS_F   },				\
+  { NAME, INSN3OP_0LU (MOP,SOP),  MINSN3OP_0LU,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_ZALIMMU6,   FLAGS_F   },				\
+  { NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS,	\
+      ARG_32BIT_ZALIMMU6,   FLAGS_CCF },				\
+  { NAME, INSN3OP_0LS (MOP,SOP),  MINSN3OP_0LS,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_ZALIMMS12,  FLAGS_F   },				\
+  { NAME, INSN3OP_ALL (MOP,SOP),  MINSN3OP_ALL,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_RALIMMLIMM, FLAGS_F   },				\
+  { NAME, INSN3OP_0LL (MOP,SOP),  MINSN3OP_0LL,  CPU, CLASS, SCLASS,	\
+      ARG_32BIT_ZALIMMLIMM, FLAGS_F   },				\
+  { NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS,	\
+      ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
+
 /* The opcode table.
 
    The format of the opcode table is:
@@ -1198,6 +1291,8 @@ const unsigned arc_NToperand = FKT_NT;
 const struct arc_opcode arc_opcodes[] =
 {
 #include "arc-tbl.h"
+
+#include "arc-ext-tbl.h"
 };
 
 const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 5adc310..ab27990 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -7856,9 +7856,6 @@
 /* invld052f3f00  00101RRRRR101111RRRRRRRRRR111111.  */
 { "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
 
-/* invld07  00111RRRRRRRRRRRRRRRRRRRRRRRRRRR.  */
-{ "invld07", 0x38000000, 0xF8000000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
-
 /* j c 00100RRR001000000RRRCCCCCCRRRRRR.  */
 { "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
 
-- 
1.9.1

