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RE: GNURX toolchain generates incorrect opcode for "mov.b #0xff, [r0]" instruction.
- From: "Vinay Kumar. G" <Vinay dot G at kpit dot com>
- To: Nick Clifton <nickc at redhat dot com>
- Cc: "binutils at sourceware dot org" <binutils at sourceware dot org>, DJ Delorie <dj at redhat dot com>
- Date: Thu, 11 Feb 2016 12:42:10 +0000
- Subject: RE: GNURX toolchain generates incorrect opcode for "mov.b #0xff, [r0]" instruction.
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- References: <SIXPR0301MB1020E733A8B7D90F3EE3DEBF93DF0 at SIXPR0301MB1020 dot apcprd03 dot prod dot outlook dot com> <56B2145F dot 3000604 at redhat dot com> <SIXPR0301MB1020DEFF3167E639C1CAC18593D70 at SIXPR0301MB1020 dot apcprd03 dot prod dot outlook dot com> <56BB0439 dot 1040508 at redhat dot com>
Hi Nick,
>> please could you add this testcase to the patch
Yes, I have added pr19665.s and pr19665.d testcase to the regression testsuite as per your suggestion.
Please find below the updated patch.
>> Really ? Because when I regression tested it I saw a new gas testsuite failure:
I have cross verified the regression failures observed at your end using the patched assembler, the generated object dump and the list files seem to be expected as shown below. Only thing is, the offset value '0' is not visible in the generated object dump.
$cat test.s
mov.b #0, 0[r0]
mov.b #255, 0[r0]
mov.w #127, 0[r0]
mov.w #0, 0[r0]
mov.l #127, 0[r0]
rx-elf-as test.s -o test.o -aln=test.lst
rx-elf-objdump -d test.o > test.o.dis
$cat test.lst
1 0000 3C 00 00 mov.b #0, 0[r0]
2 0003 3C 00 FF mov.b #255, 0[r0]
3 0006 3D 00 7F mov.w #127, 0[r0]
4 0009 3D 00 00 mov.w #0, 0[r0]
5 000c 3E 00 7F mov.l #127, 0[r0]
$cat test.o.dis
test.o: file format elf32-rx-le
Disassembly of section P:
00000000 <P>:
0: 3c 00 00 mov.b #0, [r0]
3: 3c 00 ff mov.b #255, [r0]
6: 3d 00 7f mov.w #127, [r0]
9: 3d 00 00 mov.w #0, [r0]
c: 3e 00 7f mov.l #127, [r0]
Regards,
Vinay
/*******************************************************************/
gas/ChangeLog
2016-02-10 Vinay <Vinay.G@kpit.com>
* config/rx-parse.y (MOV): Opcode generation for index
register addressing mode.
gas/testsuite/ChangeLog
* gas/rx/rx.exp: Updated for new testcase.
* gas/rx/pr19665.s: New file.
* gas/rx/pr19665.s: New file.
Index: gas/config/rx-parse.y
===================================================================
--- gas/config/rx-parse.y (revision 3183)
+++ gas/config/rx-parse.y (working copy)
@@ -271,7 +271,15 @@
} }
/* ---------------------------------------------------------------------- */
+ | MOV DOT_B '#' EXPR ',' '[' REG ']'
+ { B2 (0xf8, 0x04); F ($7, 8, 4); IMMB ($4, 12);}
+ | MOV DOT_W '#' EXPR ',' '[' REG ']'
+ { B2 (0xf8, 0x01); F ($7, 8, 4); IMMW ($4, 12);}
+
+ | MOV DOT_L '#' EXPR ',' '[' REG ']'
+ { B2 (0xf8, 0x02); F ($7, 8, 4); IMM ($4, 12);}
+
| MOV DOT_B '#' EXPR ',' disp '[' REG ']'
/* rx_disp5op changes the value if it succeeds, so keep it last. */
{ if ($8 <= 7 && rx_uintop ($4, 8) && rx_disp5op0 (&$6, BSIZE))
Index: gas/testsuite/gas/rx/rx.exp
===================================================================
--- gas/testsuite/gas/rx/rx.exp (revision 3183)
+++ gas/testsuite/gas/rx/rx.exp (working copy)
@@ -32,3 +32,4 @@
run_dump_test "rx-asm-good"
# run_list_test "rx-asm-bad" "" "Generation of error messages with bogus Renesas assembler directives"
+run_dump_test "pr19665"
--- /dev/null 2016-02-09 12:36:16.414255083 +0530
+++ gas/testsuite/gas/rx/pr19665.s 2016-02-11 13:32:13.077988960 +0530
@@ -0,0 +1,20 @@
+mov.b #0xff, [r0]
+mov.b #0xff, [r1]
+mov.b #0xff, [r2]
+mov.b #0xff, [r13]
+mov.b #0xff, [r14]
+mov.b #0xff, [r15]
+#
+mov.w #0xff, [r0]
+mov.w #0xff, [r1]
+mov.w #0xff, [r2]
+mov.w #0xff, [r13]
+mov.w #0xff, [r14]
+mov.w #0xff, [r15]
+#
+mov.l #0xff, [r0]
+mov.l #0xff, [r1]
+mov.l #0xff, [r2]
+mov.l #0xff, [r13]
+mov.l #0xff, [r14]
+mov.l #0xff, [r15]
--- /dev/null 2016-02-09 12:36:16.414255083 +0530
+++ gas/testsuite/gas/rx/pr19665.d 2016-02-11 16:44:40.686535497 +0530
@@ -0,0 +1,26 @@
+#objdump: -dr
+
+dump.o: file format elf32-rx-le
+
+
+Disassembly of section P:
+
+00000000 <P>:
+ 0: f8 04 ff mov\.b #255, \[r0\]
+ 3: f8 14 ff mov\.b #255, \[r1\]
+ 6: f8 24 ff mov\.b #255, \[r2\]
+ 9: f8 d4 ff mov\.b #255, \[r13\]
+ c: f8 e4 ff mov\.b #255, \[r14\]
+ f: f8 f4 ff mov\.b #255, \[r15\]
+ 12: f8 09 ff 00 mov\.w #255, \[r0\]
+ 16: f8 19 ff 00 mov\.w #255, \[r1\]
+ 1a: f8 29 ff 00 mov\.w #255, \[r2\]
+ 1e: f8 d9 ff 00 mov\.w #255, \[r13\]
+ 22: f8 e9 ff 00 mov\.w #255, \[r14\]
+ 26: f8 f9 ff 00 mov\.w #255, \[r15\]
+ 2a: f8 0a ff 00 mov\.l #255, \[r0\]
+ 2e: f8 1a ff 00 mov\.l #255, \[r1\]
+ 32: f8 2a ff 00 mov\.l #255, \[r2\]
+ 36: f8 da ff 00 mov\.l #255, \[r13\]
+ 3a: f8 ea ff 00 mov\.l #255, \[r14\]
+ 3e: f8 fa ff 00 mov\.l #255, \[r15\]