[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.

[Matthew Wahab <matthew dot wahab at foss dot arm dot com>]

Hello,

ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch set adds the 16-bit
Adv.SIMD vector and scalar instructions to binutils, making them
available when both +simd and +fp16 architecture extensions are enabled.
The series also adds support for a new vector type, 2H, used by the FP16
scalar pairwise instructions.

The patches in this series:
- Add a FP16 Adv.SIMD feature macro for use by the encoding/decoding
  routines.
- Add FP16 instructions in the group Vector Three Register Same.
- Add FP16 instructions in the group Scalar Three Register Same.
- Add FP16 instructions in the group Vector Two Register Misc.
- Add FP16 instructions in the group Scalar Two Register Misc.
- Add FP16 instructions in the group Vector Indexed Element.
- Add FP16 instructions in the group Scalar Indexed Element.
- Add FP16 instructions in the group Adv.SIMD Across Lanes.
- Add FP16 instructions in the group Adv.SIMD Modified Immediate.
- Rework some code for handling vector types to weaken its assumptions
  about available vector-types.
- Add support for the 2H vector type.
- Add FP16 instructions in the group Adv.SIMD Scalar Pairwise.
- Add FP16 instructions in the group Adv.SIMD Shift By Immediate.
- Add a FP16 instructions in the group Adv.SIMD Scalar Shift By
  Immediate.

This patch adds the feature macro SIMD_F16 to the AArch64
encoding/decoding routines. It is used to decide when the new
instructions are available to the assembler and is true when both +simd
and +fp16 are selected.

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_simd_f16): New.
	(SIMD_F16): New.

>From acf74dd959f16861fa8012121d3aa430e3a62706 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Tue, 8 Sep 2015 16:10:57 +0100
Subject: [PATCH 01/14] [AArch64] Add FP16 SIMD feature flag.

---
 opcodes/aarch64-tbl.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 50bbc2d..bd6b265 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1301,6 +1301,8 @@ static const aarch64_feature_set aarch64_feature_v8_2 =
   AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
 static const aarch64_feature_set aarch64_feature_fp_f16 =
   AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
+static const aarch64_feature_set aarch64_feature_simd_f16 =
+  AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0);
 
 #define CORE	&aarch64_feature_v8
 #define FP	&aarch64_feature_fp
@@ -1311,6 +1313,7 @@ static const aarch64_feature_set aarch64_feature_fp_f16 =
 #define LOR	&aarch64_feature_lor
 #define RDMA	&aarch64_feature_rdma
 #define FP_F16	&aarch64_feature_fp_f16
+#define SIMD_F16	&aarch64_feature_simd_f16
 #define ARMV8_2	&aarch64_feature_v8_2
 
 struct aarch64_opcode aarch64_opcode_table[] =
-- 
2.1.4