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[AArch64][PATCH 1/2] Add support for RAS instruction ESB.
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Tue, 8 Dec 2015 17:18:41 +0000
- Subject: [AArch64][PATCH 1/2] Add support for RAS instruction ESB.
- Authentication-results: sourceware.org; auth=none
Hello,
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.
This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.
Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
Ok for trunk?
Matthew
gas/testsuite/
2015-12-08 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: New.
* gas/aarch64/system-2.s: New.
* gas/aarch64/system.d: Adjust expected output for HINT 16.
include/opcode/
2015-12-08 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_RAS): New.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
opcodes/
2015-12-08 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (aarch64_feature_ras): New.
(RAS): New.
(aarch64_opcode_table): Add "esb".
>From 79d829317c70405e448a0094f32636ad094f2b61 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Wed, 16 Sep 2015 11:43:06 +0100
Subject: [PATCH 1/2] [Aarch64][PATCH 1/2] Add support for RAS instruction ESB.
Change-Id: I8e357bdf432ccf01e73d4c582bd70e45133d10b6
---
gas/testsuite/gas/aarch64/system-2.d | 10 ++++++++++
gas/testsuite/gas/aarch64/system-2.s | 6 ++++++
gas/testsuite/gas/aarch64/system.d | 2 +-
include/opcode/aarch64.h | 2 ++
opcodes/aarch64-asm-2.c | 13 +++++++------
opcodes/aarch64-dis-2.c | 37 ++++++++++++++++++------------------
opcodes/aarch64-tbl.h | 4 ++++
7 files changed, 49 insertions(+), 25 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/system-2.d
create mode 100644 gas/testsuite/gas/aarch64/system-2.s
diff --git a/gas/testsuite/gas/aarch64/system-2.d b/gas/testsuite/gas/aarch64/system-2.d
new file mode 100644
index 0000000..9b379cf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/system-2.d
@@ -0,0 +1,10 @@
+#as: -march=armv8.2-a
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+ 0: d503221f esb
+ 4: d503221f esb
diff --git a/gas/testsuite/gas/aarch64/system-2.s b/gas/testsuite/gas/aarch64/system-2.s
new file mode 100644
index 0000000..9b7f216
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/system-2.s
@@ -0,0 +1,6 @@
+ /* ARMv8.1 System instructions. */
+ .text
+
+ /* RAS Extension. */
+ esb
+ hint #0x10
diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d
index 4fad895..d4dcf86 100644
--- a/gas/testsuite/gas/aarch64/system.d
+++ b/gas/testsuite/gas/aarch64/system.d
@@ -28,7 +28,7 @@ Disassembly of section \.text:
50: d50321bf hint #0xd
54: d50321df hint #0xe
58: d50321ff hint #0xf
- 5c: d503221f hint #0x10
+ 5c: d503221f (hint #0x10|esb)
60: d503223f hint #0x11
64: d503225f hint #0x12
68: d503227f hint #0x13
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6654be3..51e9faa 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -49,6 +49,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
+#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -66,6 +67,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_FEATURE_V8_2 \
| AARCH64_FEATURE_F16 \
+ | AARCH64_FEATURE_RAS \
| AARCH64_FEATURE_FP \
| AARCH64_FEATURE_SIMD \
| AARCH64_FEATURE_CRC \
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 50bbc2d..91d8dcf 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1297,6 +1297,8 @@ static const aarch64_feature_set aarch64_feature_lor =
AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
static const aarch64_feature_set aarch64_feature_rdma =
AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
+static const aarch64_feature_set aarch64_feature_ras =
+ AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0);
static const aarch64_feature_set aarch64_feature_v8_2 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
static const aarch64_feature_set aarch64_feature_fp_f16 =
@@ -1311,6 +1313,7 @@ static const aarch64_feature_set aarch64_feature_fp_f16 =
#define LOR &aarch64_feature_lor
#define RDMA &aarch64_feature_rdma
#define FP_F16 &aarch64_feature_fp_f16
+#define RAS &aarch64_feature_ras
#define ARMV8_2 &aarch64_feature_v8_2
struct aarch64_opcode aarch64_opcode_table[] =
@@ -2456,6 +2459,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"wfi", 0xd503207f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
{"sev", 0xd503209f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
{"sevl", 0xd50320bf, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
+ {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS},
{"clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, CORE, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
{"dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
{"dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
--
2.1.4