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[0/4, committed] Nios II R2 support

As noted here

Altera has developed a revised version of the Nios II architecture,
which they are calling "Nios II R2"; the original ISA is referred to
as "Nios II R1".  While they haven't yet made the documentation
for the new architecture available to the public, we've agreed to start contributing the toolchain support into the mainline repositories now in order to minimize divergence.

Here is a little background on the differences between R1 and R2, as
it pertains to the binutils support:

* The R2 instruction set is designed to be mostly compatible with the
  R1 instruction set at the assembly level, but the binary encodings
  are radically different.  Fields are in different places in the
  instruction word and the numbering of some opcodes has changed.  So,
  R1 and R2 objects are not binary-compatible and cannot be mixed in
  the same program.  This restriction is implemented by new flags in
  the ELF headers which are in turn set by a new -march assembler
  option.  The default remains to produce R1 code.

* The only cases where R1 code is not assembly-language compatible
  with R2 involve reducing constant fields for some instructions
  from 16 bits to 12.  This affects the load/store IO, data cache
  management, and RDPRS instructions.

* R2 adds many new instructions, some of which are optional in the
  processor implementation.  The biggest of the optional instruction
  groups is called "CDX", for Code Density eXtension, and includes
  16-bit instructions.  The 32- and 16-bit instructions can be mixed
  freely with minimum alignment for both on a 2-byte boundary instead
  of 4-byte as in R1.

* CDX also includes new push/pop and load/store multiple instructions.
  These are of more interest on the compiler end of things since they
  allow for more compact function prologues and epilogues; from a
  binutils implementation perspective, these are most notable for
  being quite tricky to parse and validate.  :-)

* There are a lot of new instruction formats introduced, both for
  16-bit and 32-bit instructions.  Many of the new 16-bit instructions
  have register operands encoded in a 3-bit field and/or take immediate
  operands that are encoded as enumerations, requiring lookup through a
  mapping table during assembly/disassembly.

* The R2 re-encodings of the R1 instruction set use the same
  relocation numbers as R1, but interpreted against the new bit
  locations of the corresponding fields in the instruction word.
  There are new relocations for the non-enumeration immediate fields
  in the new instruction formats, including the instructions with a
  reduced constant size.  Altera will publish the details of the new
  relocations when the processor ABI documentation is revised.

* The register set and ABI for register and stack usage are the same
  for both R1 and R2.

In addition to the binutils pieces being committed now, GCC and GDB
support will follow as soon as I have time to prepare and re-test the
patches.  At present, the R2 implementation in all components is
bare-metal only (no Linux kernel or glibc support yet).

There are 4 parts to the patch series:

(1) Add Nios II arch flags and compatibility tests
(2) Relocations for Nios II R2
(3) Opcodes and assembler support for Nios II R2
(4) Assembler tests for Nios II R2


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