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RE: [PATCH] add znver1 processor.
- From: "Gopalasubramanian, Ganesh" <Ganesh dot Gopalasubramanian at amd dot com>
- To: Jan Beulich <JBeulich at suse dot com>
- Cc: "H.J. Lu (hjl dot tools at gmail dot com)" <hjl dot tools at gmail dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Thu, 19 Mar 2015 10:56:25 +0000
- Subject: RE: [PATCH] add znver1 processor.
- Authentication-results: sourceware.org; auth=none
- Authentication-results: spf=none (sender IP is 165.204.84.222) smtp dot mailfrom=Ganesh dot Gopalasubramanian at amd dot com; gmail.com; dkim=none (message not signed) header.d=none;
- References: <EB4625145972F94C9680D8CADD65161578F54FA4 at SATLEXDAG02 dot amd dot com> <550AAD32020000780006B7BE at mail dot emea dot novell dot com>
> Is there _any_ public documentation available for this new processor model?
As of now, no!
We are pulling in efforts to make this publicly available soon.
-Ganesh
-----Original Message-----
From: Jan Beulich [mailto:JBeulich@suse.com]
Sent: Thursday, March 19, 2015 3:34 PM
To: Gopalasubramanian, Ganesh
Cc: H.J. Lu (hjl.tools@gmail.com); binutils@sourceware.org
Subject: Re: [PATCH] add znver1 processor.
>>> On 10.03.15 at 08:49, <Ganesh.Gopalasubramanian@amd.com> wrote:
> Attached patch adds the following.
> * New AMD znver1 processor. The architecture has the below features
> * TBM, FMA4, XOP, LWP: ISAs are not supported.
> * SMAP, RDSEED, SHA, XSAVEC, XSAVES, CLFLUSHOPT, ADCX: ISAs are supported.
> * New CLZERO instruction support.
> * clzero has opcode "0F 01 FC".
> * clzero gets enabled with CPUID, 8000_0008, EBX[0] =1.
> * clzero instruction zero's out the 64 byte cache line specified in rax.
> Bits 5:0 of rAX are ignored