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Re: [PATCH, MIPS] Relax alignment check for LDPC

Matthew Fortune <> writes:
> Richard Sandiford <> writes:
>> only safe if the target has 8-byte alignment at assembly time.  I.e. the
>> section that the target is in should have at least 8 bytes alignment and
>> the symbol itself should have an offset that's divisible by 8.
>> So I think we should either check S_GET_VALUE (fx_addsy) + fx_offset is
>> aligned or (probably better, if it works) check that the low 3 bits of
>> *valP are the same as the low three bits of:
>>     fixP->fx_where + fixP->fx_frag->fr_address
> OK. I almost did something like this but essentially wasn't confident enough.
> I'm not sure I follow on the low three bits matching part?

It should have been the low 3 bits of -*valP.  I just thought that any
"misalignment" from 8 bytes could only come directly from the address
of the LDPC itself.  I'm happy with not doing that though.

> So the extra questions are is it OK that:
> LD <Reg>,<off>($pc) requires 'off' to be a multiple of 8 and the calculation 
> here is ($pc&~7 + off).
2> LDPC <reg>, <4-byte-aligned-label>+<4-byte-multiple-offset> is
> meaningless and will break for REL.
> Personally I think the former is not overly harmful but I suspect some would
> prefer the latter to raise an error rather than silently lose bits.

Yeah.  I take the point about n32 and n64 being RELA, but we also have
o64 and 64-bit EABI, both of which are REL.  How about requiring the
symbol and offset to be individually aligned?


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