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[PATCH V2 1/9] binutils,gas,opcodes.elf: remove never used SPARC features.
- From: "Jose E. Marchesi" <jose dot marchesi at oracle dot com>
- To: binutils at sourceware dot org
- Cc: davem at davemloft dot net
- Date: Tue, 7 Oct 2014 16:48:25 +0200
- Subject: [PATCH V2 1/9] binutils,gas,opcodes.elf: remove never used SPARC features.
- Authentication-results: sourceware.org; auth=none
- References: <1412693313-3546-1-git-send-email-jose dot marchesi at oracle dot com>
This patch removes support from GNU binutils for the following SPARC
features, which were never released to the public or implemented:
- The transactional memory instructions of the cancelled Rock
processor (UltraSPARC-AT10): CHKPT and COMMIT.
- The %cps ancillary state register, also introduced in the
UltraSPARC-AT10, along with the associated rd/wr instructions.
- The RANDOM instruction.
Tested on sparc64-unknown-linux-gnu.
opcodes/ChangeLog:
2014-10-07 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
`commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
gas/ChangeLog:
2014-10-07 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (v9a_asr_table): Entry for %cps removed.
(sparc_arch_table): Remove the HWCAP_RANDOM, HWCAP_TRANS and
HWCAP_ASI_CACHE_SPARING from the architectures using them.
gas/testsuite/ChangeLog:
2014-10-07 Jose E. Marchesi <jose.marchesi@oracle.com>
* gas/sparc/hpcvis3.d: Remove tests for the `chkpt', `commit',
`random', `wr r,i,%cps' and `rd r,%cps' instructions.
* gas/sparc/hpcvis3.s: Likewise.
---
gas/ChangeLog | 6 ++++++
gas/config/tc-sparc.c | 9 ++++-----
gas/doc/c-sparc.texi | 12 +++++-------
gas/testsuite/ChangeLog | 6 ++++++
gas/testsuite/gas/sparc/hpcvis3.d | 10 +++++-----
gas/testsuite/gas/sparc/hpcvis3.s | 10 +++++-----
opcodes/ChangeLog | 5 +++++
opcodes/sparc-opc.c | 7 -------
8 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index 7497618..609797e 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -242,8 +242,8 @@ static struct sparc_arch {
{ "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
{ "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
{ "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
- { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
- { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
+ { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU },
+ { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
{ "leon", "leon", leon, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
{ "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
{ "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
@@ -254,14 +254,14 @@ static struct sparc_arch {
{ "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
{ "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
{ "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
- { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
+ { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
{ "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
{ "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
{ "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
{ "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
{ "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
{ "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
- { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
+ { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
/* This exists to allow configure.tgt to pass one
value to specify both the default machine and default word size. */
{ "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
@@ -812,7 +812,6 @@ struct priv_reg_entry v9a_asr_table[] =
{"pcr", 16},
{"gsr", 19},
{"dcr", 18},
- {"cps", 28},
{"cfr", 26},
{"clear_softint", 21},
{"", -1}, /* End marker. */
diff --git a/gas/doc/c-sparc.texi b/gas/doc/c-sparc.texi
index 8915528..6b0710e 100644
--- a/gas/doc/c-sparc.texi
+++ b/gas/doc/c-sparc.texi
@@ -98,10 +98,9 @@ as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
multiply-add, VIS 3.0, and HPC extension instructions, as well as the
instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
-@samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional
-memory, floating point unfused multiply-add, integer multiply-add, and
-cache sparing store instructions, as well as the instructions enabled
-by @samp{-Av8plusd} and @samp{-Av9d}.
+@samp{-Av8plusv} and @samp{-Av9v} enable floating point unfused
+multiply-add, and integer multiply-add, as well as the instructions
+enabled by @samp{-Av8plusd} and @samp{-Av9d}.
@samp{-Asparc} specifies a v9 environment. It is equivalent to
@samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
@@ -121,9 +120,8 @@ multiply-add instructions enabled.
@samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
HPC , and floating point fused multiply-add instructions enabled.
-@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0,
-HPC, transactional memory, random, and floating point unfused multiply-add
-instructions enabled.
+@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0, HPC,
+and floating point unfused multiply-add instructions enabled.
@item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
diff --git a/gas/testsuite/gas/sparc/hpcvis3.d b/gas/testsuite/gas/sparc/hpcvis3.d
index 8b920a5..2c09504 100644
--- a/gas/testsuite/gas/sparc/hpcvis3.d
+++ b/gas/testsuite/gas/sparc/hpcvis3.d
@@ -7,11 +7,11 @@
Disassembly of section .text:
0+ <.text>:
- 0: 83 47 00 00 rd %cps, %g1
- 4: b9 80 a0 03 wr %g2, 3, %cps
+ 0: 01 00 00 00 nop
+ 4: 01 00 00 00 nop
8: c7 08 c0 00 ldx \[ %g3 \], %efsr
- c: 30 50 00 01 chkpt 0x10
- 10: bd f0 00 00 commit
+ c: 01 00 00 00 nop
+ 10: 01 00 00 00 nop
14: 87 a0 4a 22 fnadds %f1, %f2, %f3
18: 8d a0 8a 44 fnaddd %f2, %f4, %f6
1c: 8f a0 cb 25 fnmuls %f3, %f5, %f7
@@ -41,7 +41,7 @@ Disassembly of section .text:
7c: 95 f9 11 c6 fnumaddd %f4, %f6, %f8, %f10
80: 8f b1 42 26 addxc %g5, %g6, %g7
84: 97 b2 42 6a addxccc %o1, %o2, %o3
- 88: 8d b0 02 a0 random %f6
+ 88: 01 00 00 00 nop
8c: 9f b3 42 ce umulxhi %o5, %sp, %o7
90: b5 b0 02 f9 lzcnt %i1, %i2
94: 81 b0 03 7b cmask8 %i3
diff --git a/gas/testsuite/gas/sparc/hpcvis3.s b/gas/testsuite/gas/sparc/hpcvis3.s
index e960557..0fe151c 100644
--- a/gas/testsuite/gas/sparc/hpcvis3.s
+++ b/gas/testsuite/gas/sparc/hpcvis3.s
@@ -1,10 +1,10 @@
# Test HPC/VIS3 instructions
.text
- rd %cps, %g1
- wr %g2, 0x3, %cps
+ nop
+ nop
ldx [%g3], %efsr
- chkpt 1f
-1: commit
+ nop
+1: nop
fnadds %f1, %f2, %f3
fnaddd %f2, %f4, %f6
fnmuls %f3, %f5, %f7
@@ -34,7 +34,7 @@
fnumaddd %f4, %f6, %f8, %f10
addxc %g5, %g6, %g7
addxccc %o1, %o2, %o3
- random %f6
+ nop
umulxhi %o5, %o6, %o7
lzcnt %i1, %i2
cmask8 %i3
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 67176e6..ea5b6ca 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -925,8 +925,6 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "wr", F3(2, 0x30, 1)|RD(26), F3(~2, ~0x30, ~1)|RD(~26), "1,i,_", 0, HWCAP_CBCOND, v9b }, /* wr r,i,%cfr */
{ "wr", F3(2, 0x30, 0)|RD(27), F3(~2, ~0x30, ~0)|RD(~27)|ASI(~0), "1,2,_", 0, HWCAP_PAUSE, v9b }, /* wr r,r,%pause */
{ "wr", F3(2, 0x30, 1)|RD(27), F3(~2, ~0x30, ~1)|RD(~27), "1,i,_", 0, HWCAP_PAUSE, v9b }, /* wr r,i,%pause */
-{ "wr", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0), "1,2,_", 0, HWCAP_VIS3, v9b }, /* wr r,r,%cps */
-{ "wr", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28), "1,i,_", 0, HWCAP_VIS3, v9b }, /* wr r,i,%cps */
{ "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, v9b }, /* wr %g0,i,%pause */
@@ -951,7 +949,6 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, HWCAP_VIS2, v9b }, /* rd %sys_tick,r */
{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, HWCAP_VIS2, v9b }, /* rd %sys_tick_cmpr,r */
{ "rd", F3(2, 0x28, 0)|RS1(26), F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0), "/,d", 0, HWCAP_CBCOND, v9b }, /* rd %cfr,r */
-{ "rd", F3(2, 0x28, 0)|RS1(28), F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0), "/,d", 0, HWCAP_VIS3, v9b }, /* rd %cps,r */
{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, 0, v9 }, /* rdpr %priv,r */
{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, 0, v9 }, /* wrpr r1,r2,%priv */
@@ -1118,8 +1115,6 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,%o7 */
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, 0, v6 },
-{ "chkpt", F2(0, 1)|CONDA|ANNUL|(1<<20), F2(~0, ~1)|((~CONDA)&COND(~0)), "G", 0, HWCAP_TRANS, v9b },
-
/* Conditional instructions.
Because this part of the table was such a mess earlier, I have
@@ -1937,7 +1932,6 @@ SLCBCC("cbnefr", 15),
{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", HWCAP_VIS2, 0, v9b },
-{ "commit", F3(2, 0x3e, 0)|RD(30), F3(~2, ~0x3e, ~0)|RD(~30)|RS1_G0|SIMM13(~0), "", 0, HWCAP_TRANS, v9b },
{ "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
{ "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
{ "fnmuls", F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
@@ -1969,7 +1963,6 @@ SLCBCC("cbnefr", 15),
{ "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
{ "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3, v9b },
{ "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3, v9b },
-{ "random", F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "H", F_FLOAT, HWCAP_RANDOM, v9b },
{ "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3, v9b },
{ "lzcnt", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, v9b },
{ "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_ALIAS, HWCAP_VIS3, v9b },
--
1.7.10.4