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[PATCH 8/9] gas, opcodes: SPARC M7 support: %mcdper ancillary state register.

From: "Jose E. Marchesi" <jose dot marchesi at oracle dot com>
To: binutils at sourceware dot org
Cc: davem at davemloft dot net
Date: Thu, 2 Oct 2014 18:19:41 +0200
Subject: [PATCH 8/9] gas, opcodes: SPARC M7 support: %mcdper ancillary state register.
Authentication-results: sourceware.org; auth=none
References: <1412266782-14873-1-git-send-email-jose dot marchesi at oracle dot com>

This patch adds support for the %mcdper (%asr14) ancillary state
register introduced in OSA2015.  The corresponding rdasr/wrasr
instruction have been also added.

Tested in sparc64-unknown-linux-gnu.

gas/ChangeLog:

  2014-10-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_ip): Handle the %mcdper ancillary state
	register as an operand.

gas/testsuite/ChangeLog:

  2014-10-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* gas/sparc/sparc.exp (sparc_elf_setup): Run the mcdper test.

	* gas/sparc/mcdper.s: New file.
	* gas/sparc/mcdper.d: Likewise.

include/opcode/ChangeLog:

  2014-10-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc.h (sparc_opcode): Document the new operand kind `{',
	corresponding to the mcdper ancillary state register.

opcodes/ChangeLog:

  2014-10-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc-opcodes): Add rd/wr instructions for
	accessing the %mcdper ancillary state register.

	* sparc-dis.c (print_insn_sparc): Handle the %mcdper ancillary
	state register.
---
 gas/ChangeLog                     |    5 +++++
 gas/config/tc-sparc.c             |    6 ++++++
 gas/testsuite/ChangeLog           |    7 +++++++
 gas/testsuite/gas/sparc/mcdper.d  |   15 +++++++++++++++
 gas/testsuite/gas/sparc/mcdper.s  |    5 +++++
 gas/testsuite/gas/sparc/sparc.exp |    1 +
 include/opcode/ChangeLog          |    5 +++++
 include/opcode/sparc.h            |    1 +
 opcodes/ChangeLog                 |    8 ++++++++
 opcodes/sparc-dis.c               |    4 ++++
 opcodes/sparc-opc.c               |    3 +++
 11 files changed, 60 insertions(+)
 create mode 100644 gas/testsuite/gas/sparc/mcdper.d
 create mode 100644 gas/testsuite/gas/sparc/mcdper.s

diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index 7af5911..c808b45 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -2897,6 +2897,12 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 	      s += 5;
 	      continue;
 
+	    case '{':
+	      if (strncmp (s, "%mcdper",7) != 0)
+		break;
+	      s += 7;
+	      continue;
+
 	    case 'E':
 	      if (strncmp (s, "%ccr", 4) != 0)
 		break;
diff --git a/gas/testsuite/gas/sparc/mcdper.d b/gas/testsuite/gas/sparc/mcdper.d
new file mode 100644
index 0000000..9e0c7e2
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mcdper.d
@@ -0,0 +1,15 @@
+#as: -Av9x
+#objdump: -dr
+#name: sparc OSA2015 %mcdper asr
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	83 43 80 00 	rd  %mcdper, %g1
+   4:	9d 80 60 03 	wr  %g1, 3, %mcdper
+   8:	9d 80 40 02 	wr  %g1, %g2, %mcdper
+
+
+
diff --git a/gas/testsuite/gas/sparc/mcdper.s b/gas/testsuite/gas/sparc/mcdper.s
new file mode 100644
index 0000000..0891424
--- /dev/null
+++ b/gas/testsuite/gas/sparc/mcdper.s
@@ -0,0 +1,5 @@
+# Test reads/writes to the %mcdper asr register
+	.text
+	rd	%mcdper, %g1
+	wr	%g1, 0x3, %mcdper
+	wr	%g1, %g2, %mcdper
diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index c7d99a9..c8980cf 100644
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -91,6 +91,7 @@ if [istarget sparc*-*-*] {
     run_dump_test "edge"
     run_dump_test "flush"
     run_dump_test "mwait"
+    run_dump_test "mcdper"
 
     run_list_test "pr4587" ""
 }
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index e41a97e..6849c23 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -226,6 +226,7 @@ typedef struct sparc_opcode
 	s	%fprs. (v9)
 	P	%pc.  (v9)
 	W	%tick.	(v9)
+	{	%mcdper. (v9b)
 	o	%asi. (v9)
 	6	%fcc0. (v9)
 	7	%fcc1. (v9)
diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c
index 49a16c2..e3389a6 100644
--- a/opcodes/sparc-dis.c
+++ b/opcodes/sparc-dis.c
@@ -793,6 +793,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
 		    (*info->fprintf_func) (stream, "%%fprs");
 		    break;
 
+		  case '{':
+		    (*info->fprintf_func) (stream, "%%mcdper");
+		    break;
+
 		  case 'o':
 		    (*info->fprintf_func) (stream, "%%asi");
 		    break;
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index ba1ea25..75a8f75 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -901,6 +901,8 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "wr", F3(2, 0x30, 1)|RD(3),	F3(~2, ~0x30, ~1)|RD(~3),		"1,i,o", 0, 0, 0, v9 }, /* wr r,i,%asi */
 { "wr", F3(2, 0x30, 0)|RD(6),	F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0),	"1,2,s", 0, 0, 0, v9 }, /* wr r,r,%fprs */
 { "wr", F3(2, 0x30, 1)|RD(6),	F3(~2, ~0x30, ~1)|RD(~6),		"1,i,s", 0, 0, 0, v9 }, /* wr r,i,%fprs */
+{ "wr", F3(2, 0x30, 0)|RD(14),  F3(~2, ~0x30, ~0)|RD(~14),              "1,2,{", 0, 0, HWCAP2_SPARC5, v9b }, /* wr r,r,%mcdper */
+{ "wr", F3(2, 0x30, 1)|RD(14),  F3(~2, ~0x30, ~1)|RD(~14),              "1,i,{", 0, 0, HWCAP2_SPARC5, v9b }, /* wr r,i,%mcdper */
 
 { "wr", F3(2, 0x30, 0)|RD(16),	F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0),	"1,2,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,r,%pcr */
 { "wr", F3(2, 0x30, 1)|RD(16),	F3(~2, ~0x30, ~1)|RD(~16),		"1,i,_", 0, HWCAP_VIS, 0, v9a }, /* wr r,i,%pcr */
@@ -942,6 +944,7 @@ const struct sparc_opcode sparc_opcodes[] = {
 { "rd",	F3(2, 0x28, 0)|RS1(4),		F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0),	"W,d", 0, 0, 0, v9 }, /* rd %tick,r */
 { "rd",	F3(2, 0x28, 0)|RS1(5),		F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0),	"P,d", 0, 0, 0, v9 }, /* rd %pc,r */
 { "rd",	F3(2, 0x28, 0)|RS1(6),		F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0),	"s,d", 0, 0, 0, v9 }, /* rd %fprs,r */
+{ "rd", F3(2, 0x28, 0)|RS1(14),         F3(~2, ~0x28, ~0)|RS1(~14)|SIMM13(~0),  "{,d", 0, 0, HWCAP2_SPARC5, v9b }, /* rd %mcdper,r */
 
 { "rd",	F3(2, 0x28, 0)|RS1(16),		F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0),	"/,d", 0, HWCAP_VIS, 0, v9a }, /* rd %pcr,r */
 { "rd",	F3(2, 0x28, 0)|RS1(17),		F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0),	"/,d", 0, HWCAP_VIS, 0, v9a }, /* rd %pic,r */
-- 
1.7.10.4

References:
- [PATCH 0/9] Add support for the SPARC M7 cpu to binutils
  - From: Jose E. Marchesi

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