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Re: [PATCH] Add support for MIPS eretnc MIPS32r5 instruction
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: Andrew Bennett <Andrew dot Bennett at imgtec dot com>
- Cc: "binutils\ at sourceware dot org" <binutils at sourceware dot org>, Matthew Fortune <Matthew dot Fortune at imgtec dot com>, Saeed Ghazanfar <Saeed dot Ghazanfar at imgtec dot com>, Rich Fuhler <Rich dot Fuhler at imgtec dot com>
- Date: Thu, 01 May 2014 21:44:00 +0100
- Subject: Re: [PATCH] Add support for MIPS eretnc MIPS32r5 instruction
- Authentication-results: sourceware.org; auth=none
- References: <0DA23CC379F5F945ACB41CF394B9827755A9EA at LEMAIL01 dot le dot imgtec dot org> <87wqegw90k dot fsf at sandifor-thinkpad dot stglab dot manchester dot uk dot ibm dot com> <0DA23CC379F5F945ACB41CF394B98277574ADA at LEMAIL01 dot le dot imgtec dot org> <0DA23CC379F5F945ACB41CF394B98277576B72 at LEMAIL01 dot le dot imgtec dot org>
Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
> diff --git a/bfd/archures.c b/bfd/archures.c
> index 4ab5f1d..20e4d0b 100644
> --- a/bfd/archures.c
> +++ b/bfd/archures.c
> @@ -182,8 +182,12 @@ DESCRIPTION
> .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
> .#define bfd_mach_mipsisa32 32
> .#define bfd_mach_mipsisa32r2 33
> +.#define bfd_mach_mipsisa32r3 34
> +.#define bfd_mach_mipsisa32r5 35
> .#define bfd_mach_mipsisa64 64
> .#define bfd_mach_mipsisa64r2 65
> +.#define bfd_mach_mipsisa64r3 66
> +.#define bfd_mach_mipsisa64r5 67
> .#define bfd_mach_mips_micromips 96
> . bfd_arch_i386, {* Intel 386 *}
> .#define bfd_mach_i386_intel_syntax (1 << 0)
Let's keep the gap in the bfd_mach_mips* numbering too, so r5 is 36 and 68.
> diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
> index 0c5e82d..e940ba3 100644
> --- a/gas/doc/c-mips.texi
> +++ b/gas/doc/c-mips.texi
> @@ -81,16 +81,22 @@ VxWorks-style position-independent macro expansions.
> @itemx -mips5
> @itemx -mips32
> @itemx -mips32r2
> +@itemx -mips32r5
> +@itemx -mips32r6
> @itemx -mips64
> @itemx -mips64r2
> +@itemx -mips64r5
> +@itemx -mips64r6
Should be r3 and r5 rather than r5 and r6.
Unfortunately this is duplicated in as.texinfo, so we need to update both.
> @@ -1079,6 +1079,10 @@ struct mips_opcode
> #define INSN_ISA4_32 12
> #define INSN_ISA4_32R2 13
> #define INSN_ISA5_32R2 14
> +#define INSN_ISA32R3 15
> +#define INSN_ISA32R5 16
> +#define INSN_ISA64R3 17
> +#define INSN_ISA64R5 18
I realise this'll be a pain, sorry, but the new INSN_*s should go
just before:
/* Below this point the INSN_* values correspond to combinations of ISAs.
They are only for use in the opcodes table to indicate membership of
a combination of ISAs that cannot be expressed using the usual inclusion
ordering on the above INSN_* values. */
so that the array stops at r5 and doesn't include the compound groups.
Feel free to leave a gap for r6 :-) Might as well keep the 32rNs
and 64rNs together at the same time.
> /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
> INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
We should update this comment too.
> @@ -1089,7 +1093,8 @@ struct mips_opcode
> (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
> is non-zero. */
> static const unsigned int mips_isa_table[] =
> - { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
> + { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff,
> + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x7e63, 0xfe63, 0x17fff, 0x3ffff };
This is a pretty hairy table, so it's probably worth making all entries
have 5 digits.
...actually, keeping it like this is just too much hassle. I've installed
the patch below to redo it more symbolically. Hopefully then it'll be
easier to update.
> @@ -1203,9 +1212,13 @@ static const unsigned int mips_isa_table[] =
> #define CPU_MIPS16 16
> #define CPU_MIPS32 32
> #define CPU_MIPS32R2 33
> +#define CPU_MIPS32R3 34
> +#define CPU_MIPS32R5 35
> #define CPU_MIPS5 5
> #define CPU_MIPS64 64
> #define CPU_MIPS64R2 65
> +#define CPU_MIPS64R3 66
> +#define CPU_MIPS64R5 67
> #define CPU_SB1 12310201 /* octal 'SB', 01. */
> #define CPU_LOONGSON_2E 3001
> #define CPU_LOONGSON_2F 3002
Same numbering comments as for bfd_mach_*
Looks good otherwise, thanks, but we'll need to wait for the copyright
thing to be sorted out.
Richard
include/opcode/
* mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
Index: include/opcode/mips.h
===================================================================
--- include/opcode/mips.h 2014-05-01 21:29:10.777977139 +0100
+++ include/opcode/mips.h 2014-05-01 21:35:21.899091547 +0100
@@ -1080,16 +1080,33 @@ #define INSN_ISA4_32 12
#define INSN_ISA4_32R2 13
#define INSN_ISA5_32R2 14
-/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
- INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
- this table describes whether at least one of the ISAs described by X
- is/are implemented by ISA Y. (Think of Y as the ISA level supported by
- a particular core and X as the ISA level(s) at which a certain instruction
- is defined.) The ISA(s) described by X is/are implemented by Y iff
- (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
- is non-zero. */
-static const unsigned int mips_isa_table[] =
- { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
+/* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */
+#define ISAF(X) (1 << (INSN_ISA##X - 1))
+#define INSN_UPTO1 ISAF(1)
+#define INSN_UPTO2 INSN_UPTO1 | ISAF(2)
+#define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2)
+#define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2)
+#define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2)
+#define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32)
+#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \
+ | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2)
+#define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32)
+#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2)
+
+/* The same information in table form: bit INSN_ISA<X> - 1 of index
+ INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */
+static const unsigned int mips_isa_table[] = {
+ INSN_UPTO1,
+ INSN_UPTO2,
+ INSN_UPTO3,
+ INSN_UPTO4,
+ INSN_UPTO5,
+ INSN_UPTO32,
+ INSN_UPTO32R2,
+ INSN_UPTO64,
+ INSN_UPTO64R2
+};
+#undef ISAF
/* Masks used for Chip specific instructions. */
#define INSN_CHIP_MASK 0xc3ff0f20