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[PATCH 01/14] or32 and openrisc opcode changes
- From: Christian Svensson <blue at cmd dot nu>
- To: binutils at sourceware dot org
- Cc: openrisc at lists dot openrisc dot net,openrisc at lists dot opencores dot org
- Date: Sat, 8 Mar 2014 12:05:54 +0000
- Subject: [PATCH 01/14] or32 and openrisc opcode changes
- Authentication-results: sourceware.org; auth=none
This patch removes opcodes code for old OpenRISC targets.
---
opcodes/Makefile.am | 20 +-
opcodes/Makefile.in | 27 +-
opcodes/configure | 2 -
opcodes/configure.in | 2 -
opcodes/disassemble.c | 15 -
opcodes/openrisc-asm.c | 648 -----------------------------
opcodes/openrisc-desc.c | 1018 ----------------------------------------------
opcodes/openrisc-desc.h | 288 -------------
opcodes/openrisc-dis.c | 555 -------------------------
opcodes/openrisc-ibld.c | 1008 ----------------------------------------------
opcodes/openrisc-opc.c | 682 -------------------------------
opcodes/openrisc-opc.h | 113 ------
opcodes/or32-dis.c | 325 ---------------
opcodes/or32-opc.c | 1030 -----------------------------------------------
14 files changed, 4 insertions(+), 5729 deletions(-)
delete mode 100644 opcodes/openrisc-asm.c
delete mode 100644 opcodes/openrisc-desc.c
delete mode 100644 opcodes/openrisc-desc.h
delete mode 100644 opcodes/openrisc-dis.c
delete mode 100644 opcodes/openrisc-ibld.c
delete mode 100644 opcodes/openrisc-opc.c
delete mode 100644 opcodes/openrisc-opc.h
delete mode 100644 opcodes/or32-dis.c
delete mode 100644 opcodes/or32-opc.c
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 0f2fb9d..eeba51a 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -79,7 +79,6 @@ HFILES = \
mep-desc.h mep-opc.h \
microblaze-opc.h \
mt-desc.h mt-opc.h \
- openrisc-desc.h openrisc-opc.h \
score-opc.h \
sh-opc.h \
sh64-opc.h \
@@ -211,13 +210,6 @@ TARGET_LIBOPCODES_CFILES = \
nios2-dis.c \
nios2-opc.c \
ns32k-dis.c \
- openrisc-asm.c \
- openrisc-desc.c \
- openrisc-dis.c \
- openrisc-ibld.c \
- openrisc-opc.c \
- or32-dis.c \
- or32-opc.c \
pdp11-dis.c \
pdp11-opc.c \
pj-dis.c \
@@ -355,7 +347,7 @@ po/POTFILES.in: @MAINT@ Makefile
CLEANFILES = \
stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
stamp-m32c stamp-m32r stamp-mep stamp-mt \
- stamp-openrisc stamp-xc16x stamp-xstormy16 \
+ stamp-xc16x stamp-xstormy16 \
libopcodes.a stamp-lib
@@ -371,7 +363,7 @@ CGENDEPS = \
$(CGENDIR)/opc-opinst.scm \
cgen-asm.in cgen-dis.in cgen-ibld.in
-CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
+CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt xc16x xstormy16
if CGEN_MAINT
EPIPHANY_DEPS = stamp-epiphany
@@ -384,7 +376,6 @@ M32C_DEPS = stamp-m32c
M32R_DEPS = stamp-m32r
MEP_DEPS = stamp-mep
MT_DEPS = stamp-mt
-OPENRISC_DEPS = stamp-openrisc
XC16X_DEPS = stamp-xc16x
XSTORMY16_DEPS = stamp-xstormy16
else
@@ -398,7 +389,6 @@ M32C_DEPS =
M32R_DEPS =
MEP_DEPS =
MT_DEPS =
-OPENRISC_DEPS =
XC16X_DEPS =
XSTORMY16_DEPS =
endif
@@ -492,12 +482,6 @@ stamp-mt: $(CGENDEPS) $(CPUDIR)/mt.cpu $(CPUDIR)/mt.opc
archfile=$(CPUDIR)/mt.cpu \
opcfile=$(CPUDIR)/mt.opc extrafiles=
-$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
- @true
-stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
- $(MAKE) run-cgen arch=openrisc prefix=openrisc options= \
- archfile=$(CPUDIR)/openrisc.cpu opcfile=$(CPUDIR)/openrisc.opc extrafiles=
-
$(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS)
@true
stamp-xc16x: $(CGENDEPS) $(CPUDIR)/xc16x.cpu $(CPUDIR)/xc16x.opc
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index b161d62..18e0b1d 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -350,7 +350,6 @@ HFILES = \
mep-desc.h mep-opc.h \
microblaze-opc.h \
mt-desc.h mt-opc.h \
- openrisc-desc.h openrisc-opc.h \
score-opc.h \
sh-opc.h \
sh64-opc.h \
@@ -483,13 +482,6 @@ TARGET_LIBOPCODES_CFILES = \
nios2-dis.c \
nios2-opc.c \
ns32k-dis.c \
- openrisc-asm.c \
- openrisc-desc.c \
- openrisc-dis.c \
- openrisc-ibld.c \
- openrisc-opc.c \
- or32-dis.c \
- or32-opc.c \
pdp11-dis.c \
pdp11-opc.c \
pj-dis.c \
@@ -596,7 +588,7 @@ POTFILES = $(HFILES) $(CFILES)
CLEANFILES = \
stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \
stamp-m32c stamp-m32r stamp-mep stamp-mt \
- stamp-openrisc stamp-xc16x stamp-xstormy16 \
+ stamp-xc16x stamp-xstormy16 \
libopcodes.a stamp-lib
CGENDIR = @cgendir@
@@ -610,7 +602,7 @@ CGENDEPS = \
$(CGENDIR)/opc-opinst.scm \
cgen-asm.in cgen-dis.in cgen-ibld.in
-CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16
+CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt xc16x xstormy16
@CGEN_MAINT_FALSE@EPIPHANY_DEPS =
@CGEN_MAINT_TRUE@EPIPHANY_DEPS = stamp-epiphany
@CGEN_MAINT_FALSE@FR30_DEPS =
@@ -631,8 +623,6 @@ CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x x
@CGEN_MAINT_TRUE@MEP_DEPS = stamp-mep
@CGEN_MAINT_FALSE@MT_DEPS =
@CGEN_MAINT_TRUE@MT_DEPS = stamp-mt
-@CGEN_MAINT_FALSE@OPENRISC_DEPS =
-@CGEN_MAINT_TRUE@OPENRISC_DEPS = stamp-openrisc
@CGEN_MAINT_FALSE@XC16X_DEPS =
@CGEN_MAINT_TRUE@XC16X_DEPS = stamp-xc16x
@CGEN_MAINT_FALSE@XSTORMY16_DEPS =
@@ -886,13 +876,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nios2-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nios2-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ns32k-dis.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/openrisc-asm.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/openrisc-desc.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/openrisc-dis.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/openrisc-ibld.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/openrisc-opc.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or32-dis.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/or32-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pdp11-dis.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pdp11-opc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pj-dis.Plo@am__quote@
@@ -1371,12 +1354,6 @@ stamp-mt: $(CGENDEPS) $(CPUDIR)/mt.cpu $(CPUDIR)/mt.opc
archfile=$(CPUDIR)/mt.cpu \
opcfile=$(CPUDIR)/mt.opc extrafiles=
-$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
- @true
-stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
- $(MAKE) run-cgen arch=openrisc prefix=openrisc options= \
- archfile=$(CPUDIR)/openrisc.cpu opcfile=$(CPUDIR)/openrisc.opc extrafiles=
-
$(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS)
@true
stamp-xc16x: $(CGENDEPS) $(CPUDIR)/xc16x.cpu $(CPUDIR)/xc16x.opc
diff --git a/opcodes/configure b/opcodes/configure
index eb7532e..28c4466 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12549,8 +12549,6 @@ if test x${all_targets} = xfalse ; then
bfd_nds32_arch) ta="$ta nds32-asm.lo nds32-dis.lo" ;;
bfd_nios2_arch) ta="$ta nios2-dis.lo nios2-opc.lo" ;;
bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;;
- bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;;
- bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;;
bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;;
bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;;
bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 6606b1c..244b4c0 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -296,8 +296,6 @@ if test x${all_targets} = xfalse ; then
bfd_nds32_arch) ta="$ta nds32-asm.lo nds32-dis.lo" ;;
bfd_nios2_arch) ta="$ta nios2-dis.lo nios2-opc.lo" ;;
bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;;
- bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;;
- bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;;
bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;;
bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;;
bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 79d41a4..4b3b50d 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -68,8 +68,6 @@
#define ARCH_nds32
#define ARCH_nios2
#define ARCH_ns32k
-#define ARCH_openrisc
-#define ARCH_or32
#define ARCH_pdp11
#define ARCH_pj
#define ARCH_powerpc
@@ -351,19 +349,6 @@ disassembler (abfd)
disassemble = print_insn_little_nios2;
break;
#endif
-#ifdef ARCH_openrisc
- case bfd_arch_openrisc:
- disassemble = print_insn_openrisc;
- break;
-#endif
-#ifdef ARCH_or32
- case bfd_arch_or32:
- if (bfd_big_endian (abfd))
- disassemble = print_insn_big_or32;
- else
- disassemble = print_insn_little_or32;
- break;
-#endif
#ifdef ARCH_pdp11
case bfd_arch_pdp11:
disassemble = print_insn_pdp11;
diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c
deleted file mode 100644
index 98e22d8..0000000
--- a/opcodes/openrisc-asm.c
+++ /dev/null
@@ -1,648 +0,0 @@
-/* Assembler interface for targets using CGEN. -*- C -*-
- CGEN: Cpu tools GENerator
-
- THIS FILE IS MACHINE GENERATED WITH CGEN.
- - the resultant file is machine generated, cgen-asm.in isn't
-
- Copyright (C) 1996-2014 Free Software Foundation, Inc.
-
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-
-/* ??? Eventually more and more of this stuff can go to cpu-independent files.
- Keep that in mind. */
-
-#include "sysdep.h"
-#include <stdio.h>
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "openrisc-desc.h"
-#include "openrisc-opc.h"
-#include "opintl.h"
-#include "xregex.h"
-#include "libiberty.h"
-#include "safe-ctype.h"
-
-#undef min
-#define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
-#define max(a,b) ((a) > (b) ? (a) : (b))
-
-static const char * parse_insn_normal
- (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
-
-/* -- assembler routines inserted here. */
-
-/* -- asm.c */
-
-static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
-
-#define CGEN_VERBOSE_ASSEMBLER_ERRORS
-
-long
-openrisc_sign_extend_16bit (long value)
-{
- return ((value & 0xffff) ^ 0x8000) - 0x8000;
-}
-
-/* Handle hi(). */
-
-static const char *
-parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
-{
- const char *errmsg;
- enum cgen_parse_operand_result result_type;
- unsigned long ret;
-
- if (**strp == '#')
- ++*strp;
-
- if (strncasecmp (*strp, "hi(", 3) == 0)
- {
- bfd_vma value;
-
- *strp += 3;
- errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
- & result_type, & value);
- if (**strp != ')')
- return MISSING_CLOSING_PARENTHESIS;
-
- ++*strp;
- if (errmsg == NULL
- && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
- value >>= 16;
- ret = value;
- }
- else
- {
- if (**strp == '-')
- {
- long value;
-
- errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
- ret = value;
- }
- else
- {
- unsigned long value;
-
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
- ret = value;
- }
- }
-
- *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000;
- return errmsg;
-}
-
-/* Handle lo(). */
-
-static const char *
-parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep)
-{
- const char *errmsg;
- enum cgen_parse_operand_result result_type;
- unsigned long ret;
-
- if (**strp == '#')
- ++*strp;
-
- if (strncasecmp (*strp, "lo(", 3) == 0)
- {
- bfd_vma value;
-
- *strp += 3;
- errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
- & result_type, & value);
- if (**strp != ')')
- return MISSING_CLOSING_PARENTHESIS;
-
- ++*strp;
- ret = value;
- }
- else
- {
- if (**strp == '-')
- {
- long value;
-
- errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
- ret = value;
- }
- else
- {
- unsigned long value;
-
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
- ret = value;
- }
- }
-
- *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000;
- return errmsg;
-}
-
-/* -- */
-
-const char * openrisc_cgen_parse_operand
- (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
-
-/* Main entry point for operand parsing.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `parse_insn_normal', but keeping it
- separate makes clear the interface between `parse_insn_normal' and each of
- the handlers. */
-
-const char *
-openrisc_cgen_parse_operand (CGEN_CPU_DESC cd,
- int opindex,
- const char ** strp,
- CGEN_FIELDS * fields)
-{
- const char * errmsg = NULL;
- /* Used by scalar operands that still need to be parsed. */
- long junk ATTRIBUTE_UNUSED;
-
- switch (opindex)
- {
- case OPENRISC_OPERAND_ABS_26 :
- {
- bfd_vma value = 0;
- errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_ABS_26, 0, NULL, & value);
- fields->f_abs26 = value;
- }
- break;
- case OPENRISC_OPERAND_DISP_26 :
- {
- bfd_vma value = 0;
- errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_DISP_26, 0, NULL, & value);
- fields->f_disp26 = value;
- }
- break;
- case OPENRISC_OPERAND_HI16 :
- errmsg = parse_hi16 (cd, strp, OPENRISC_OPERAND_HI16, (long *) (& fields->f_simm16));
- break;
- case OPENRISC_OPERAND_LO16 :
- errmsg = parse_lo16 (cd, strp, OPENRISC_OPERAND_LO16, (long *) (& fields->f_lo16));
- break;
- case OPENRISC_OPERAND_OP_F_23 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_OP_F_23, (unsigned long *) (& fields->f_op4));
- break;
- case OPENRISC_OPERAND_OP_F_3 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_OP_F_3, (unsigned long *) (& fields->f_op5));
- break;
- case OPENRISC_OPERAND_RA :
- errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r2);
- break;
- case OPENRISC_OPERAND_RB :
- errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r3);
- break;
- case OPENRISC_OPERAND_RD :
- errmsg = cgen_parse_keyword (cd, strp, & openrisc_cgen_opval_h_gr, & fields->f_r1);
- break;
- case OPENRISC_OPERAND_SIMM_16 :
- errmsg = cgen_parse_signed_integer (cd, strp, OPENRISC_OPERAND_SIMM_16, (long *) (& fields->f_simm16));
- break;
- case OPENRISC_OPERAND_UI16NC :
- errmsg = parse_lo16 (cd, strp, OPENRISC_OPERAND_UI16NC, (long *) (& fields->f_i16nc));
- break;
- case OPENRISC_OPERAND_UIMM_16 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_UIMM_16, (unsigned long *) (& fields->f_uimm16));
- break;
- case OPENRISC_OPERAND_UIMM_5 :
- errmsg = cgen_parse_unsigned_integer (cd, strp, OPENRISC_OPERAND_UIMM_5, (unsigned long *) (& fields->f_uimm5));
- break;
-
- default :
- /* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
- abort ();
- }
-
- return errmsg;
-}
-
-cgen_parse_fn * const openrisc_cgen_parse_handlers[] =
-{
- parse_insn_normal,
-};
-
-void
-openrisc_cgen_init_asm (CGEN_CPU_DESC cd)
-{
- openrisc_cgen_init_opcode_table (cd);
- openrisc_cgen_init_ibld_table (cd);
- cd->parse_handlers = & openrisc_cgen_parse_handlers[0];
- cd->parse_operand = openrisc_cgen_parse_operand;
-#ifdef CGEN_ASM_INIT_HOOK
-CGEN_ASM_INIT_HOOK
-#endif
-}
-
-
-
-/* Regex construction routine.
-
- This translates an opcode syntax string into a regex string,
- by replacing any non-character syntax element (such as an
- opcode) with the pattern '.*'
-
- It then compiles the regex and stores it in the opcode, for
- later use by openrisc_cgen_assemble_insn
-
- Returns NULL for success, an error message for failure. */
-
-char *
-openrisc_cgen_build_insn_regex (CGEN_INSN *insn)
-{
- CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
- const char *mnem = CGEN_INSN_MNEMONIC (insn);
- char rxbuf[CGEN_MAX_RX_ELEMENTS];
- char *rx = rxbuf;
- const CGEN_SYNTAX_CHAR_TYPE *syn;
- int reg_err;
-
- syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
-
- /* Mnemonics come first in the syntax string. */
- if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
- return _("missing mnemonic in syntax string");
- ++syn;
-
- /* Generate a case sensitive regular expression that emulates case
- insensitive matching in the "C" locale. We cannot generate a case
- insensitive regular expression because in Turkish locales, 'i' and 'I'
- are not equal modulo case conversion. */
-
- /* Copy the literal mnemonic out of the insn. */
- for (; *mnem; mnem++)
- {
- char c = *mnem;
-
- if (ISALPHA (c))
- {
- *rx++ = '[';
- *rx++ = TOLOWER (c);
- *rx++ = TOUPPER (c);
- *rx++ = ']';
- }
- else
- *rx++ = c;
- }
-
- /* Copy any remaining literals from the syntax string into the rx. */
- for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
- {
- if (CGEN_SYNTAX_CHAR_P (* syn))
- {
- char c = CGEN_SYNTAX_CHAR (* syn);
-
- switch (c)
- {
- /* Escape any regex metacharacters in the syntax. */
- case '.': case '[': case '\\':
- case '*': case '^': case '$':
-
-#ifdef CGEN_ESCAPE_EXTENDED_REGEX
- case '?': case '{': case '}':
- case '(': case ')': case '*':
- case '|': case '+': case ']':
-#endif
- *rx++ = '\\';
- *rx++ = c;
- break;
-
- default:
- if (ISALPHA (c))
- {
- *rx++ = '[';
- *rx++ = TOLOWER (c);
- *rx++ = TOUPPER (c);
- *rx++ = ']';
- }
- else
- *rx++ = c;
- break;
- }
- }
- else
- {
- /* Replace non-syntax fields with globs. */
- *rx++ = '.';
- *rx++ = '*';
- }
- }
-
- /* Trailing whitespace ok. */
- * rx++ = '[';
- * rx++ = ' ';
- * rx++ = '\t';
- * rx++ = ']';
- * rx++ = '*';
-
- /* But anchor it after that. */
- * rx++ = '$';
- * rx = '\0';
-
- CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
- reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
-
- if (reg_err == 0)
- return NULL;
- else
- {
- static char msg[80];
-
- regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
- regfree ((regex_t *) CGEN_INSN_RX (insn));
- free (CGEN_INSN_RX (insn));
- (CGEN_INSN_RX (insn)) = NULL;
- return msg;
- }
-}
-
-
-/* Default insn parser.
-
- The syntax string is scanned and operands are parsed and stored in FIELDS.
- Relocs are queued as we go via other callbacks.
-
- ??? Note that this is currently an all-or-nothing parser. If we fail to
- parse the instruction, we return 0 and the caller will start over from
- the beginning. Backtracking will be necessary in parsing subexpressions,
- but that can be handled there. Not handling backtracking here may get
- expensive in the case of the m68k. Deal with later.
-
- Returns NULL for success, an error message for failure. */
-
-static const char *
-parse_insn_normal (CGEN_CPU_DESC cd,
- const CGEN_INSN *insn,
- const char **strp,
- CGEN_FIELDS *fields)
-{
- /* ??? Runtime added insns not handled yet. */
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- const char *str = *strp;
- const char *errmsg;
- const char *p;
- const CGEN_SYNTAX_CHAR_TYPE * syn;
-#ifdef CGEN_MNEMONIC_OPERANDS
- /* FIXME: wip */
- int past_opcode_p;
-#endif
-
- /* For now we assume the mnemonic is first (there are no leading operands).
- We can parse it without needing to set up operand parsing.
- GAS's input scrubber will ensure mnemonics are lowercase, but we may
- not be called from GAS. */
- p = CGEN_INSN_MNEMONIC (insn);
- while (*p && TOLOWER (*p) == TOLOWER (*str))
- ++p, ++str;
-
- if (* p)
- return _("unrecognized instruction");
-
-#ifndef CGEN_MNEMONIC_OPERANDS
- if (* str && ! ISSPACE (* str))
- return _("unrecognized instruction");
-#endif
-
- CGEN_INIT_PARSE (cd);
- cgen_init_parse_operand (cd);
-#ifdef CGEN_MNEMONIC_OPERANDS
- past_opcode_p = 0;
-#endif
-
- /* We don't check for (*str != '\0') here because we want to parse
- any trailing fake arguments in the syntax string. */
- syn = CGEN_SYNTAX_STRING (syntax);
-
- /* Mnemonics come first for now, ensure valid string. */
- if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
- abort ();
-
- ++syn;
-
- while (* syn != 0)
- {
- /* Non operand chars must match exactly. */
- if (CGEN_SYNTAX_CHAR_P (* syn))
- {
- /* FIXME: While we allow for non-GAS callers above, we assume the
- first char after the mnemonic part is a space. */
- /* FIXME: We also take inappropriate advantage of the fact that
- GAS's input scrubber will remove extraneous blanks. */
- if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
- {
-#ifdef CGEN_MNEMONIC_OPERANDS
- if (CGEN_SYNTAX_CHAR(* syn) == ' ')
- past_opcode_p = 1;
-#endif
- ++ syn;
- ++ str;
- }
- else if (*str)
- {
- /* Syntax char didn't match. Can't be this insn. */
- static char msg [80];
-
- /* xgettext:c-format */
- sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
- CGEN_SYNTAX_CHAR(*syn), *str);
- return msg;
- }
- else
- {
- /* Ran out of input. */
- static char msg [80];
-
- /* xgettext:c-format */
- sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
- CGEN_SYNTAX_CHAR(*syn));
- return msg;
- }
- continue;
- }
-
-#ifdef CGEN_MNEMONIC_OPERANDS
- (void) past_opcode_p;
-#endif
- /* We have an operand of some sort. */
- errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields);
- if (errmsg)
- return errmsg;
-
- /* Done with this operand, continue with next one. */
- ++ syn;
- }
-
- /* If we're at the end of the syntax string, we're done. */
- if (* syn == 0)
- {
- /* FIXME: For the moment we assume a valid `str' can only contain
- blanks now. IE: We needn't try again with a longer version of
- the insn and it is assumed that longer versions of insns appear
- before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */
- while (ISSPACE (* str))
- ++ str;
-
- if (* str != '\0')
- return _("junk at end of line"); /* FIXME: would like to include `str' */
-
- return NULL;
- }
-
- /* We couldn't parse it. */
- return _("unrecognized instruction");
-}
-
-/* Main entry point.
- This routine is called for each instruction to be assembled.
- STR points to the insn to be assembled.
- We assume all necessary tables have been initialized.
- The assembled instruction, less any fixups, is stored in BUF.
- Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
- still needs to be converted to target byte order, otherwise BUF is an array
- of bytes in target byte order.
- The result is a pointer to the insn's entry in the opcode table,
- or NULL if an error occured (an error message will have already been
- printed).
-
- Note that when processing (non-alias) macro-insns,
- this function recurses.
-
- ??? It's possible to make this cpu-independent.
- One would have to deal with a few minor things.
- At this point in time doing so would be more of a curiosity than useful
- [for example this file isn't _that_ big], but keeping the possibility in
- mind helps keep the design clean. */
-
-const CGEN_INSN *
-openrisc_cgen_assemble_insn (CGEN_CPU_DESC cd,
- const char *str,
- CGEN_FIELDS *fields,
- CGEN_INSN_BYTES_PTR buf,
- char **errmsg)
-{
- const char *start;
- CGEN_INSN_LIST *ilist;
- const char *parse_errmsg = NULL;
- const char *insert_errmsg = NULL;
- int recognized_mnemonic = 0;
-
- /* Skip leading white space. */
- while (ISSPACE (* str))
- ++ str;
-
- /* The instructions are stored in hashed lists.
- Get the first in the list. */
- ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
-
- /* Keep looking until we find a match. */
- start = str;
- for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
- {
- const CGEN_INSN *insn = ilist->insn;
- recognized_mnemonic = 1;
-
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
- /* Not usually needed as unsupported opcodes
- shouldn't be in the hash lists. */
- /* Is this insn supported by the selected cpu? */
- if (! openrisc_cgen_insn_supported (cd, insn))
- continue;
-#endif
- /* If the RELAXED attribute is set, this is an insn that shouldn't be
- chosen immediately. Instead, it is used during assembler/linker
- relaxation if possible. */
- if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
- continue;
-
- str = start;
-
- /* Skip this insn if str doesn't look right lexically. */
- if (CGEN_INSN_RX (insn) != NULL &&
- regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
- continue;
-
- /* Allow parse/insert handlers to obtain length of insn. */
- CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
-
- parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
- if (parse_errmsg != NULL)
- continue;
-
- /* ??? 0 is passed for `pc'. */
- insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
- (bfd_vma) 0);
- if (insert_errmsg != NULL)
- continue;
-
- /* It is up to the caller to actually output the insn and any
- queued relocs. */
- return insn;
- }
-
- {
- static char errbuf[150];
- const char *tmp_errmsg;
-#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
-#define be_verbose 1
-#else
-#define be_verbose 0
-#endif
-
- if (be_verbose)
- {
- /* If requesting verbose error messages, use insert_errmsg.
- Failing that, use parse_errmsg. */
- tmp_errmsg = (insert_errmsg ? insert_errmsg :
- parse_errmsg ? parse_errmsg :
- recognized_mnemonic ?
- _("unrecognized form of instruction") :
- _("unrecognized instruction"));
-
- if (strlen (start) > 50)
- /* xgettext:c-format */
- sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
- else
- /* xgettext:c-format */
- sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
- }
- else
- {
- if (strlen (start) > 50)
- /* xgettext:c-format */
- sprintf (errbuf, _("bad instruction `%.50s...'"), start);
- else
- /* xgettext:c-format */
- sprintf (errbuf, _("bad instruction `%.50s'"), start);
- }
-
- *errmsg = errbuf;
- return NULL;
- }
-}
diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c
deleted file mode 100644
index 421d5db..0000000
--- a/opcodes/openrisc-desc.c
+++ /dev/null
@@ -1,1018 +0,0 @@
-/* CPU data for openrisc.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2014 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#include "sysdep.h"
-#include <stdio.h>
-#include <stdarg.h>
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "openrisc-desc.h"
-#include "openrisc-opc.h"
-#include "opintl.h"
-#include "libiberty.h"
-#include "xregex.h"
-
-/* Attributes. */
-
-static const CGEN_ATTR_ENTRY bool_attr[] =
-{
- { "#f", 0 },
- { "#t", 1 },
- { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
-{
- { "base", MACH_BASE },
- { "openrisc", MACH_OPENRISC },
- { "or1300", MACH_OR1300 },
- { "max", MACH_MAX },
- { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
-{
- { "or32", ISA_OR32 },
- { "max", ISA_MAX },
- { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY HAS_CACHE_attr[] ATTRIBUTE_UNUSED =
-{
- { "DATA_CACHE", HAS_CACHE_DATA_CACHE },
- { "INSN_CACHE", HAS_CACHE_INSN_CACHE },
- { 0, 0 }
-};
-
-const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
- { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
- { "RESERVED", &bool_attr[0], &bool_attr[0] },
- { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
- { "SIGNED", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
- { "PC", &bool_attr[0], &bool_attr[0] },
- { "PROFILE", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
- { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
- { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
- { "SIGNED", &bool_attr[0], &bool_attr[0] },
- { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
- { "RELAX", &bool_attr[0], &bool_attr[0] },
- { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[] =
-{
- { "MACH", & MACH_attr[0], & MACH_attr[0] },
- { "ALIAS", &bool_attr[0], &bool_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
- { "COND-CTI", &bool_attr[0], &bool_attr[0] },
- { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
- { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
- { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
- { "RELAXED", &bool_attr[0], &bool_attr[0] },
- { "NO-DIS", &bool_attr[0], &bool_attr[0] },
- { "PBB", &bool_attr[0], &bool_attr[0] },
- { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-/* Instruction set variants. */
-
-static const CGEN_ISA openrisc_cgen_isa_table[] = {
- { "or32", 32, 32, 32, 32 },
- { 0, 0, 0, 0, 0 }
-};
-
-/* Machine variants. */
-
-static const CGEN_MACH openrisc_cgen_mach_table[] = {
- { "openrisc", "openrisc", MACH_OPENRISC, 0 },
- { "or1300", "openrisc:1300", MACH_OR1300, 0 },
- { 0, 0, 0, 0 }
-};
-
-static CGEN_KEYWORD_ENTRY openrisc_cgen_opval_h_gr_entries[] =
-{
- { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
- { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
- { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
- { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
- { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
- { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
- { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
- { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
- { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
- { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
- { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
- { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
- { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
- { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
- { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
- { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
- { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
- { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
- { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
- { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
- { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
- { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
- { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
- { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
- { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
- { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
- { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
- { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
- { "lr", 11, {0, {{{0, 0}}}}, 0, 0 },
- { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
- { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
-};
-
-CGEN_KEYWORD openrisc_cgen_opval_h_gr =
-{
- & openrisc_cgen_opval_h_gr_entries[0],
- 35,
- 0, 0, 0, 0, ""
-};
-
-
-/* The hardware table. */
-
-#define A(a) (1 << CGEN_HW_##a)
-
-const CGEN_HW_ENTRY openrisc_cgen_hw_table[] =
-{
- { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & openrisc_cgen_opval_h_gr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-lo16", HW_H_LO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-delay-insn", HW_H_DELAY_INSN, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
-};
-
-#undef A
-
-
-/* The instruction field table. */
-
-#define A(a) (1 << CGEN_IFLD_##a)
-
-const CGEN_IFLD openrisc_cgen_ifld_table[] =
-{
- { OPENRISC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_CLASS, "f-class", 0, 32, 31, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_SUB, "f-sub", 0, 32, 29, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_R1, "f-r1", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_R2, "f-r2", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_R3, "f-r3", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_UIMM5, "f-uimm5", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_HI16, "f-hi16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_LO16, "f-lo16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_OP1, "f-op1", 0, 32, 31, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_OP2, "f-op2", 0, 32, 29, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_OP3, "f-op3", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_OP4, "f-op4", 0, 32, 23, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_OP5, "f-op5", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_OP6, "f-op6", 0, 32, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_OP7, "f-op7", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_I16_1, "f-i16-1", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_I16_2, "f-i16-2", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_ABS26, "f-abs26", 0, 32, 25, 26, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_I16NC, "f-i16nc", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_F_15_8, "f-f-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_F_10_3, "f-f-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_F_4_1, "f-f-4-1", 0, 32, 4, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_F_7_3, "f-f-7-3", 0, 32, 7, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_F_10_7, "f-f-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
- { OPENRISC_F_F_10_11, "f-f-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
- { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
-};
-
-#undef A
-
-
-
-/* multi ifield declarations */
-
-const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [];
-
-
-/* multi ifield definitions */
-
-const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [] =
-{
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_I16_1] } },
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_I16_2] } },
- { 0, { (const PTR) 0 } }
-};
-
-/* The operand table. */
-
-#define A(a) (1 << CGEN_OPERAND_##a)
-#define OPERAND(op) OPENRISC_OPERAND_##op
-
-const CGEN_OPERAND openrisc_cgen_operand_table[] =
-{
-/* pc: program counter */
- { "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_NIL] } },
- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
-/* sr: special register */
- { "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0,
- { 0, { (const PTR) 0 } },
- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
-/* cbit: condition bit */
- { "cbit", OPENRISC_OPERAND_CBIT, HW_H_CBIT, 0, 0,
- { 0, { (const PTR) 0 } },
- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
-/* simm-16: 16 bit signed immediate */
- { "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* uimm-16: 16 bit unsigned immediate */
- { "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM16] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* disp-26: pc-rel 26 bit */
- { "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_DISP26] } },
- { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
-/* abs-26: abs 26 bit */
- { "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_ABS26] } },
- { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
-/* uimm-5: imm5 */
- { "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM5] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* rD: destination register */
- { "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R1] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* rA: source register A */
- { "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R2] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* rB: source register B */
- { "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R3] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* op-f-23: f-op23 */
- { "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP4] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* op-f-3: f-op3 */
- { "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP5] } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* hi16: high 16 bit immediate, sign optional */
- { "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } },
- { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
-/* lo16: low 16 bit immediate, sign optional */
- { "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16,
- { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_LO16] } },
- { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
-/* ui16nc: 16 bit immediate, sign optional */
- { "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16,
- { 2, { (const PTR) &OPENRISC_F_I16NC_MULTI_IFIELD[0] } },
- { 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
-/* sentinel */
- { 0, 0, 0, 0, 0,
- { 0, { (const PTR) 0 } },
- { 0, { { { (1<<MACH_BASE), 0 } } } } }
-};
-
-#undef A
-
-
-/* The instruction table. */
-
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-#define A(a) (1 << CGEN_INSN_##a)
-
-static const CGEN_IBASE openrisc_cgen_insn_table[MAX_INSNS] =
-{
- /* Special null first entry.
- A `num' value of zero is thus invalid.
- Also, the special `invalid' insn resides here. */
- { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
-/* l.j ${abs-26} */
- {
- OPENRISC_INSN_L_J, "l-j", "l.j", 32,
- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.jal ${abs-26} */
- {
- OPENRISC_INSN_L_JAL, "l-jal", "l.jal", 32,
- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.jr $rA */
- {
- OPENRISC_INSN_L_JR, "l-jr", "l.jr", 32,
- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.jalr $rA */
- {
- OPENRISC_INSN_L_JALR, "l-jalr", "l.jalr", 32,
- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.bal ${disp-26} */
- {
- OPENRISC_INSN_L_BAL, "l-bal", "l.bal", 32,
- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.bnf ${disp-26} */
- {
- OPENRISC_INSN_L_BNF, "l-bnf", "l.bnf", 32,
- { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.bf ${disp-26} */
- {
- OPENRISC_INSN_L_BF, "l-bf", "l.bf", 32,
- { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.brk ${uimm-16} */
- {
- OPENRISC_INSN_L_BRK, "l-brk", "l.brk", 32,
- { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.rfe $rA */
- {
- OPENRISC_INSN_L_RFE, "l-rfe", "l.rfe", 32,
- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sys ${uimm-16} */
- {
- OPENRISC_INSN_L_SYS, "l-sys", "l.sys", 32,
- { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.nop */
- {
- OPENRISC_INSN_L_NOP, "l-nop", "l.nop", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.movhi $rD,$hi16 */
- {
- OPENRISC_INSN_L_MOVHI, "l-movhi", "l.movhi", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.mfsr $rD,$rA */
- {
- OPENRISC_INSN_L_MFSR, "l-mfsr", "l.mfsr", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.mtsr $rA,$rB */
- {
- OPENRISC_INSN_L_MTSR, "l-mtsr", "l.mtsr", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.lw $rD,${simm-16}($rA) */
- {
- OPENRISC_INSN_L_LW, "l-lw", "l.lw", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.lbz $rD,${simm-16}($rA) */
- {
- OPENRISC_INSN_L_LBZ, "l-lbz", "l.lbz", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.lbs $rD,${simm-16}($rA) */
- {
- OPENRISC_INSN_L_LBS, "l-lbs", "l.lbs", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.lhz $rD,${simm-16}($rA) */
- {
- OPENRISC_INSN_L_LHZ, "l-lhz", "l.lhz", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.lhs $rD,${simm-16}($rA) */
- {
- OPENRISC_INSN_L_LHS, "l-lhs", "l.lhs", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sw ${ui16nc}($rA),$rB */
- {
- OPENRISC_INSN_L_SW, "l-sw", "l.sw", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sb ${ui16nc}($rA),$rB */
- {
- OPENRISC_INSN_L_SB, "l-sb", "l.sb", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sh ${ui16nc}($rA),$rB */
- {
- OPENRISC_INSN_L_SH, "l-sh", "l.sh", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sll $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_SLL, "l-sll", "l.sll", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.slli $rD,$rA,${uimm-5} */
- {
- OPENRISC_INSN_L_SLLI, "l-slli", "l.slli", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.srl $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_SRL, "l-srl", "l.srl", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.srli $rD,$rA,${uimm-5} */
- {
- OPENRISC_INSN_L_SRLI, "l-srli", "l.srli", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sra $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_SRA, "l-sra", "l.sra", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.srai $rD,$rA,${uimm-5} */
- {
- OPENRISC_INSN_L_SRAI, "l-srai", "l.srai", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.ror $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_ROR, "l-ror", "l.ror", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.rori $rD,$rA,${uimm-5} */
- {
- OPENRISC_INSN_L_RORI, "l-rori", "l.rori", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.add $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_ADD, "l-add", "l.add", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.addi $rD,$rA,$lo16 */
- {
- OPENRISC_INSN_L_ADDI, "l-addi", "l.addi", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sub $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_SUB, "l-sub", "l.sub", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.subi $rD,$rA,$lo16 */
- {
- OPENRISC_INSN_L_SUBI, "l-subi", "l.subi", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.and $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_AND, "l-and", "l.and", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.andi $rD,$rA,$lo16 */
- {
- OPENRISC_INSN_L_ANDI, "l-andi", "l.andi", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.or $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_OR, "l-or", "l.or", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.ori $rD,$rA,$lo16 */
- {
- OPENRISC_INSN_L_ORI, "l-ori", "l.ori", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.xor $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_XOR, "l-xor", "l.xor", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.xori $rD,$rA,$lo16 */
- {
- OPENRISC_INSN_L_XORI, "l-xori", "l.xori", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.mul $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_MUL, "l-mul", "l.mul", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.muli $rD,$rA,$lo16 */
- {
- OPENRISC_INSN_L_MULI, "l-muli", "l.muli", 32,
- { 0, { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.div $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_DIV, "l-div", "l.div", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.divu $rD,$rA,$rB */
- {
- OPENRISC_INSN_L_DIVU, "l-divu", "l.divu", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfgts $rA,$rB */
- {
- OPENRISC_INSN_L_SFGTS, "l-sfgts", "l.sfgts", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfgtu $rA,$rB */
- {
- OPENRISC_INSN_L_SFGTU, "l-sfgtu", "l.sfgtu", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfges $rA,$rB */
- {
- OPENRISC_INSN_L_SFGES, "l-sfges", "l.sfges", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfgeu $rA,$rB */
- {
- OPENRISC_INSN_L_SFGEU, "l-sfgeu", "l.sfgeu", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sflts $rA,$rB */
- {
- OPENRISC_INSN_L_SFLTS, "l-sflts", "l.sflts", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfltu $rA,$rB */
- {
- OPENRISC_INSN_L_SFLTU, "l-sfltu", "l.sfltu", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfles $rA,$rB */
- {
- OPENRISC_INSN_L_SFLES, "l-sfles", "l.sfles", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfleu $rA,$rB */
- {
- OPENRISC_INSN_L_SFLEU, "l-sfleu", "l.sfleu", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfgtsi $rA,${simm-16} */
- {
- OPENRISC_INSN_L_SFGTSI, "l-sfgtsi", "l.sfgtsi", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfgtui $rA,${uimm-16} */
- {
- OPENRISC_INSN_L_SFGTUI, "l-sfgtui", "l.sfgtui", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfgesi $rA,${simm-16} */
- {
- OPENRISC_INSN_L_SFGESI, "l-sfgesi", "l.sfgesi", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfgeui $rA,${uimm-16} */
- {
- OPENRISC_INSN_L_SFGEUI, "l-sfgeui", "l.sfgeui", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfltsi $rA,${simm-16} */
- {
- OPENRISC_INSN_L_SFLTSI, "l-sfltsi", "l.sfltsi", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfltui $rA,${uimm-16} */
- {
- OPENRISC_INSN_L_SFLTUI, "l-sfltui", "l.sfltui", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sflesi $rA,${simm-16} */
- {
- OPENRISC_INSN_L_SFLESI, "l-sflesi", "l.sflesi", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfleui $rA,${uimm-16} */
- {
- OPENRISC_INSN_L_SFLEUI, "l-sfleui", "l.sfleui", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfeq $rA,$rB */
- {
- OPENRISC_INSN_L_SFEQ, "l-sfeq", "l.sfeq", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfeqi $rA,${simm-16} */
- {
- OPENRISC_INSN_L_SFEQI, "l-sfeqi", "l.sfeqi", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfne $rA,$rB */
- {
- OPENRISC_INSN_L_SFNE, "l-sfne", "l.sfne", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-/* l.sfnei $rA,${simm-16} */
- {
- OPENRISC_INSN_L_SFNEI, "l-sfnei", "l.sfnei", 32,
- { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
- },
-};
-
-#undef OP
-#undef A
-
-/* Initialize anything needed to be done once, before any cpu_open call. */
-
-static void
-init_tables (void)
-{
-}
-
-static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
-static void build_hw_table (CGEN_CPU_TABLE *);
-static void build_ifield_table (CGEN_CPU_TABLE *);
-static void build_operand_table (CGEN_CPU_TABLE *);
-static void build_insn_table (CGEN_CPU_TABLE *);
-static void openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *);
-
-/* Subroutine of openrisc_cgen_cpu_open to look up a mach via its bfd name. */
-
-static const CGEN_MACH *
-lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
-{
- while (table->name)
- {
- if (strcmp (name, table->bfd_name) == 0)
- return table;
- ++table;
- }
- abort ();
-}
-
-/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */
-
-static void
-build_hw_table (CGEN_CPU_TABLE *cd)
-{
- int i;
- int machs = cd->machs;
- const CGEN_HW_ENTRY *init = & openrisc_cgen_hw_table[0];
- /* MAX_HW is only an upper bound on the number of selected entries.
- However each entry is indexed by it's enum so there can be holes in
- the table. */
- const CGEN_HW_ENTRY **selected =
- (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
-
- cd->hw_table.init_entries = init;
- cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
- memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
- /* ??? For now we just use machs to determine which ones we want. */
- for (i = 0; init[i].name != NULL; ++i)
- if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
- & machs)
- selected[init[i].type] = &init[i];
- cd->hw_table.entries = selected;
- cd->hw_table.num_entries = MAX_HW;
-}
-
-/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */
-
-static void
-build_ifield_table (CGEN_CPU_TABLE *cd)
-{
- cd->ifld_table = & openrisc_cgen_ifld_table[0];
-}
-
-/* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */
-
-static void
-build_operand_table (CGEN_CPU_TABLE *cd)
-{
- int i;
- int machs = cd->machs;
- const CGEN_OPERAND *init = & openrisc_cgen_operand_table[0];
- /* MAX_OPERANDS is only an upper bound on the number of selected entries.
- However each entry is indexed by it's enum so there can be holes in
- the table. */
- const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
-
- cd->operand_table.init_entries = init;
- cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
- memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
- /* ??? For now we just use mach to determine which ones we want. */
- for (i = 0; init[i].name != NULL; ++i)
- if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
- & machs)
- selected[init[i].type] = &init[i];
- cd->operand_table.entries = selected;
- cd->operand_table.num_entries = MAX_OPERANDS;
-}
-
-/* Subroutine of openrisc_cgen_cpu_open to build the hardware table.
- ??? This could leave out insns not supported by the specified mach/isa,
- but that would cause errors like "foo only supported by bar" to become
- "unknown insn", so for now we include all insns and require the app to
- do the checking later.
- ??? On the other hand, parsing of such insns may require their hardware or
- operand elements to be in the table [which they mightn't be]. */
-
-static void
-build_insn_table (CGEN_CPU_TABLE *cd)
-{
- int i;
- const CGEN_IBASE *ib = & openrisc_cgen_insn_table[0];
- CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
-
- memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
- for (i = 0; i < MAX_INSNS; ++i)
- insns[i].base = &ib[i];
- cd->insn_table.init_entries = insns;
- cd->insn_table.entry_size = sizeof (CGEN_IBASE);
- cd->insn_table.num_init_entries = MAX_INSNS;
-}
-
-/* Subroutine of openrisc_cgen_cpu_open to rebuild the tables. */
-
-static void
-openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
-{
- int i;
- CGEN_BITSET *isas = cd->isas;
- unsigned int machs = cd->machs;
-
- cd->int_insn_p = CGEN_INT_INSN_P;
-
- /* Data derived from the isa spec. */
-#define UNSET (CGEN_SIZE_UNKNOWN + 1)
- cd->default_insn_bitsize = UNSET;
- cd->base_insn_bitsize = UNSET;
- cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
- cd->max_insn_bitsize = 0;
- for (i = 0; i < MAX_ISAS; ++i)
- if (cgen_bitset_contains (isas, i))
- {
- const CGEN_ISA *isa = & openrisc_cgen_isa_table[i];
-
- /* Default insn sizes of all selected isas must be
- equal or we set the result to 0, meaning "unknown". */
- if (cd->default_insn_bitsize == UNSET)
- cd->default_insn_bitsize = isa->default_insn_bitsize;
- else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
- ; /* This is ok. */
- else
- cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
-
- /* Base insn sizes of all selected isas must be equal
- or we set the result to 0, meaning "unknown". */
- if (cd->base_insn_bitsize == UNSET)
- cd->base_insn_bitsize = isa->base_insn_bitsize;
- else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
- ; /* This is ok. */
- else
- cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
-
- /* Set min,max insn sizes. */
- if (isa->min_insn_bitsize < cd->min_insn_bitsize)
- cd->min_insn_bitsize = isa->min_insn_bitsize;
- if (isa->max_insn_bitsize > cd->max_insn_bitsize)
- cd->max_insn_bitsize = isa->max_insn_bitsize;
- }
-
- /* Data derived from the mach spec. */
- for (i = 0; i < MAX_MACHS; ++i)
- if (((1 << i) & machs) != 0)
- {
- const CGEN_MACH *mach = & openrisc_cgen_mach_table[i];
-
- if (mach->insn_chunk_bitsize != 0)
- {
- if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
- {
- fprintf (stderr, "openrisc_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
- cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
- abort ();
- }
-
- cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
- }
- }
-
- /* Determine which hw elements are used by MACH. */
- build_hw_table (cd);
-
- /* Build the ifield table. */
- build_ifield_table (cd);
-
- /* Determine which operands are used by MACH/ISA. */
- build_operand_table (cd);
-
- /* Build the instruction table. */
- build_insn_table (cd);
-}
-
-/* Initialize a cpu table and return a descriptor.
- It's much like opening a file, and must be the first function called.
- The arguments are a set of (type/value) pairs, terminated with
- CGEN_CPU_OPEN_END.
-
- Currently supported values:
- CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
- CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
- CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
- CGEN_CPU_OPEN_ENDIAN: specify endian choice
- CGEN_CPU_OPEN_END: terminates arguments
-
- ??? Simultaneous multiple isas might not make sense, but it's not (yet)
- precluded. */
-
-CGEN_CPU_DESC
-openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
-{
- CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
- static int init_p;
- CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
- unsigned int machs = 0; /* 0 = "unspecified" */
- enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
- va_list ap;
-
- if (! init_p)
- {
- init_tables ();
- init_p = 1;
- }
-
- memset (cd, 0, sizeof (*cd));
-
- va_start (ap, arg_type);
- while (arg_type != CGEN_CPU_OPEN_END)
- {
- switch (arg_type)
- {
- case CGEN_CPU_OPEN_ISAS :
- isas = va_arg (ap, CGEN_BITSET *);
- break;
- case CGEN_CPU_OPEN_MACHS :
- machs = va_arg (ap, unsigned int);
- break;
- case CGEN_CPU_OPEN_BFDMACH :
- {
- const char *name = va_arg (ap, const char *);
- const CGEN_MACH *mach =
- lookup_mach_via_bfd_name (openrisc_cgen_mach_table, name);
-
- machs |= 1 << mach->num;
- break;
- }
- case CGEN_CPU_OPEN_ENDIAN :
- endian = va_arg (ap, enum cgen_endian);
- break;
- default :
- fprintf (stderr, "openrisc_cgen_cpu_open: unsupported argument `%d'\n",
- arg_type);
- abort (); /* ??? return NULL? */
- }
- arg_type = va_arg (ap, enum cgen_cpu_open_arg);
- }
- va_end (ap);
-
- /* Mach unspecified means "all". */
- if (machs == 0)
- machs = (1 << MAX_MACHS) - 1;
- /* Base mach is always selected. */
- machs |= 1;
- if (endian == CGEN_ENDIAN_UNKNOWN)
- {
- /* ??? If target has only one, could have a default. */
- fprintf (stderr, "openrisc_cgen_cpu_open: no endianness specified\n");
- abort ();
- }
-
- cd->isas = cgen_bitset_copy (isas);
- cd->machs = machs;
- cd->endian = endian;
- /* FIXME: for the sparc case we can determine insn-endianness statically.
- The worry here is where both data and insn endian can be independently
- chosen, in which case this function will need another argument.
- Actually, will want to allow for more arguments in the future anyway. */
- cd->insn_endian = endian;
-
- /* Table (re)builder. */
- cd->rebuild_tables = openrisc_cgen_rebuild_tables;
- openrisc_cgen_rebuild_tables (cd);
-
- /* Default to not allowing signed overflow. */
- cd->signed_overflow_ok_p = 0;
-
- return (CGEN_CPU_DESC) cd;
-}
-
-/* Cover fn to openrisc_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
- MACH_NAME is the bfd name of the mach. */
-
-CGEN_CPU_DESC
-openrisc_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
-{
- return openrisc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
- CGEN_CPU_OPEN_ENDIAN, endian,
- CGEN_CPU_OPEN_END);
-}
-
-/* Close a cpu table.
- ??? This can live in a machine independent file, but there's currently
- no place to put this file (there's no libcgen). libopcodes is the wrong
- place as some simulator ports use this but they don't use libopcodes. */
-
-void
-openrisc_cgen_cpu_close (CGEN_CPU_DESC cd)
-{
- unsigned int i;
- const CGEN_INSN *insns;
-
- if (cd->macro_insn_table.init_entries)
- {
- insns = cd->macro_insn_table.init_entries;
- for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
- if (CGEN_INSN_RX ((insns)))
- regfree (CGEN_INSN_RX (insns));
- }
-
- if (cd->insn_table.init_entries)
- {
- insns = cd->insn_table.init_entries;
- for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
- if (CGEN_INSN_RX (insns))
- regfree (CGEN_INSN_RX (insns));
- }
-
- if (cd->macro_insn_table.init_entries)
- free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
-
- if (cd->insn_table.init_entries)
- free ((CGEN_INSN *) cd->insn_table.init_entries);
-
- if (cd->hw_table.entries)
- free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
-
- if (cd->operand_table.entries)
- free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
-
- free (cd);
-}
-
diff --git a/opcodes/openrisc-desc.h b/opcodes/openrisc-desc.h
deleted file mode 100644
index d37fa9a..0000000
--- a/opcodes/openrisc-desc.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/* CPU data header for openrisc.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2014 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#ifndef OPENRISC_CPU_H
-#define OPENRISC_CPU_H
-
-#define CGEN_ARCH openrisc
-
-/* Given symbol S, return openrisc_cgen_<S>. */
-#define CGEN_SYM(s) openrisc##_cgen_##s
-
-
-/* Selected cpu families. */
-#define HAVE_CPU_OPENRISCBF
-
-#define CGEN_INSN_LSB0_P 1
-
-/* Minimum size of any insn (in bytes). */
-#define CGEN_MIN_INSN_SIZE 4
-
-/* Maximum size of any insn (in bytes). */
-#define CGEN_MAX_INSN_SIZE 4
-
-#define CGEN_INT_INSN_P 1
-
-/* Maximum number of syntax elements in an instruction. */
-#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 14
-
-/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
- e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
- we can't hash on everything up to the space. */
-#define CGEN_MNEMONIC_OPERANDS
-
-/* Maximum number of fields in an instruction. */
-#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
-
-/* Enums. */
-
-/* Enum declaration for exception vectors. */
-typedef enum e_exception {
- E_RESET, E_BUSERR, E_DPF, E_IPF
- , E_EXTINT, E_ALIGN, E_ILLEGAL, E_PEINT
- , E_DTLBMISS, E_ITLBMISS, E_RRANGE, E_SYSCALL
- , E_BREAK, E_RESERVED
-} E_EXCEPTION;
-
-/* Enum declaration for FIXME. */
-typedef enum insn_class {
- OP1_0, OP1_1, OP1_2, OP1_3
-} INSN_CLASS;
-
-/* Enum declaration for FIXME. */
-typedef enum insn_sub {
- OP2_0, OP2_1, OP2_2, OP2_3
- , OP2_4, OP2_5, OP2_6, OP2_7
- , OP2_8, OP2_9, OP2_10, OP2_11
- , OP2_12, OP2_13, OP2_14, OP2_15
-} INSN_SUB;
-
-/* Enum declaration for FIXME. */
-typedef enum insn_op3 {
- OP3_0, OP3_1, OP3_2, OP3_3
-} INSN_OP3;
-
-/* Enum declaration for FIXME. */
-typedef enum insn_op4 {
- OP4_0, OP4_1, OP4_2, OP4_3
- , OP4_4, OP4_5, OP4_6, OP4_7
-} INSN_OP4;
-
-/* Enum declaration for FIXME. */
-typedef enum insn_op5 {
- OP5_0, OP5_1, OP5_2, OP5_3
- , OP5_4, OP5_5, OP5_6, OP5_7
- , OP5_8, OP5_9, OP5_10, OP5_11
- , OP5_12, OP5_13, OP5_14, OP5_15
- , OP5_16, OP5_17, OP5_18, OP5_19
- , OP5_20, OP5_21, OP5_22, OP5_23
- , OP5_24, OP5_25, OP5_26, OP5_27
- , OP5_28, OP5_29, OP5_30, OP5_31
-} INSN_OP5;
-
-/* Enum declaration for FIXME. */
-typedef enum insn_op6 {
- OP6_0, OP6_1, OP6_2, OP6_3
- , OP6_4, OP6_5, OP6_6, OP6_7
-} INSN_OP6;
-
-/* Enum declaration for FIXME. */
-typedef enum insn_op7 {
- OP7_0, OP7_1, OP7_2, OP7_3
- , OP7_4, OP7_5, OP7_6, OP7_7
- , OP7_8, OP7_9, OP7_10, OP7_11
- , OP7_12, OP7_13, OP7_14, OP7_15
-} INSN_OP7;
-
-/* Attributes. */
-
-/* Enum declaration for machine type selection. */
-typedef enum mach_attr {
- MACH_BASE, MACH_OPENRISC, MACH_OR1300, MACH_MAX
-} MACH_ATTR;
-
-/* Enum declaration for instruction set selection. */
-typedef enum isa_attr {
- ISA_OR32, ISA_MAX
-} ISA_ATTR;
-
-/* Enum declaration for if this model has caches. */
-typedef enum has_cache_attr {
- HAS_CACHE_DATA_CACHE, HAS_CACHE_INSN_CACHE
-} HAS_CACHE_ATTR;
-
-/* Number of architecture variants. */
-#define MAX_ISAS 1
-#define MAX_MACHS ((int) MACH_MAX)
-
-/* Ifield support. */
-
-/* Ifield attribute indices. */
-
-/* Enum declaration for cgen_ifld attrs. */
-typedef enum cgen_ifld_attr {
- CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
- , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
- , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
-} CGEN_IFLD_ATTR;
-
-/* Number of non-boolean elements in cgen_ifld_attr. */
-#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
-
-/* cgen_ifld attribute accessor macros. */
-#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
-
-/* Enum declaration for openrisc ifield types. */
-typedef enum ifield_type {
- OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB
- , OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3, OPENRISC_F_SIMM16
- , OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16, OPENRISC_F_LO16
- , OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3, OPENRISC_F_OP4
- , OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7, OPENRISC_F_I16_1
- , OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26, OPENRISC_F_I16NC
- , OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1, OPENRISC_F_F_7_3
- , OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX
-} IFIELD_TYPE;
-
-#define MAX_IFLD ((int) OPENRISC_F_MAX)
-
-/* Hardware attribute indices. */
-
-/* Enum declaration for cgen_hw attrs. */
-typedef enum cgen_hw_attr {
- CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
- , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
-} CGEN_HW_ATTR;
-
-/* Number of non-boolean elements in cgen_hw_attr. */
-#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
-
-/* cgen_hw attribute accessor macros. */
-#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
-#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
-
-/* Enum declaration for openrisc hardware types. */
-typedef enum cgen_hw_type {
- HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
- , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_SR
- , HW_H_HI16, HW_H_LO16, HW_H_CBIT, HW_H_DELAY_INSN
- , HW_MAX
-} CGEN_HW_TYPE;
-
-#define MAX_HW ((int) HW_MAX)
-
-/* Operand attribute indices. */
-
-/* Enum declaration for cgen_operand attrs. */
-typedef enum cgen_operand_attr {
- CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
- , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
- , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
-} CGEN_OPERAND_ATTR;
-
-/* Number of non-boolean elements in cgen_operand_attr. */
-#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
-
-/* cgen_operand attribute accessor macros. */
-#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
-
-/* Enum declaration for openrisc operand types. */
-typedef enum cgen_operand_type {
- OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16
- , OPENRISC_OPERAND_UIMM_16, OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5
- , OPENRISC_OPERAND_RD, OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23
- , OPENRISC_OPERAND_OP_F_3, OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC
- , OPENRISC_OPERAND_MAX
-} CGEN_OPERAND_TYPE;
-
-/* Number of operands types. */
-#define MAX_OPERANDS 16
-
-/* Maximum number of operands referenced by any insn. */
-#define MAX_OPERAND_INSTANCES 8
-
-/* Insn attribute indices. */
-
-/* Enum declaration for cgen_insn attrs. */
-typedef enum cgen_insn_attr {
- CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
- , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
- , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
- , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
-} CGEN_INSN_ATTR;
-
-/* Number of non-boolean elements in cgen_insn_attr. */
-#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
-
-/* cgen_insn attribute accessor macros. */
-#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
-#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
-#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
-#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
-#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
-#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
-#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0)
-
-/* cgen.h uses things we just defined. */
-#include "opcode/cgen.h"
-
-extern const struct cgen_ifld openrisc_cgen_ifld_table[];
-
-/* Attributes. */
-extern const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[];
-extern const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[];
-extern const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[];
-extern const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[];
-
-/* Hardware decls. */
-
-extern CGEN_KEYWORD openrisc_cgen_opval_h_gr;
-
-extern const CGEN_HW_ENTRY openrisc_cgen_hw_table[];
-
-
-
-#endif /* OPENRISC_CPU_H */
diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c
deleted file mode 100644
index 0020de9..0000000
--- a/opcodes/openrisc-dis.c
+++ /dev/null
@@ -1,555 +0,0 @@
-/* Disassembler interface for targets using CGEN. -*- C -*-
- CGEN: Cpu tools GENerator
-
- THIS FILE IS MACHINE GENERATED WITH CGEN.
- - the resultant file is machine generated, cgen-dis.in isn't
-
- Copyright (C) 1996-2014 Free Software Foundation, Inc.
-
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-/* ??? Eventually more and more of this stuff can go to cpu-independent files.
- Keep that in mind. */
-
-#include "sysdep.h"
-#include <stdio.h>
-#include "ansidecl.h"
-#include "dis-asm.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "libiberty.h"
-#include "openrisc-desc.h"
-#include "openrisc-opc.h"
-#include "opintl.h"
-
-/* Default text to print if an instruction isn't recognized. */
-#define UNKNOWN_INSN_MSG _("*unknown*")
-
-static void print_normal
- (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
-static void print_address
- (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
-static void print_keyword
- (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
-static void print_insn_normal
- (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
-static int print_insn
- (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
-static int default_print_insn
- (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
-static int read_insn
- (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
- unsigned long *);
-
-/* -- disassembler routines inserted here. */
-
-
-void openrisc_cgen_print_operand
- (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
-
-/* Main entry point for printing operands.
- XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
- of dis-asm.h on cgen.h.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `print_insn_normal', but keeping it
- separate makes clear the interface between `print_insn_normal' and each of
- the handlers. */
-
-void
-openrisc_cgen_print_operand (CGEN_CPU_DESC cd,
- int opindex,
- void * xinfo,
- CGEN_FIELDS *fields,
- void const *attrs ATTRIBUTE_UNUSED,
- bfd_vma pc,
- int length)
-{
- disassemble_info *info = (disassemble_info *) xinfo;
-
- switch (opindex)
- {
- case OPENRISC_OPERAND_ABS_26 :
- print_address (cd, info, fields->f_abs26, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
- break;
- case OPENRISC_OPERAND_DISP_26 :
- print_address (cd, info, fields->f_disp26, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
- break;
- case OPENRISC_OPERAND_HI16 :
- print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
- break;
- case OPENRISC_OPERAND_LO16 :
- print_normal (cd, info, fields->f_lo16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
- break;
- case OPENRISC_OPERAND_OP_F_23 :
- print_normal (cd, info, fields->f_op4, 0, pc, length);
- break;
- case OPENRISC_OPERAND_OP_F_3 :
- print_normal (cd, info, fields->f_op5, 0, pc, length);
- break;
- case OPENRISC_OPERAND_RA :
- print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r2, 0);
- break;
- case OPENRISC_OPERAND_RB :
- print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r3, 0);
- break;
- case OPENRISC_OPERAND_RD :
- print_keyword (cd, info, & openrisc_cgen_opval_h_gr, fields->f_r1, 0);
- break;
- case OPENRISC_OPERAND_SIMM_16 :
- print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
- break;
- case OPENRISC_OPERAND_UI16NC :
- print_normal (cd, info, fields->f_i16nc, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
- break;
- case OPENRISC_OPERAND_UIMM_16 :
- print_normal (cd, info, fields->f_uimm16, 0, pc, length);
- break;
- case OPENRISC_OPERAND_UIMM_5 :
- print_normal (cd, info, fields->f_uimm5, 0, pc, length);
- break;
-
- default :
- /* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
- opindex);
- abort ();
- }
-}
-
-cgen_print_fn * const openrisc_cgen_print_handlers[] =
-{
- print_insn_normal,
-};
-
-
-void
-openrisc_cgen_init_dis (CGEN_CPU_DESC cd)
-{
- openrisc_cgen_init_opcode_table (cd);
- openrisc_cgen_init_ibld_table (cd);
- cd->print_handlers = & openrisc_cgen_print_handlers[0];
- cd->print_operand = openrisc_cgen_print_operand;
-}
-
-
-/* Default print handler. */
-
-static void
-print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- long value,
- unsigned int attrs,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- /* Print the operand as directed by the attributes. */
- if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
- ; /* nothing to do */
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
- (*info->fprintf_func) (info->stream, "%ld", value);
- else
- (*info->fprintf_func) (info->stream, "0x%lx", value);
-}
-
-/* Default address handler. */
-
-static void
-print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- bfd_vma value,
- unsigned int attrs,
- bfd_vma pc ATTRIBUTE_UNUSED,
- int length ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
-
- /* Print the operand as directed by the attributes. */
- if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
- ; /* Nothing to do. */
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
- (*info->print_address_func) (value, info);
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
- (*info->print_address_func) (value, info);
- else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
- (*info->fprintf_func) (info->stream, "%ld", (long) value);
- else
- (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
-}
-
-/* Keyword print handler. */
-
-static void
-print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- void *dis_info,
- CGEN_KEYWORD *keyword_table,
- long value,
- unsigned int attrs ATTRIBUTE_UNUSED)
-{
- disassemble_info *info = (disassemble_info *) dis_info;
- const CGEN_KEYWORD_ENTRY *ke;
-
- ke = cgen_keyword_lookup_value (keyword_table, value);
- if (ke != NULL)
- (*info->fprintf_func) (info->stream, "%s", ke->name);
- else
- (*info->fprintf_func) (info->stream, "???");
-}
-
-/* Default insn printer.
-
- DIS_INFO is defined as `void *' so the disassembler needn't know anything
- about disassemble_info. */
-
-static void
-print_insn_normal (CGEN_CPU_DESC cd,
- void *dis_info,
- const CGEN_INSN *insn,
- CGEN_FIELDS *fields,
- bfd_vma pc,
- int length)
-{
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- disassemble_info *info = (disassemble_info *) dis_info;
- const CGEN_SYNTAX_CHAR_TYPE *syn;
-
- CGEN_INIT_PRINT (cd);
-
- for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
- {
- if (CGEN_SYNTAX_MNEMONIC_P (*syn))
- {
- (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
- continue;
- }
- if (CGEN_SYNTAX_CHAR_P (*syn))
- {
- (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
- continue;
- }
-
- /* We have an operand. */
- openrisc_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
- fields, CGEN_INSN_ATTRS (insn), pc, length);
- }
-}
-
-/* Subroutine of print_insn. Reads an insn into the given buffers and updates
- the extract info.
- Returns 0 if all is well, non-zero otherwise. */
-
-static int
-read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- bfd_vma pc,
- disassemble_info *info,
- bfd_byte *buf,
- int buflen,
- CGEN_EXTRACT_INFO *ex_info,
- unsigned long *insn_value)
-{
- int status = (*info->read_memory_func) (pc, buf, buflen, info);
-
- if (status != 0)
- {
- (*info->memory_error_func) (status, pc, info);
- return -1;
- }
-
- ex_info->dis_info = info;
- ex_info->valid = (1 << buflen) - 1;
- ex_info->insn_bytes = buf;
-
- *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
- return 0;
-}
-
-/* Utility to print an insn.
- BUF is the base part of the insn, target byte order, BUFLEN bytes long.
- The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occurs fetching data (memory_error_func will have
- been called). */
-
-static int
-print_insn (CGEN_CPU_DESC cd,
- bfd_vma pc,
- disassemble_info *info,
- bfd_byte *buf,
- unsigned int buflen)
-{
- CGEN_INSN_INT insn_value;
- const CGEN_INSN_LIST *insn_list;
- CGEN_EXTRACT_INFO ex_info;
- int basesize;
-
- /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
- basesize = cd->base_insn_bitsize < buflen * 8 ?
- cd->base_insn_bitsize : buflen * 8;
- insn_value = cgen_get_insn_value (cd, buf, basesize);
-
-
- /* Fill in ex_info fields like read_insn would. Don't actually call
- read_insn, since the incoming buffer is already read (and possibly
- modified a la m32r). */
- ex_info.valid = (1 << buflen) - 1;
- ex_info.dis_info = info;
- ex_info.insn_bytes = buf;
-
- /* The instructions are stored in hash lists.
- Pick the first one and keep trying until we find the right one. */
-
- insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
- while (insn_list != NULL)
- {
- const CGEN_INSN *insn = insn_list->insn;
- CGEN_FIELDS fields;
- int length;
- unsigned long insn_value_cropped;
-
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
- /* Not needed as insn shouldn't be in hash lists if not supported. */
- /* Supported by this cpu? */
- if (! openrisc_cgen_insn_supported (cd, insn))
- {
- insn_list = CGEN_DIS_NEXT_INSN (insn_list);
- continue;
- }
-#endif
-
- /* Basic bit mask must be correct. */
- /* ??? May wish to allow target to defer this check until the extract
- handler. */
-
- /* Base size may exceed this instruction's size. Extract the
- relevant part from the buffer. */
- if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
- (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
- info->endian == BFD_ENDIAN_BIG);
- else
- insn_value_cropped = insn_value;
-
- if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
- == CGEN_INSN_BASE_VALUE (insn))
- {
- /* Printing is handled in two passes. The first pass parses the
- machine insn and extracts the fields. The second pass prints
- them. */
-
- /* Make sure the entire insn is loaded into insn_value, if it
- can fit. */
- if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
- (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- {
- unsigned long full_insn_value;
- int rc = read_insn (cd, pc, info, buf,
- CGEN_INSN_BITSIZE (insn) / 8,
- & ex_info, & full_insn_value);
- if (rc != 0)
- return rc;
- length = CGEN_EXTRACT_FN (cd, insn)
- (cd, insn, &ex_info, full_insn_value, &fields, pc);
- }
- else
- length = CGEN_EXTRACT_FN (cd, insn)
- (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
-
- /* Length < 0 -> error. */
- if (length < 0)
- return length;
- if (length > 0)
- {
- CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
- /* Length is in bits, result is in bytes. */
- return length / 8;
- }
- }
-
- insn_list = CGEN_DIS_NEXT_INSN (insn_list);
- }
-
- return 0;
-}
-
-/* Default value for CGEN_PRINT_INSN.
- The result is the size of the insn in bytes or zero for an unknown insn
- or -1 if an error occured fetching bytes. */
-
-#ifndef CGEN_PRINT_INSN
-#define CGEN_PRINT_INSN default_print_insn
-#endif
-
-static int
-default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
-{
- bfd_byte buf[CGEN_MAX_INSN_SIZE];
- int buflen;
- int status;
-
- /* Attempt to read the base part of the insn. */
- buflen = cd->base_insn_bitsize / 8;
- status = (*info->read_memory_func) (pc, buf, buflen, info);
-
- /* Try again with the minimum part, if min < base. */
- if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
- {
- buflen = cd->min_insn_bitsize / 8;
- status = (*info->read_memory_func) (pc, buf, buflen, info);
- }
-
- if (status != 0)
- {
- (*info->memory_error_func) (status, pc, info);
- return -1;
- }
-
- return print_insn (cd, pc, info, buf, buflen);
-}
-
-/* Main entry point.
- Print one instruction from PC on INFO->STREAM.
- Return the size of the instruction (in bytes). */
-
-typedef struct cpu_desc_list
-{
- struct cpu_desc_list *next;
- CGEN_BITSET *isa;
- int mach;
- int endian;
- CGEN_CPU_DESC cd;
-} cpu_desc_list;
-
-int
-print_insn_openrisc (bfd_vma pc, disassemble_info *info)
-{
- static cpu_desc_list *cd_list = 0;
- cpu_desc_list *cl = 0;
- static CGEN_CPU_DESC cd = 0;
- static CGEN_BITSET *prev_isa;
- static int prev_mach;
- static int prev_endian;
- int length;
- CGEN_BITSET *isa;
- int mach;
- int endian = (info->endian == BFD_ENDIAN_BIG
- ? CGEN_ENDIAN_BIG
- : CGEN_ENDIAN_LITTLE);
- enum bfd_architecture arch;
-
- /* ??? gdb will set mach but leave the architecture as "unknown" */
-#ifndef CGEN_BFD_ARCH
-#define CGEN_BFD_ARCH bfd_arch_openrisc
-#endif
- arch = info->arch;
- if (arch == bfd_arch_unknown)
- arch = CGEN_BFD_ARCH;
-
- /* There's no standard way to compute the machine or isa number
- so we leave it to the target. */
-#ifdef CGEN_COMPUTE_MACH
- mach = CGEN_COMPUTE_MACH (info);
-#else
- mach = info->mach;
-#endif
-
-#ifdef CGEN_COMPUTE_ISA
- {
- static CGEN_BITSET *permanent_isa;
-
- if (!permanent_isa)
- permanent_isa = cgen_bitset_create (MAX_ISAS);
- isa = permanent_isa;
- cgen_bitset_clear (isa);
- cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
- }
-#else
- isa = info->insn_sets;
-#endif
-
- /* If we've switched cpu's, try to find a handle we've used before */
- if (cd
- && (cgen_bitset_compare (isa, prev_isa) != 0
- || mach != prev_mach
- || endian != prev_endian))
- {
- cd = 0;
- for (cl = cd_list; cl; cl = cl->next)
- {
- if (cgen_bitset_compare (cl->isa, isa) == 0 &&
- cl->mach == mach &&
- cl->endian == endian)
- {
- cd = cl->cd;
- prev_isa = cd->isas;
- break;
- }
- }
- }
-
- /* If we haven't initialized yet, initialize the opcode table. */
- if (! cd)
- {
- const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
- const char *mach_name;
-
- if (!arch_type)
- abort ();
- mach_name = arch_type->printable_name;
-
- prev_isa = cgen_bitset_copy (isa);
- prev_mach = mach;
- prev_endian = endian;
- cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
- CGEN_CPU_OPEN_BFDMACH, mach_name,
- CGEN_CPU_OPEN_ENDIAN, prev_endian,
- CGEN_CPU_OPEN_END);
- if (!cd)
- abort ();
-
- /* Save this away for future reference. */
- cl = xmalloc (sizeof (struct cpu_desc_list));
- cl->cd = cd;
- cl->isa = prev_isa;
- cl->mach = mach;
- cl->endian = endian;
- cl->next = cd_list;
- cd_list = cl;
-
- openrisc_cgen_init_dis (cd);
- }
-
- /* We try to have as much common code as possible.
- But at this point some targets need to take over. */
- /* ??? Some targets may need a hook elsewhere. Try to avoid this,
- but if not possible try to move this hook elsewhere rather than
- have two hooks. */
- length = CGEN_PRINT_INSN (cd, pc, info);
- if (length > 0)
- return length;
- if (length < 0)
- return -1;
-
- (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
- return cd->default_insn_bitsize / 8;
-}
diff --git a/opcodes/openrisc-ibld.c b/opcodes/openrisc-ibld.c
deleted file mode 100644
index 554f433..0000000
--- a/opcodes/openrisc-ibld.c
+++ /dev/null
@@ -1,1008 +0,0 @@
-/* Instruction building/extraction support for openrisc. -*- C -*-
-
- THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- - the resultant file is machine generated, cgen-ibld.in isn't
-
- Copyright (C) 1996-2014 Free Software Foundation, Inc.
-
- This file is part of libopcodes.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-/* ??? Eventually more and more of this stuff can go to cpu-independent files.
- Keep that in mind. */
-
-#include "sysdep.h"
-#include <stdio.h>
-#include "ansidecl.h"
-#include "dis-asm.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "openrisc-desc.h"
-#include "openrisc-opc.h"
-#include "cgen/basic-modes.h"
-#include "opintl.h"
-#include "safe-ctype.h"
-
-#undef min
-#define min(a,b) ((a) < (b) ? (a) : (b))
-#undef max
-#define max(a,b) ((a) > (b) ? (a) : (b))
-
-/* Used by the ifield rtx function. */
-#define FLD(f) (fields->f)
-
-static const char * insert_normal
- (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
- unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
-static const char * insert_insn_normal
- (CGEN_CPU_DESC, const CGEN_INSN *,
- CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
-static int extract_normal
- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
- unsigned int, unsigned int, unsigned int, unsigned int,
- unsigned int, unsigned int, bfd_vma, long *);
-static int extract_insn_normal
- (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
- CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
-#if CGEN_INT_INSN_P
-static void put_insn_int_value
- (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
-#endif
-#if ! CGEN_INT_INSN_P
-static CGEN_INLINE void insert_1
- (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
-static CGEN_INLINE int fill_cache
- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
-static CGEN_INLINE long extract_1
- (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
-#endif
-
-/* Operand insertion. */
-
-#if ! CGEN_INT_INSN_P
-
-/* Subroutine of insert_normal. */
-
-static CGEN_INLINE void
-insert_1 (CGEN_CPU_DESC cd,
- unsigned long value,
- int start,
- int length,
- int word_length,
- unsigned char *bufp)
-{
- unsigned long x,mask;
- int shift;
-
- x = cgen_get_insn_value (cd, bufp, word_length);
-
- /* Written this way to avoid undefined behaviour. */
- mask = (((1L << (length - 1)) - 1) << 1) | 1;
- if (CGEN_INSN_LSB0_P)
- shift = (start + 1) - length;
- else
- shift = (word_length - (start + length));
- x = (x & ~(mask << shift)) | ((value & mask) << shift);
-
- cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
-}
-
-#endif /* ! CGEN_INT_INSN_P */
-
-/* Default insertion routine.
-
- ATTRS is a mask of the boolean attributes.
- WORD_OFFSET is the offset in bits from the start of the insn of the value.
- WORD_LENGTH is the length of the word in bits in which the value resides.
- START is the starting bit number in the word, architecture origin.
- LENGTH is the length of VALUE in bits.
- TOTAL_LENGTH is the total length of the insn in bits.
-
- The result is an error message or NULL if success. */
-
-/* ??? This duplicates functionality with bfd's howto table and
- bfd_install_relocation. */
-/* ??? This doesn't handle bfd_vma's. Create another function when
- necessary. */
-
-static const char *
-insert_normal (CGEN_CPU_DESC cd,
- long value,
- unsigned int attrs,
- unsigned int word_offset,
- unsigned int start,
- unsigned int length,
- unsigned int word_length,
- unsigned int total_length,
- CGEN_INSN_BYTES_PTR buffer)
-{
- static char errbuf[100];
- /* Written this way to avoid undefined behaviour. */
- unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
-
- /* If LENGTH is zero, this operand doesn't contribute to the value. */
- if (length == 0)
- return NULL;
-
- if (word_length > 8 * sizeof (CGEN_INSN_INT))
- abort ();
-
- /* For architectures with insns smaller than the base-insn-bitsize,
- word_length may be too big. */
- if (cd->min_insn_bitsize < cd->base_insn_bitsize)
- {
- if (word_offset == 0
- && word_length > total_length)
- word_length = total_length;
- }
-
- /* Ensure VALUE will fit. */
- if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
- {
- long minval = - (1L << (length - 1));
- unsigned long maxval = mask;
-
- if ((value > 0 && (unsigned long) value > maxval)
- || value < minval)
- {
- /* xgettext:c-format */
- sprintf (errbuf,
- _("operand out of range (%ld not between %ld and %lu)"),
- value, minval, maxval);
- return errbuf;
- }
- }
- else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
- {
- unsigned long maxval = mask;
- unsigned long val = (unsigned long) value;
-
- /* For hosts with a word size > 32 check to see if value has been sign
- extended beyond 32 bits. If so then ignore these higher sign bits
- as the user is attempting to store a 32-bit signed value into an
- unsigned 32-bit field which is allowed. */
- if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
- val &= 0xFFFFFFFF;
-
- if (val > maxval)
- {
- /* xgettext:c-format */
- sprintf (errbuf,
- _("operand out of range (0x%lx not between 0 and 0x%lx)"),
- val, maxval);
- return errbuf;
- }
- }
- else
- {
- if (! cgen_signed_overflow_ok_p (cd))
- {
- long minval = - (1L << (length - 1));
- long maxval = (1L << (length - 1)) - 1;
-
- if (value < minval || value > maxval)
- {
- sprintf
- /* xgettext:c-format */
- (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
- value, minval, maxval);
- return errbuf;
- }
- }
- }
-
-#if CGEN_INT_INSN_P
-
- {
- int shift;
-
- if (CGEN_INSN_LSB0_P)
- shift = (word_offset + start + 1) - length;
- else
- shift = total_length - (word_offset + start + length);
- *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
- }
-
-#else /* ! CGEN_INT_INSN_P */
-
- {
- unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
-
- insert_1 (cd, value, start, length, word_length, bufp);
- }
-
-#endif /* ! CGEN_INT_INSN_P */
-
- return NULL;
-}
-
-/* Default insn builder (insert handler).
- The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
- that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
- recorded in host byte order, otherwise BUFFER is an array of bytes
- and the value is recorded in target byte order).
- The result is an error message or NULL if success. */
-
-static const char *
-insert_insn_normal (CGEN_CPU_DESC cd,
- const CGEN_INSN * insn,
- CGEN_FIELDS * fields,
- CGEN_INSN_BYTES_PTR buffer,
- bfd_vma pc)
-{
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- unsigned long value;
- const CGEN_SYNTAX_CHAR_TYPE * syn;
-
- CGEN_INIT_INSERT (cd);
- value = CGEN_INSN_BASE_VALUE (insn);
-
- /* If we're recording insns as numbers (rather than a string of bytes),
- target byte order handling is deferred until later. */
-
-#if CGEN_INT_INSN_P
-
- put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
- CGEN_FIELDS_BITSIZE (fields), value);
-
-#else
-
- cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
- (unsigned) CGEN_FIELDS_BITSIZE (fields)),
- value);
-
-#endif /* ! CGEN_INT_INSN_P */
-
- /* ??? It would be better to scan the format's fields.
- Still need to be able to insert a value based on the operand though;
- e.g. storing a branch displacement that got resolved later.
- Needs more thought first. */
-
- for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
- {
- const char *errmsg;
-
- if (CGEN_SYNTAX_CHAR_P (* syn))
- continue;
-
- errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
- fields, buffer, pc);
- if (errmsg)
- return errmsg;
- }
-
- return NULL;
-}
-
-#if CGEN_INT_INSN_P
-/* Cover function to store an insn value into an integral insn. Must go here
- because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
-
-static void
-put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- CGEN_INSN_BYTES_PTR buf,
- int length,
- int insn_length,
- CGEN_INSN_INT value)
-{
- /* For architectures with insns smaller than the base-insn-bitsize,
- length may be too big. */
- if (length > insn_length)
- *buf = value;
- else
- {
- int shift = insn_length - length;
- /* Written this way to avoid undefined behaviour. */
- CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
-
- *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
- }
-}
-#endif
-
-/* Operand extraction. */
-
-#if ! CGEN_INT_INSN_P
-
-/* Subroutine of extract_normal.
- Ensure sufficient bytes are cached in EX_INFO.
- OFFSET is the offset in bytes from the start of the insn of the value.
- BYTES is the length of the needed value.
- Returns 1 for success, 0 for failure. */
-
-static CGEN_INLINE int
-fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- CGEN_EXTRACT_INFO *ex_info,
- int offset,
- int bytes,
- bfd_vma pc)
-{
- /* It's doubtful that the middle part has already been fetched so
- we don't optimize that case. kiss. */
- unsigned int mask;
- disassemble_info *info = (disassemble_info *) ex_info->dis_info;
-
- /* First do a quick check. */
- mask = (1 << bytes) - 1;
- if (((ex_info->valid >> offset) & mask) == mask)
- return 1;
-
- /* Search for the first byte we need to read. */
- for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
- if (! (mask & ex_info->valid))
- break;
-
- if (bytes)
- {
- int status;
-
- pc += offset;
- status = (*info->read_memory_func)
- (pc, ex_info->insn_bytes + offset, bytes, info);
-
- if (status != 0)
- {
- (*info->memory_error_func) (status, pc, info);
- return 0;
- }
-
- ex_info->valid |= ((1 << bytes) - 1) << offset;
- }
-
- return 1;
-}
-
-/* Subroutine of extract_normal. */
-
-static CGEN_INLINE long
-extract_1 (CGEN_CPU_DESC cd,
- CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
- int start,
- int length,
- int word_length,
- unsigned char *bufp,
- bfd_vma pc ATTRIBUTE_UNUSED)
-{
- unsigned long x;
- int shift;
-
- x = cgen_get_insn_value (cd, bufp, word_length);
-
- if (CGEN_INSN_LSB0_P)
- shift = (start + 1) - length;
- else
- shift = (word_length - (start + length));
- return x >> shift;
-}
-
-#endif /* ! CGEN_INT_INSN_P */
-
-/* Default extraction routine.
-
- INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
- or sometimes less for cases like the m32r where the base insn size is 32
- but some insns are 16 bits.
- ATTRS is a mask of the boolean attributes. We only need `SIGNED',
- but for generality we take a bitmask of all of them.
- WORD_OFFSET is the offset in bits from the start of the insn of the value.
- WORD_LENGTH is the length of the word in bits in which the value resides.
- START is the starting bit number in the word, architecture origin.
- LENGTH is the length of VALUE in bits.
- TOTAL_LENGTH is the total length of the insn in bits.
-
- Returns 1 for success, 0 for failure. */
-
-/* ??? The return code isn't properly used. wip. */
-
-/* ??? This doesn't handle bfd_vma's. Create another function when
- necessary. */
-
-static int
-extract_normal (CGEN_CPU_DESC cd,
-#if ! CGEN_INT_INSN_P
- CGEN_EXTRACT_INFO *ex_info,
-#else
- CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
-#endif
- CGEN_INSN_INT insn_value,
- unsigned int attrs,
- unsigned int word_offset,
- unsigned int start,
- unsigned int length,
- unsigned int word_length,
- unsigned int total_length,
-#if ! CGEN_INT_INSN_P
- bfd_vma pc,
-#else
- bfd_vma pc ATTRIBUTE_UNUSED,
-#endif
- long *valuep)
-{
- long value, mask;
-
- /* If LENGTH is zero, this operand doesn't contribute to the value
- so give it a standard value of zero. */
- if (length == 0)
- {
- *valuep = 0;
- return 1;
- }
-
- if (word_length > 8 * sizeof (CGEN_INSN_INT))
- abort ();
-
- /* For architectures with insns smaller than the insn-base-bitsize,
- word_length may be too big. */
- if (cd->min_insn_bitsize < cd->base_insn_bitsize)
- {
- if (word_offset + word_length > total_length)
- word_length = total_length - word_offset;
- }
-
- /* Does the value reside in INSN_VALUE, and at the right alignment? */
-
- if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
- {
- if (CGEN_INSN_LSB0_P)
- value = insn_value >> ((word_offset + start + 1) - length);
- else
- value = insn_value >> (total_length - ( word_offset + start + length));
- }
-
-#if ! CGEN_INT_INSN_P
-
- else
- {
- unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
-
- if (word_length > 8 * sizeof (CGEN_INSN_INT))
- abort ();
-
- if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
- return 0;
-
- value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
- }
-
-#endif /* ! CGEN_INT_INSN_P */
-
- /* Written this way to avoid undefined behaviour. */
- mask = (((1L << (length - 1)) - 1) << 1) | 1;
-
- value &= mask;
- /* sign extend? */
- if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
- && (value & (1L << (length - 1))))
- value |= ~mask;
-
- *valuep = value;
-
- return 1;
-}
-
-/* Default insn extractor.
-
- INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
- The extracted fields are stored in FIELDS.
- EX_INFO is used to handle reading variable length insns.
- Return the length of the insn in bits, or 0 if no match,
- or -1 if an error occurs fetching data (memory_error_func will have
- been called). */
-
-static int
-extract_insn_normal (CGEN_CPU_DESC cd,
- const CGEN_INSN *insn,
- CGEN_EXTRACT_INFO *ex_info,
- CGEN_INSN_INT insn_value,
- CGEN_FIELDS *fields,
- bfd_vma pc)
-{
- const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
- const CGEN_SYNTAX_CHAR_TYPE *syn;
-
- CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
-
- CGEN_INIT_EXTRACT (cd);
-
- for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
- {
- int length;
-
- if (CGEN_SYNTAX_CHAR_P (*syn))
- continue;
-
- length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
- ex_info, insn_value, fields, pc);
- if (length <= 0)
- return length;
- }
-
- /* We recognized and successfully extracted this insn. */
- return CGEN_INSN_BITSIZE (insn);
-}
-
-/* Machine generated code added here. */
-
-const char * openrisc_cgen_insert_operand
- (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
-
-/* Main entry point for operand insertion.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `parse_insn_normal', but keeping it
- separate makes clear the interface between `parse_insn_normal' and each of
- the handlers. It's also needed by GAS to insert operands that couldn't be
- resolved during parsing. */
-
-const char *
-openrisc_cgen_insert_operand (CGEN_CPU_DESC cd,
- int opindex,
- CGEN_FIELDS * fields,
- CGEN_INSN_BYTES_PTR buffer,
- bfd_vma pc ATTRIBUTE_UNUSED)
-{
- const char * errmsg = NULL;
- unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
-
- switch (opindex)
- {
- case OPENRISC_OPERAND_ABS_26 :
- {
- long value = fields->f_abs26;
- value = ((SI) (pc) >> (2));
- errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 25, 26, 32, total_length, buffer);
- }
- break;
- case OPENRISC_OPERAND_DISP_26 :
- {
- long value = fields->f_disp26;
- value = ((SI) (((value) - (pc))) >> (2));
- errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer);
- }
- break;
- case OPENRISC_OPERAND_HI16 :
- errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
- break;
- case OPENRISC_OPERAND_LO16 :
- errmsg = insert_normal (cd, fields->f_lo16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
- break;
- case OPENRISC_OPERAND_OP_F_23 :
- errmsg = insert_normal (cd, fields->f_op4, 0, 0, 23, 3, 32, total_length, buffer);
- break;
- case OPENRISC_OPERAND_OP_F_3 :
- errmsg = insert_normal (cd, fields->f_op5, 0, 0, 25, 5, 32, total_length, buffer);
- break;
- case OPENRISC_OPERAND_RA :
- errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer);
- break;
- case OPENRISC_OPERAND_RB :
- errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer);
- break;
- case OPENRISC_OPERAND_RD :
- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer);
- break;
- case OPENRISC_OPERAND_SIMM_16 :
- errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, buffer);
- break;
- case OPENRISC_OPERAND_UI16NC :
- {
-{
- FLD (f_i16_2) = ((((HI) (FLD (f_i16nc)) >> (11))) & (31));
- FLD (f_i16_1) = ((FLD (f_i16nc)) & (2047));
-}
- errmsg = insert_normal (cd, fields->f_i16_1, 0, 0, 10, 11, 32, total_length, buffer);
- if (errmsg)
- break;
- errmsg = insert_normal (cd, fields->f_i16_2, 0, 0, 25, 5, 32, total_length, buffer);
- if (errmsg)
- break;
- }
- break;
- case OPENRISC_OPERAND_UIMM_16 :
- errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer);
- break;
- case OPENRISC_OPERAND_UIMM_5 :
- errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 4, 5, 32, total_length, buffer);
- break;
-
- default :
- /* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
- opindex);
- abort ();
- }
-
- return errmsg;
-}
-
-int openrisc_cgen_extract_operand
- (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
-
-/* Main entry point for operand extraction.
- The result is <= 0 for error, >0 for success.
- ??? Actual values aren't well defined right now.
-
- This function is basically just a big switch statement. Earlier versions
- used tables to look up the function to use, but
- - if the table contains both assembler and disassembler functions then
- the disassembler contains much of the assembler and vice-versa,
- - there's a lot of inlining possibilities as things grow,
- - using a switch statement avoids the function call overhead.
-
- This function could be moved into `print_insn_normal', but keeping it
- separate makes clear the interface between `print_insn_normal' and each of
- the handlers. */
-
-int
-openrisc_cgen_extract_operand (CGEN_CPU_DESC cd,
- int opindex,
- CGEN_EXTRACT_INFO *ex_info,
- CGEN_INSN_INT insn_value,
- CGEN_FIELDS * fields,
- bfd_vma pc)
-{
- /* Assume success (for those operands that are nops). */
- int length = 1;
- unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
-
- switch (opindex)
- {
- case OPENRISC_OPERAND_ABS_26 :
- {
- long value;
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 25, 26, 32, total_length, pc, & value);
- value = ((value) << (2));
- fields->f_abs26 = value;
- }
- break;
- case OPENRISC_OPERAND_DISP_26 :
- {
- long value;
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value);
- value = ((((value) << (2))) + (pc));
- fields->f_disp26 = value;
- }
- break;
- case OPENRISC_OPERAND_HI16 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_simm16);
- break;
- case OPENRISC_OPERAND_LO16 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_lo16);
- break;
- case OPENRISC_OPERAND_OP_F_23 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 3, 32, total_length, pc, & fields->f_op4);
- break;
- case OPENRISC_OPERAND_OP_F_3 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_op5);
- break;
- case OPENRISC_OPERAND_RA :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2);
- break;
- case OPENRISC_OPERAND_RB :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3);
- break;
- case OPENRISC_OPERAND_RD :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1);
- break;
- case OPENRISC_OPERAND_SIMM_16 :
- length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 15, 16, 32, total_length, pc, & fields->f_simm16);
- break;
- case OPENRISC_OPERAND_UI16NC :
- {
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_i16_1);
- if (length <= 0) break;
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2);
- if (length <= 0) break;
-{
- FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1))));
-}
- }
- break;
- case OPENRISC_OPERAND_UIMM_16 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16);
- break;
- case OPENRISC_OPERAND_UIMM_5 :
- length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_uimm5);
- break;
-
- default :
- /* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
- opindex);
- abort ();
- }
-
- return length;
-}
-
-cgen_insert_fn * const openrisc_cgen_insert_handlers[] =
-{
- insert_insn_normal,
-};
-
-cgen_extract_fn * const openrisc_cgen_extract_handlers[] =
-{
- extract_insn_normal,
-};
-
-int openrisc_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
-bfd_vma openrisc_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
-
-/* Getting values from cgen_fields is handled by a collection of functions.
- They are distinguished by the type of the VALUE argument they return.
- TODO: floating point, inlining support, remove cases where result type
- not appropriate. */
-
-int
-openrisc_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- const CGEN_FIELDS * fields)
-{
- int value;
-
- switch (opindex)
- {
- case OPENRISC_OPERAND_ABS_26 :
- value = fields->f_abs26;
- break;
- case OPENRISC_OPERAND_DISP_26 :
- value = fields->f_disp26;
- break;
- case OPENRISC_OPERAND_HI16 :
- value = fields->f_simm16;
- break;
- case OPENRISC_OPERAND_LO16 :
- value = fields->f_lo16;
- break;
- case OPENRISC_OPERAND_OP_F_23 :
- value = fields->f_op4;
- break;
- case OPENRISC_OPERAND_OP_F_3 :
- value = fields->f_op5;
- break;
- case OPENRISC_OPERAND_RA :
- value = fields->f_r2;
- break;
- case OPENRISC_OPERAND_RB :
- value = fields->f_r3;
- break;
- case OPENRISC_OPERAND_RD :
- value = fields->f_r1;
- break;
- case OPENRISC_OPERAND_SIMM_16 :
- value = fields->f_simm16;
- break;
- case OPENRISC_OPERAND_UI16NC :
- value = fields->f_i16nc;
- break;
- case OPENRISC_OPERAND_UIMM_16 :
- value = fields->f_uimm16;
- break;
- case OPENRISC_OPERAND_UIMM_5 :
- value = fields->f_uimm5;
- break;
-
- default :
- /* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
- opindex);
- abort ();
- }
-
- return value;
-}
-
-bfd_vma
-openrisc_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- const CGEN_FIELDS * fields)
-{
- bfd_vma value;
-
- switch (opindex)
- {
- case OPENRISC_OPERAND_ABS_26 :
- value = fields->f_abs26;
- break;
- case OPENRISC_OPERAND_DISP_26 :
- value = fields->f_disp26;
- break;
- case OPENRISC_OPERAND_HI16 :
- value = fields->f_simm16;
- break;
- case OPENRISC_OPERAND_LO16 :
- value = fields->f_lo16;
- break;
- case OPENRISC_OPERAND_OP_F_23 :
- value = fields->f_op4;
- break;
- case OPENRISC_OPERAND_OP_F_3 :
- value = fields->f_op5;
- break;
- case OPENRISC_OPERAND_RA :
- value = fields->f_r2;
- break;
- case OPENRISC_OPERAND_RB :
- value = fields->f_r3;
- break;
- case OPENRISC_OPERAND_RD :
- value = fields->f_r1;
- break;
- case OPENRISC_OPERAND_SIMM_16 :
- value = fields->f_simm16;
- break;
- case OPENRISC_OPERAND_UI16NC :
- value = fields->f_i16nc;
- break;
- case OPENRISC_OPERAND_UIMM_16 :
- value = fields->f_uimm16;
- break;
- case OPENRISC_OPERAND_UIMM_5 :
- value = fields->f_uimm5;
- break;
-
- default :
- /* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
- opindex);
- abort ();
- }
-
- return value;
-}
-
-void openrisc_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
-void openrisc_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
-
-/* Stuffing values in cgen_fields is handled by a collection of functions.
- They are distinguished by the type of the VALUE argument they accept.
- TODO: floating point, inlining support, remove cases where argument type
- not appropriate. */
-
-void
-openrisc_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- CGEN_FIELDS * fields,
- int value)
-{
- switch (opindex)
- {
- case OPENRISC_OPERAND_ABS_26 :
- fields->f_abs26 = value;
- break;
- case OPENRISC_OPERAND_DISP_26 :
- fields->f_disp26 = value;
- break;
- case OPENRISC_OPERAND_HI16 :
- fields->f_simm16 = value;
- break;
- case OPENRISC_OPERAND_LO16 :
- fields->f_lo16 = value;
- break;
- case OPENRISC_OPERAND_OP_F_23 :
- fields->f_op4 = value;
- break;
- case OPENRISC_OPERAND_OP_F_3 :
- fields->f_op5 = value;
- break;
- case OPENRISC_OPERAND_RA :
- fields->f_r2 = value;
- break;
- case OPENRISC_OPERAND_RB :
- fields->f_r3 = value;
- break;
- case OPENRISC_OPERAND_RD :
- fields->f_r1 = value;
- break;
- case OPENRISC_OPERAND_SIMM_16 :
- fields->f_simm16 = value;
- break;
- case OPENRISC_OPERAND_UI16NC :
- fields->f_i16nc = value;
- break;
- case OPENRISC_OPERAND_UIMM_16 :
- fields->f_uimm16 = value;
- break;
- case OPENRISC_OPERAND_UIMM_5 :
- fields->f_uimm5 = value;
- break;
-
- default :
- /* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
- opindex);
- abort ();
- }
-}
-
-void
-openrisc_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
- int opindex,
- CGEN_FIELDS * fields,
- bfd_vma value)
-{
- switch (opindex)
- {
- case OPENRISC_OPERAND_ABS_26 :
- fields->f_abs26 = value;
- break;
- case OPENRISC_OPERAND_DISP_26 :
- fields->f_disp26 = value;
- break;
- case OPENRISC_OPERAND_HI16 :
- fields->f_simm16 = value;
- break;
- case OPENRISC_OPERAND_LO16 :
- fields->f_lo16 = value;
- break;
- case OPENRISC_OPERAND_OP_F_23 :
- fields->f_op4 = value;
- break;
- case OPENRISC_OPERAND_OP_F_3 :
- fields->f_op5 = value;
- break;
- case OPENRISC_OPERAND_RA :
- fields->f_r2 = value;
- break;
- case OPENRISC_OPERAND_RB :
- fields->f_r3 = value;
- break;
- case OPENRISC_OPERAND_RD :
- fields->f_r1 = value;
- break;
- case OPENRISC_OPERAND_SIMM_16 :
- fields->f_simm16 = value;
- break;
- case OPENRISC_OPERAND_UI16NC :
- fields->f_i16nc = value;
- break;
- case OPENRISC_OPERAND_UIMM_16 :
- fields->f_uimm16 = value;
- break;
- case OPENRISC_OPERAND_UIMM_5 :
- fields->f_uimm5 = value;
- break;
-
- default :
- /* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
- opindex);
- abort ();
- }
-}
-
-/* Function to call before using the instruction builder tables. */
-
-void
-openrisc_cgen_init_ibld_table (CGEN_CPU_DESC cd)
-{
- cd->insert_handlers = & openrisc_cgen_insert_handlers[0];
- cd->extract_handlers = & openrisc_cgen_extract_handlers[0];
-
- cd->insert_operand = openrisc_cgen_insert_operand;
- cd->extract_operand = openrisc_cgen_extract_operand;
-
- cd->get_int_operand = openrisc_cgen_get_int_operand;
- cd->set_int_operand = openrisc_cgen_set_int_operand;
- cd->get_vma_operand = openrisc_cgen_get_vma_operand;
- cd->set_vma_operand = openrisc_cgen_set_vma_operand;
-}
diff --git a/opcodes/openrisc-opc.c b/opcodes/openrisc-opc.c
deleted file mode 100644
index dd8bc0a..0000000
--- a/opcodes/openrisc-opc.c
+++ /dev/null
@@ -1,682 +0,0 @@
-/* Instruction opcode table for openrisc.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2014 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#include "sysdep.h"
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "openrisc-desc.h"
-#include "openrisc-opc.h"
-#include "libiberty.h"
-
-/* -- opc.c */
-/* -- */
-/* The hash functions are recorded here to help keep assembler code out of
- the disassembler and vice versa. */
-
-static int asm_hash_insn_p (const CGEN_INSN *);
-static unsigned int asm_hash_insn (const char *);
-static int dis_hash_insn_p (const CGEN_INSN *);
-static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
-
-/* Instruction formats. */
-
-#define F(f) & openrisc_cgen_ifld_table[OPENRISC_##f]
-static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
- 0, 0, 0x0, { { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_j ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_ABS26) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_jr ATTRIBUTE_UNUSED = {
- 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP3) }, { F (F_OP4) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_bal ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_DISP26) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_movhi ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_mfsr ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_mtsr ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_I16_1) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_lw ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_sw ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R3) }, { F (F_I16NC) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_sll ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_3) }, { F (F_OP6) }, { F (F_F_4_1) }, { F (F_OP7) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_slli ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc00ffe0, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_F_15_8) }, { F (F_OP6) }, { F (F_UIMM5) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_add ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc0007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_7) }, { F (F_OP7) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_addi ATTRIBUTE_UNUSED = {
- 32, 32, 0xfc000000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_R1) }, { F (F_R2) }, { F (F_LO16) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_sfgts ATTRIBUTE_UNUSED = {
- 32, 32, 0xffe007ff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_R3) }, { F (F_F_10_11) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_sfgtsi ATTRIBUTE_UNUSED = {
- 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_l_sfgtui ATTRIBUTE_UNUSED = {
- 32, 32, 0xffe00000, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP5) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
-};
-
-#undef F
-
-#define A(a) (1 << CGEN_INSN_##a)
-#define OPERAND(op) OPENRISC_OPERAND_##op
-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-
-/* The instruction table. */
-
-static const CGEN_OPCODE openrisc_cgen_insn_opcode_table[MAX_INSNS] =
-{
- /* Special null first entry.
- A `num' value of zero is thus invalid.
- Also, the special `invalid' insn resides here. */
- { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
-/* l.j ${abs-26} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (ABS_26), 0 } },
- & ifmt_l_j, { 0x0 }
- },
-/* l.jal ${abs-26} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (ABS_26), 0 } },
- & ifmt_l_j, { 0x4000000 }
- },
-/* l.jr $rA */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), 0 } },
- & ifmt_l_jr, { 0x14000000 }
- },
-/* l.jalr $rA */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), 0 } },
- & ifmt_l_jr, { 0x14200000 }
- },
-/* l.bal ${disp-26} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DISP_26), 0 } },
- & ifmt_l_bal, { 0x8000000 }
- },
-/* l.bnf ${disp-26} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DISP_26), 0 } },
- & ifmt_l_bal, { 0xc000000 }
- },
-/* l.bf ${disp-26} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DISP_26), 0 } },
- & ifmt_l_bal, { 0x10000000 }
- },
-/* l.brk ${uimm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (UIMM_16), 0 } },
- & ifmt_l_jr, { 0x17000000 }
- },
-/* l.rfe $rA */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), 0 } },
- & ifmt_l_jr, { 0x14400000 }
- },
-/* l.sys ${uimm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (UIMM_16), 0 } },
- & ifmt_l_jr, { 0x16000000 }
- },
-/* l.nop */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_l_jr, { 0x15000000 }
- },
-/* l.movhi $rD,$hi16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (HI16), 0 } },
- & ifmt_l_movhi, { 0x18000000 }
- },
-/* l.mfsr $rD,$rA */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), 0 } },
- & ifmt_l_mfsr, { 0x1c000000 }
- },
-/* l.mtsr $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_mtsr, { 0x40000000 }
- },
-/* l.lw $rD,${simm-16}($rA) */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } },
- & ifmt_l_lw, { 0x80000000 }
- },
-/* l.lbz $rD,${simm-16}($rA) */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } },
- & ifmt_l_lw, { 0x84000000 }
- },
-/* l.lbs $rD,${simm-16}($rA) */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } },
- & ifmt_l_lw, { 0x88000000 }
- },
-/* l.lhz $rD,${simm-16}($rA) */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } },
- & ifmt_l_lw, { 0x8c000000 }
- },
-/* l.lhs $rD,${simm-16}($rA) */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (SIMM_16), '(', OP (RA), ')', 0 } },
- & ifmt_l_lw, { 0x90000000 }
- },
-/* l.sw ${ui16nc}($rA),$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } },
- & ifmt_l_sw, { 0xd4000000 }
- },
-/* l.sb ${ui16nc}($rA),$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } },
- & ifmt_l_sw, { 0xd8000000 }
- },
-/* l.sh ${ui16nc}($rA),$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (UI16NC), '(', OP (RA), ')', ',', OP (RB), 0 } },
- & ifmt_l_sw, { 0xdc000000 }
- },
-/* l.sll $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sll, { 0xe0000008 }
- },
-/* l.slli $rD,$rA,${uimm-5} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } },
- & ifmt_l_slli, { 0xb4000000 }
- },
-/* l.srl $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sll, { 0xe0000028 }
- },
-/* l.srli $rD,$rA,${uimm-5} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } },
- & ifmt_l_slli, { 0xb4000020 }
- },
-/* l.sra $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sll, { 0xe0000048 }
- },
-/* l.srai $rD,$rA,${uimm-5} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } },
- & ifmt_l_slli, { 0xb4000040 }
- },
-/* l.ror $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sll, { 0xe0000088 }
- },
-/* l.rori $rD,$rA,${uimm-5} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM_5), 0 } },
- & ifmt_l_slli, { 0xb4000080 }
- },
-/* l.add $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_add, { 0xe0000000 }
- },
-/* l.addi $rD,$rA,$lo16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } },
- & ifmt_l_addi, { 0x94000000 }
- },
-/* l.sub $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_add, { 0xe0000002 }
- },
-/* l.subi $rD,$rA,$lo16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } },
- & ifmt_l_addi, { 0x9c000000 }
- },
-/* l.and $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_add, { 0xe0000003 }
- },
-/* l.andi $rD,$rA,$lo16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } },
- & ifmt_l_addi, { 0xa0000000 }
- },
-/* l.or $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_add, { 0xe0000004 }
- },
-/* l.ori $rD,$rA,$lo16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } },
- & ifmt_l_addi, { 0xa4000000 }
- },
-/* l.xor $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_add, { 0xe0000005 }
- },
-/* l.xori $rD,$rA,$lo16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } },
- & ifmt_l_addi, { 0xa8000000 }
- },
-/* l.mul $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_add, { 0xe0000006 }
- },
-/* l.muli $rD,$rA,$lo16 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (LO16), 0 } },
- & ifmt_l_addi, { 0xac000000 }
- },
-/* l.div $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_add, { 0xe0000009 }
- },
-/* l.divu $rD,$rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_add, { 0xe000000a }
- },
-/* l.sfgts $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sfgts, { 0xe4c00000 }
- },
-/* l.sfgtu $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sfgts, { 0xe4400000 }
- },
-/* l.sfges $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sfgts, { 0xe4e00000 }
- },
-/* l.sfgeu $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sfgts, { 0xe4600000 }
- },
-/* l.sflts $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sfgts, { 0xe5000000 }
- },
-/* l.sfltu $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sfgts, { 0xe4800000 }
- },
-/* l.sfles $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sfgts, { 0xe5200000 }
- },
-/* l.sfleu $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sfgts, { 0xe4a00000 }
- },
-/* l.sfgtsi $rA,${simm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } },
- & ifmt_l_sfgtsi, { 0xb8c00000 }
- },
-/* l.sfgtui $rA,${uimm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } },
- & ifmt_l_sfgtui, { 0xb8400000 }
- },
-/* l.sfgesi $rA,${simm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } },
- & ifmt_l_sfgtsi, { 0xb8e00000 }
- },
-/* l.sfgeui $rA,${uimm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } },
- & ifmt_l_sfgtui, { 0xb8600000 }
- },
-/* l.sfltsi $rA,${simm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } },
- & ifmt_l_sfgtsi, { 0xb9000000 }
- },
-/* l.sfltui $rA,${uimm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } },
- & ifmt_l_sfgtui, { 0xb8800000 }
- },
-/* l.sflesi $rA,${simm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } },
- & ifmt_l_sfgtsi, { 0xb9200000 }
- },
-/* l.sfleui $rA,${uimm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (UIMM_16), 0 } },
- & ifmt_l_sfgtui, { 0xb8a00000 }
- },
-/* l.sfeq $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sfgts, { 0xe4000000 }
- },
-/* l.sfeqi $rA,${simm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } },
- & ifmt_l_sfgtsi, { 0xb8000000 }
- },
-/* l.sfne $rA,$rB */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (RB), 0 } },
- & ifmt_l_sfgts, { 0xe4200000 }
- },
-/* l.sfnei $rA,${simm-16} */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (RA), ',', OP (SIMM_16), 0 } },
- & ifmt_l_sfgtsi, { 0xb8200000 }
- },
-};
-
-#undef A
-#undef OPERAND
-#undef MNEM
-#undef OP
-
-/* Formats for ALIAS macro-insns. */
-
-#define F(f) & openrisc_cgen_ifld_table[OPENRISC_##f]
-static const CGEN_IFMT ifmt_l_ret ATTRIBUTE_UNUSED = {
- 32, 32, 0xffffffff, { { F (F_CLASS) }, { F (F_SUB) }, { F (F_OP3) }, { F (F_OP4) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
-};
-
-#undef F
-
-/* Each non-simple macro entry points to an array of expansion possibilities. */
-
-#define A(a) (1 << CGEN_INSN_##a)
-#define OPERAND(op) OPENRISC_OPERAND_##op
-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-
-/* The macro instruction table. */
-
-static const CGEN_IBASE openrisc_cgen_macro_insn_table[] =
-{
-/* l.ret */
- {
- -1, "l-ret", "l.ret", 32,
- { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
- },
-};
-
-/* The macro instruction opcode table. */
-
-static const CGEN_OPCODE openrisc_cgen_macro_insn_opcode_table[] =
-{
-/* l.ret */
- {
- { 0, 0, 0, 0 },
- { { MNEM, 0 } },
- & ifmt_l_ret, { 0x140b0000 }
- },
-};
-
-#undef A
-#undef OPERAND
-#undef MNEM
-#undef OP
-
-#ifndef CGEN_ASM_HASH_P
-#define CGEN_ASM_HASH_P(insn) 1
-#endif
-
-#ifndef CGEN_DIS_HASH_P
-#define CGEN_DIS_HASH_P(insn) 1
-#endif
-
-/* Return non-zero if INSN is to be added to the hash table.
- Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
-
-static int
-asm_hash_insn_p (insn)
- const CGEN_INSN *insn ATTRIBUTE_UNUSED;
-{
- return CGEN_ASM_HASH_P (insn);
-}
-
-static int
-dis_hash_insn_p (insn)
- const CGEN_INSN *insn;
-{
- /* If building the hash table and the NO-DIS attribute is present,
- ignore. */
- if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
- return 0;
- return CGEN_DIS_HASH_P (insn);
-}
-
-#ifndef CGEN_ASM_HASH
-#define CGEN_ASM_HASH_SIZE 127
-#ifdef CGEN_MNEMONIC_OPERANDS
-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
-#else
-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
-#endif
-#endif
-
-/* It doesn't make much sense to provide a default here,
- but while this is under development we do.
- BUFFER is a pointer to the bytes of the insn, target order.
- VALUE is the first base_insn_bitsize bits as an int in host order. */
-
-#ifndef CGEN_DIS_HASH
-#define CGEN_DIS_HASH_SIZE 256
-#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
-#endif
-
-/* The result is the hash value of the insn.
- Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
-
-static unsigned int
-asm_hash_insn (mnem)
- const char * mnem;
-{
- return CGEN_ASM_HASH (mnem);
-}
-
-/* BUF is a pointer to the bytes of the insn, target order.
- VALUE is the first base_insn_bitsize bits as an int in host order. */
-
-static unsigned int
-dis_hash_insn (buf, value)
- const char * buf ATTRIBUTE_UNUSED;
- CGEN_INSN_INT value ATTRIBUTE_UNUSED;
-{
- return CGEN_DIS_HASH (buf, value);
-}
-
-/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
-
-static void
-set_fields_bitsize (CGEN_FIELDS *fields, int size)
-{
- CGEN_FIELDS_BITSIZE (fields) = size;
-}
-
-/* Function to call before using the operand instance table.
- This plugs the opcode entries and macro instructions into the cpu table. */
-
-void
-openrisc_cgen_init_opcode_table (CGEN_CPU_DESC cd)
-{
- int i;
- int num_macros = (sizeof (openrisc_cgen_macro_insn_table) /
- sizeof (openrisc_cgen_macro_insn_table[0]));
- const CGEN_IBASE *ib = & openrisc_cgen_macro_insn_table[0];
- const CGEN_OPCODE *oc = & openrisc_cgen_macro_insn_opcode_table[0];
- CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
-
- /* This test has been added to avoid a warning generated
- if memset is called with a third argument of value zero. */
- if (num_macros >= 1)
- memset (insns, 0, num_macros * sizeof (CGEN_INSN));
- for (i = 0; i < num_macros; ++i)
- {
- insns[i].base = &ib[i];
- insns[i].opcode = &oc[i];
- openrisc_cgen_build_insn_regex (& insns[i]);
- }
- cd->macro_insn_table.init_entries = insns;
- cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
- cd->macro_insn_table.num_init_entries = num_macros;
-
- oc = & openrisc_cgen_insn_opcode_table[0];
- insns = (CGEN_INSN *) cd->insn_table.init_entries;
- for (i = 0; i < MAX_INSNS; ++i)
- {
- insns[i].opcode = &oc[i];
- openrisc_cgen_build_insn_regex (& insns[i]);
- }
-
- cd->sizeof_fields = sizeof (CGEN_FIELDS);
- cd->set_fields_bitsize = set_fields_bitsize;
-
- cd->asm_hash_p = asm_hash_insn_p;
- cd->asm_hash = asm_hash_insn;
- cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
-
- cd->dis_hash_p = dis_hash_insn_p;
- cd->dis_hash = dis_hash_insn;
- cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
-}
diff --git a/opcodes/openrisc-opc.h b/opcodes/openrisc-opc.h
deleted file mode 100644
index 18b44ef..0000000
--- a/opcodes/openrisc-opc.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Instruction opcode header for openrisc.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright (C) 1996-2014 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#ifndef OPENRISC_OPC_H
-#define OPENRISC_OPC_H
-
-/* -- opc.h */
-#undef CGEN_DIS_HASH_SIZE
-#define CGEN_DIS_HASH_SIZE 64
-#undef CGEN_DIS_HASH
-#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
-
-extern long openrisc_sign_extend_16bit (long);
-/* -- */
-/* Enum declaration for openrisc instruction types. */
-typedef enum cgen_insn_type {
- OPENRISC_INSN_INVALID, OPENRISC_INSN_L_J, OPENRISC_INSN_L_JAL, OPENRISC_INSN_L_JR
- , OPENRISC_INSN_L_JALR, OPENRISC_INSN_L_BAL, OPENRISC_INSN_L_BNF, OPENRISC_INSN_L_BF
- , OPENRISC_INSN_L_BRK, OPENRISC_INSN_L_RFE, OPENRISC_INSN_L_SYS, OPENRISC_INSN_L_NOP
- , OPENRISC_INSN_L_MOVHI, OPENRISC_INSN_L_MFSR, OPENRISC_INSN_L_MTSR, OPENRISC_INSN_L_LW
- , OPENRISC_INSN_L_LBZ, OPENRISC_INSN_L_LBS, OPENRISC_INSN_L_LHZ, OPENRISC_INSN_L_LHS
- , OPENRISC_INSN_L_SW, OPENRISC_INSN_L_SB, OPENRISC_INSN_L_SH, OPENRISC_INSN_L_SLL
- , OPENRISC_INSN_L_SLLI, OPENRISC_INSN_L_SRL, OPENRISC_INSN_L_SRLI, OPENRISC_INSN_L_SRA
- , OPENRISC_INSN_L_SRAI, OPENRISC_INSN_L_ROR, OPENRISC_INSN_L_RORI, OPENRISC_INSN_L_ADD
- , OPENRISC_INSN_L_ADDI, OPENRISC_INSN_L_SUB, OPENRISC_INSN_L_SUBI, OPENRISC_INSN_L_AND
- , OPENRISC_INSN_L_ANDI, OPENRISC_INSN_L_OR, OPENRISC_INSN_L_ORI, OPENRISC_INSN_L_XOR
- , OPENRISC_INSN_L_XORI, OPENRISC_INSN_L_MUL, OPENRISC_INSN_L_MULI, OPENRISC_INSN_L_DIV
- , OPENRISC_INSN_L_DIVU, OPENRISC_INSN_L_SFGTS, OPENRISC_INSN_L_SFGTU, OPENRISC_INSN_L_SFGES
- , OPENRISC_INSN_L_SFGEU, OPENRISC_INSN_L_SFLTS, OPENRISC_INSN_L_SFLTU, OPENRISC_INSN_L_SFLES
- , OPENRISC_INSN_L_SFLEU, OPENRISC_INSN_L_SFGTSI, OPENRISC_INSN_L_SFGTUI, OPENRISC_INSN_L_SFGESI
- , OPENRISC_INSN_L_SFGEUI, OPENRISC_INSN_L_SFLTSI, OPENRISC_INSN_L_SFLTUI, OPENRISC_INSN_L_SFLESI
- , OPENRISC_INSN_L_SFLEUI, OPENRISC_INSN_L_SFEQ, OPENRISC_INSN_L_SFEQI, OPENRISC_INSN_L_SFNE
- , OPENRISC_INSN_L_SFNEI
-} CGEN_INSN_TYPE;
-
-/* Index of `invalid' insn place holder. */
-#define CGEN_INSN_INVALID OPENRISC_INSN_INVALID
-
-/* Total number of insns in table. */
-#define MAX_INSNS ((int) OPENRISC_INSN_L_SFNEI + 1)
-
-/* This struct records data prior to insertion or after extraction. */
-struct cgen_fields
-{
- int length;
- long f_nil;
- long f_anyof;
- long f_class;
- long f_sub;
- long f_r1;
- long f_r2;
- long f_r3;
- long f_simm16;
- long f_uimm16;
- long f_uimm5;
- long f_hi16;
- long f_lo16;
- long f_op1;
- long f_op2;
- long f_op3;
- long f_op4;
- long f_op5;
- long f_op6;
- long f_op7;
- long f_i16_1;
- long f_i16_2;
- long f_disp26;
- long f_abs26;
- long f_i16nc;
- long f_f_15_8;
- long f_f_10_3;
- long f_f_4_1;
- long f_f_7_3;
- long f_f_10_7;
- long f_f_10_11;
-};
-
-#define CGEN_INIT_PARSE(od) \
-{\
-}
-#define CGEN_INIT_INSERT(od) \
-{\
-}
-#define CGEN_INIT_EXTRACT(od) \
-{\
-}
-#define CGEN_INIT_PRINT(od) \
-{\
-}
-
-
-#endif /* OPENRISC_OPC_H */
diff --git a/opcodes/or32-dis.c b/opcodes/or32-dis.c
deleted file mode 100644
index b015d12..0000000
--- a/opcodes/or32-dis.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/* Instruction printing code for the OpenRISC 1000
- Copyright (C) 2002-2014 Free Software Foundation, Inc.
- Contributed by Damjan Lampret <lampret@opencores.org>.
- Modified from a29k port.
-
- This file is part of the GNU opcodes library.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
- MA 02110-1301, USA. */
-
-#ifndef DEBUG
-#define DEBUG 0
-#endif
-
-#include "sysdep.h"
-#include "dis-asm.h"
-#include "opcode/or32.h"
-#include "safe-ctype.h"
-
-#define EXTEND29(x) ((x) & (unsigned long) 0x10000000 ? ((x) | (unsigned long) 0xf0000000) : ((x)))
-
-/* Now find the four bytes of INSN_CH and put them in *INSN. */
-
-static void
-find_bytes_big (unsigned char *insn_ch, unsigned long *insn)
-{
- *insn =
- ((unsigned long) insn_ch[0] << 24) +
- ((unsigned long) insn_ch[1] << 16) +
- ((unsigned long) insn_ch[2] << 8) +
- ((unsigned long) insn_ch[3]);
-#if DEBUG
- printf ("find_bytes_big3: %lx\n", *insn);
-#endif
-}
-
-static void
-find_bytes_little (unsigned char *insn_ch, unsigned long *insn)
-{
- *insn =
- ((unsigned long) insn_ch[3] << 24) +
- ((unsigned long) insn_ch[2] << 16) +
- ((unsigned long) insn_ch[1] << 8) +
- ((unsigned long) insn_ch[0]);
-}
-
-typedef void (*find_byte_func_type) (unsigned char *, unsigned long *);
-
-static unsigned long
-or32_extract (char param_ch, char *enc_initial, unsigned long insn)
-{
- char *enc;
- unsigned long ret = 0;
- int opc_pos = 0;
- int param_pos = 0;
-
- for (enc = enc_initial; *enc != '\0'; enc++)
- if (*enc == param_ch)
- {
- if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x'))
- continue;
- else
- param_pos++;
- }
-
-#if DEBUG
- printf ("or32_extract: %c %x ", param_ch, param_pos);
-#endif
- opc_pos = 32;
-
- for (enc = enc_initial; *enc != '\0'; )
- if ((*enc == '0') && (*(enc + 1) == 'x'))
- {
- opc_pos -= 4;
-
- if ((param_ch == '0') || (param_ch == '1'))
- {
- unsigned long tmp = strtoul (enc, NULL, 16);
-#if DEBUG
- printf (" enc=%s, tmp=%lx ", enc, tmp);
-#endif
- if (param_ch == '0')
- tmp = 15 - tmp;
- ret |= tmp << opc_pos;
- }
- enc += 3;
- }
- else if ((*enc == '0') || (*enc == '1'))
- {
- opc_pos--;
- if (param_ch == *enc)
- ret |= 1 << opc_pos;
- enc++;
- }
- else if (*enc == param_ch)
- {
- opc_pos--;
- param_pos--;
-#if DEBUG
- printf ("\n ret=%lx opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos);
-#endif
- ret += ((insn >> opc_pos) & 0x1) << param_pos;
-
- if (!param_pos
- && letter_signed (param_ch)
- && ret >> (letter_range (param_ch) - 1))
- {
-#if DEBUG
- printf ("\n ret=%lx opc_pos=%x, param_pos=%x\n",
- ret, opc_pos, param_pos);
-#endif
- ret |= 0xffffffff << letter_range(param_ch);
-#if DEBUG
- printf ("\n after conversion to signed: ret=%lx\n", ret);
-#endif
- }
- enc++;
- }
- else if (ISALPHA (*enc))
- {
- opc_pos--;
- enc++;
- }
- else if (*enc == '-')
- {
- opc_pos--;
- enc++;
- }
- else
- enc++;
-
-#if DEBUG
- printf ("ret=%lx\n", ret);
-#endif
- return ret;
-}
-
-static int
-or32_opcode_match (unsigned long insn, char *encoding)
-{
- unsigned long ones, zeros;
-
-#if DEBUG
- printf ("or32_opcode_match: %.8lx\n", insn);
-#endif
- ones = or32_extract ('1', encoding, insn);
- zeros = or32_extract ('0', encoding, insn);
-
-#if DEBUG
- printf ("ones: %lx \n", ones);
- printf ("zeros: %lx \n", zeros);
-#endif
- if ((insn & ones) != ones)
- {
-#if DEBUG
- printf ("ret1\n");
-#endif
- return 0;
- }
-
- if ((~insn & zeros) != zeros)
- {
-#if DEBUG
- printf ("ret2\n");
-#endif
- return 0;
- }
-
-#if DEBUG
- printf ("ret3\n");
-#endif
- return 1;
-}
-
-/* Print register to INFO->STREAM. Used only by print_insn. */
-
-static void
-or32_print_register (char param_ch,
- char *encoding,
- unsigned long insn,
- struct disassemble_info *info)
-{
- int regnum = or32_extract (param_ch, encoding, insn);
-
-#if DEBUG
- printf ("or32_print_register: %c, %s, %lx\n", param_ch, encoding, insn);
-#endif
- if (param_ch == 'A')
- (*info->fprintf_func) (info->stream, "r%d", regnum);
- else if (param_ch == 'B')
- (*info->fprintf_func) (info->stream, "r%d", regnum);
- else if (param_ch == 'D')
- (*info->fprintf_func) (info->stream, "r%d", regnum);
- else if (regnum < 16)
- (*info->fprintf_func) (info->stream, "r%d", regnum);
- else if (regnum < 32)
- (*info->fprintf_func) (info->stream, "r%d", regnum-16);
- else
- (*info->fprintf_func) (info->stream, "X%d", regnum);
-}
-
-/* Print immediate to INFO->STREAM. Used only by print_insn. */
-
-static void
-or32_print_immediate (char param_ch,
- char *encoding,
- unsigned long insn,
- struct disassemble_info *info)
-{
- int imm = or32_extract(param_ch, encoding, insn);
-
- if (letter_signed(param_ch))
- (*info->fprintf_func) (info->stream, "0x%x", imm);
-/* (*info->fprintf_func) (info->stream, "%d", imm); */
- else
- (*info->fprintf_func) (info->stream, "0x%x", imm);
-}
-
-/* Print one instruction from MEMADDR on INFO->STREAM.
- Return the size of the instruction (always 4 on or32). */
-
-static int
-print_insn (bfd_vma memaddr, struct disassemble_info *info)
-{
- /* The raw instruction. */
- unsigned char insn_ch[4];
- /* Address. Will be sign extened 27-bit. */
- unsigned long addr;
- /* The four bytes of the instruction. */
- unsigned long insn;
- find_byte_func_type find_byte_func = (find_byte_func_type) info->private_data;
- struct or32_opcode const * opcode;
-
- {
- int status =
- (*info->read_memory_func) (memaddr, (bfd_byte *) &insn_ch[0], 4, info);
-
- if (status != 0)
- {
- (*info->memory_error_func) (status, memaddr, info);
- return -1;
- }
- }
-
- (*find_byte_func) (&insn_ch[0], &insn);
-
- for (opcode = &or32_opcodes[0];
- opcode < &or32_opcodes[or32_num_opcodes];
- ++opcode)
- {
- if (or32_opcode_match (insn, opcode->encoding))
- {
- char *s;
-
- (*info->fprintf_func) (info->stream, "%s ", opcode->name);
-
- for (s = opcode->args; *s != '\0'; ++s)
- {
- switch (*s)
- {
- case '\0':
- return 4;
-
- case 'r':
- or32_print_register (*++s, opcode->encoding, insn, info);
- break;
-
- case 'X':
- addr = or32_extract ('X', opcode->encoding, insn) << 2;
-
- /* Calulate the correct address. XXX is this really correct ?? */
- addr = memaddr + EXTEND29 (addr);
-
- (*info->print_address_func)
- (addr, info);
- break;
-
- default:
- if (strchr (opcode->encoding, *s))
- or32_print_immediate (*s, opcode->encoding, insn, info);
- else
- (*info->fprintf_func) (info->stream, "%c", *s);
- }
- }
-
- return 4;
- }
- }
-
- /* This used to be %8x for binutils. */
- (*info->fprintf_func)
- (info->stream, ".word 0x%08lx", insn);
- return 4;
-}
-
-/* Disassemble a big-endian or32 instruction. */
-
-int
-print_insn_big_or32 (bfd_vma memaddr, struct disassemble_info *info)
-{
- info->private_data = find_bytes_big;
-
- return print_insn (memaddr, info);
-}
-
-/* Disassemble a little-endian or32 instruction. */
-
-int
-print_insn_little_or32 (bfd_vma memaddr, struct disassemble_info *info)
-{
- info->private_data = find_bytes_little;
- return print_insn (memaddr, info);
-}
diff --git a/opcodes/or32-opc.c b/opcodes/or32-opc.c
deleted file mode 100644
index f4bc706..0000000
--- a/opcodes/or32-opc.c
+++ /dev/null
@@ -1,1030 +0,0 @@
-/* Table of opcodes for the OpenRISC 1000 ISA.
- Copyright (C) 2002-2014 Free Software Foundation, Inc.
- Contributed by Damjan Lampret (lampret@opencores.org).
-
- This file is part of the GNU opcodes library.
-
- This library is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
- MA 02110-1301, USA. */
-
-#include "sysdep.h"
-#include <string.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include "safe-ctype.h"
-#include "ansidecl.h"
-#include "opcode/or32.h"
-
-/* We treat all letters the same in encode/decode routines so
- we need to assign some characteristics to them like signess etc. */
-
-const struct or32_letter or32_letters[] =
-{
- { 'A', NUM_UNSIGNED },
- { 'B', NUM_UNSIGNED },
- { 'D', NUM_UNSIGNED },
- { 'I', NUM_SIGNED },
- { 'K', NUM_UNSIGNED },
- { 'L', NUM_UNSIGNED },
- { 'N', NUM_SIGNED },
- { '0', NUM_UNSIGNED },
- { '\0', 0 } /* Dummy entry. */
-};
-
-/* Opcode encoding:
- machine[31:30]: first two bits of opcode
- 00 - neither of source operands is GPR
- 01 - second source operand is GPR (rB)
- 10 - first source operand is GPR (rA)
- 11 - both source operands are GPRs (rA and rB)
- machine[29:26]: next four bits of opcode
- machine[25:00]: instruction operands (specific to individual instruction)
-
- Recommendation: irrelevant instruction bits should be set with a value of
- bits in same positions of instruction preceding current instruction in the
- code (when assembling). */
-
-#define EFN &l_none
-
-#ifdef HAS_EXECUTION
-#define EF(func) &(func)
-#define EFI &l_invalid
-#else /* HAS_EXECUTION */
-#define EF(func) EFN
-#define EFI EFN
-#endif /* HAS_EXECUTION */
-
-const struct or32_opcode or32_opcodes[] =
-{
- { "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY },
- { "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY },
- { "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG},
- { "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG },
- { "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 },
- { "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/
- { "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/
-
- { "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 },
- { "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */
- { "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 },
- { "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 },
- { "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 },
- { "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY },
-
- { "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
- { "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
- { "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
- { "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
- { "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
- { "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
- { "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
- { "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
- { "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
- { "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
- { "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
- { "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
- { "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 },
- { "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 },
- { "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 },
- { "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 },
- { "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 },
- { "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 },
- { "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 },
- { "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 },
- { "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 },
- { "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 },
- { "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 },
- { "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 },
- { "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 },
- { "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 },
- { "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 },
- { "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 },
- { "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 },
- { "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 },
- { "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 },
- { "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 },
- { "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 },
- { "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 },
- { "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 },
- { "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 },
- { "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 },
- { "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 },
- { "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 },
- { "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 },
- { "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 },
- { "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 },
- { "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 },
- { "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 },
- { "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 },
- { "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 },
- { "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 },
- { "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 },
- { "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 },
- { "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 },
- { "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 },
- { "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 },
- { "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 },
- { "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 },
- { "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 },
- { "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 },
- { "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 },
- { "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 },
- { "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 },
- { "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 },
- { "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 },
- { "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 },
- { "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 },
- { "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 },
- { "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 },
- { "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 },
- { "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 },
- { "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 },
- { "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 },
- { "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 },
- { "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 },
- { "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 },
- { "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 },
- { "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 },
- { "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 },
- { "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 },
- { "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 },
- { "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 },
- { "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 },
- { "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 },
- { "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 },
- { "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 },
- { "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 },
- { "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 },
- { "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 },
- { "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 },
- { "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 },
- { "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 },
- { "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 },
- { "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 },
- { "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 },
-
- { "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
- { "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
- { "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
- { "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
- { "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
- { "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
- { "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
- { "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
- { "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
- { "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
- { "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
- { "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
- { "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
- { "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
- { "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI, 0 },
-
- { "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
- { "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
- { "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 },
- { "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 },
- { "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 },
- { "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 },
- { "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 },
- { "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 },
- { "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 },
- { "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 },
- { "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 },
- { "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 },
- { "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 },
- { "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 },
- { "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI, 0 },
-
- { "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 },
- { "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 },
- { "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 },
- { "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 },
-
- { "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY },
- { "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY },
- { "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 },
- { "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 },
- { "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 },
- { "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 },
- { "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 },
-
- { "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
- { "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 },
- { "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
- { "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 },
- { "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 },
- { "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 },
- { "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 },
-
- { "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 },
- { "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
- { "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 },
- { "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 },
- { "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 },
- { "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 },
- { "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 },
- { "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 },
- { "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 },
- { "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 },
- { "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 },
-
- { "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG },
- { "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG },
- { "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG },
- { "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG },
- { "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG },
- { "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG },
- { "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG },
- { "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG },
- { "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG },
- { "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG },
-
- { "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 },
- { "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/
- { "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/
-
- { "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 },
- { "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 },
- { "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 },
- { "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 },
-
- { "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 },
- { "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 },
- { "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 },
- { "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 },
- { "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 },
- { "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 },
- { "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 },
-
- { "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 },
- { "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 },
- { "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 },
- { "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 },
- { "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 },
- { "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 },
- { "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 },
- { "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 },
- { "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 },
- { "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 },
- { "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 },
- { "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 },
- { "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 },
- { "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 },
- { "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 },
-
- { "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG },
- { "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG },
- { "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG },
- { "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG },
- { "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG },
- { "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG },
- { "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG },
- { "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG },
- { "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG },
- { "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG },
-
- { "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI, 0 },
- { "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 },
- { "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 },
- { "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 },
-
- /* This section should not be defined in or1ksim, since it contains duplicates,
- which would cause machine builder to complain. */
-#ifdef HAS_CUST
- { "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 },
- { "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
- { "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
-
- { "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 },
- { "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
- { "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
-
- { "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 },
- { "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
- { "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
-
- { "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 },
- { "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 },
- { "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 },
-#endif
-
- /* Dummy entry, not included in num_opcodes. This
- lets code examine entry i+1 without checking
- if we've run off the end of the table. */
- { "", "", "", EFI, 0 }
-};
-
-#undef EFI
-#undef EFN
-#undef EF
-
-/* Define dummy, if debug is not defined. */
-
-#if !defined HAS_DEBUG
-static void ATTRIBUTE_PRINTF_2
-debug (int level ATTRIBUTE_UNUSED, const char *format ATTRIBUTE_UNUSED, ...)
-{
-}
-#endif
-
-const unsigned int or32_num_opcodes = ((sizeof(or32_opcodes)) / (sizeof(struct or32_opcode))) - 1;
-
-/* Calculates instruction length in bytes. Always 4 for OR32. */
-
-int
-insn_len (int i_index ATTRIBUTE_UNUSED)
-{
- return 4;
-}
-
-/* Is individual insn's operand signed or unsigned? */
-
-int
-letter_signed (char l)
-{
- const struct or32_letter *pletter;
-
- for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
- if (pletter->letter == l)
- return pletter->sign;
-
- printf ("letter_signed(%c): Unknown letter.\n", l);
- return 0;
-}
-
-/* Number of letters in the individual lettered operand. */
-
-int
-letter_range (char l)
-{
- const struct or32_opcode *pinsn;
- char *enc;
- int range = 0;
-
- for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn ++)
- {
- if (strchr (pinsn->encoding,l))
- {
- for (enc = pinsn->encoding; *enc != '\0'; enc ++)
- if ((*enc == '0') && (*(enc + 1) == 'x'))
- enc += 2;
- else if (*enc == l)
- range++;
- return range;
- }
- }
-
- printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
- exit (1);
-}
-
-/* MM: Returns index of given instruction name. */
-
-int
-insn_index (char *insn)
-{
- unsigned int i;
- int found = -1;
-
- for (i = 0; i < or32_num_opcodes; i++)
- if (!strcmp (or32_opcodes[i].name, insn))
- {
- found = i;
- break;
- }
- return found;
-}
-
-const char *
-insn_name (int op_index)
-{
- if (op_index >= 0 && op_index < (int) or32_num_opcodes)
- return or32_opcodes[op_index].name;
- else
- return "???";
-}
-
-void
-l_none (void)
-{
-}
-
-/* Finite automata for instruction decoding building code. */
-
-/* Find simbols in encoding. */
-
-static unsigned long
-insn_extract (char param_ch, char *enc_initial)
-{
- char *enc;
- unsigned long ret = 0;
- unsigned opc_pos = 32;
-
- for (enc = enc_initial; *enc != '\0'; )
- if ((*enc == '0') && (*(enc + 1) == 'x'))
- {
- unsigned long tmp = strtol (enc+2, NULL, 16);
-
- opc_pos -= 4;
- if (param_ch == '0' || param_ch == '1')
- {
- if (param_ch == '0')
- tmp = 15 - tmp;
- ret |= tmp << opc_pos;
- }
- enc += 3;
- }
- else
- {
- if (*enc == '0' || *enc == '1' || *enc == '-' || ISALPHA (*enc))
- {
- opc_pos--;
- if (param_ch == *enc)
- ret |= 1 << opc_pos;
- }
- enc++;
- }
- return ret;
-}
-
-#define MAX_AUTOMATA_SIZE 1200
-#define MAX_OP_TABLE_SIZE 1200
-#define LEAF_FLAG 0x80000000
-#define MAX_LEN 8
-
-#ifndef MIN
-#define MIN(x, y) ((x) < (y) ? (x) : (y))
-#endif
-
-unsigned long *automata;
-int nuncovered;
-int curpass = 0;
-
-/* MM: Struct that hold runtime build information about instructions. */
-struct temp_insn_struct
-{
- unsigned long insn;
- unsigned long insn_mask;
- int in_pass;
-} *ti;
-
-struct insn_op_struct *op_data, **op_start;
-
-/* Recursive utility function used to find best match and to build automata. */
-
-static unsigned long *
-cover_insn (unsigned long * cur, int pass, unsigned int mask)
-{
- int best_first = 0, last_match = -1, ninstr = 0;
- unsigned int best_len = 0;
- unsigned int i;
- unsigned long cur_mask = mask;
- unsigned long *next;
-
- for (i = 0; i < or32_num_opcodes; i++)
- if (ti[i].in_pass == pass)
- {
- cur_mask &= ti[i].insn_mask;
- ninstr++;
- last_match = i;
- }
-
- debug (8, "%08X %08lX\n", mask, cur_mask);
-
- if (ninstr == 0)
- return 0;
-
- if (ninstr == 1)
- {
- /* Leaf holds instruction index. */
- debug (8, "%li>I%i %s\n",
- (long)(cur - automata), last_match, or32_opcodes[last_match].name);
-
- *cur = LEAF_FLAG | last_match;
- cur++;
- nuncovered--;
- }
- else
- {
- /* Find longest match. */
- for (i = 0; i < 32; i++)
- {
- unsigned int len;
-
- for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
- {
- unsigned long m = (1UL << ((unsigned long) len)) - 1;
-
- debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)",
- len,m, cur_mask, i, (cur_mask >> (unsigned)i),
- (cur_mask >> (unsigned) i) & m);
-
- if ((m & (cur_mask >> (unsigned) i)) == m)
- {
- best_len = len;
- best_first = i;
- debug (9, "!");
- }
- else
- break;
- }
- }
-
- debug (9, "\n");
-
- if (!best_len)
- {
- fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr, mask);
-
- for (i = 0; i < or32_num_opcodes; i++)
- if (ti[i].in_pass == pass)
- fprintf (stderr, "%s ", or32_opcodes[i].name);
-
- fprintf (stderr, "\n");
- exit (1);
- }
-
- debug (8, "%li> #### %i << %i (%i) ####\n",
- (long)(cur - automata), best_len, best_first, ninstr);
-
- *cur = best_first;
- cur++;
- *cur = (1 << best_len) - 1;
- cur++;
- next = cur;
-
- /* Allocate space for pointers. */
- cur += 1 << best_len;
- cur_mask = (1 << (unsigned long) best_len) - 1;
-
- for (i = 0; i < ((unsigned) 1 << best_len); i++)
- {
- unsigned int j;
- unsigned long *c;
-
- curpass++;
- for (j = 0; j < or32_num_opcodes; j++)
- if (ti[j].in_pass == pass
- && ((ti[j].insn >> best_first) & cur_mask) == (unsigned long) i
- && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
- ti[j].in_pass = curpass;
-
- debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first);
- c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
- if (c)
- {
- debug (8, "%li> #%X -> %lu\n", (long)(next - automata), i,
- (unsigned long)(cur - automata));
- *next = cur - automata;
- cur = c;
- }
- else
- {
- debug (8, "%li> N/A\n", (long)(next - automata));
- *next = 0;
- }
- next++;
- }
- }
- return cur;
-}
-
-/* Returns number of nonzero bits. */
-
-static int
-num_ones (unsigned long value)
-{
- int c = 0;
-
- while (value)
- {
- if (value & 1)
- c++;
- value >>= 1;
- }
- return c;
-}
-
-/* Utility function, which converts parameters from or32_opcode
- format to more binary form. Parameters are stored in ti struct. */
-
-static struct insn_op_struct *
-parse_params (const struct or32_opcode * opcode,
- struct insn_op_struct * cur)
-{
- char *args = opcode->args;
- int i, type;
-
- i = 0;
- type = 0;
- /* In case we don't have any parameters, we add dummy read from r0. */
-
- if (!(*args))
- {
- cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
- cur->data = 0;
- debug (9, "#%08lX %08lX\n", cur->type, cur->data);
- cur++;
- return cur;
- }
-
- while (*args != '\0')
- {
- if (*args == 'r')
- {
- args++;
- type |= OPTYPE_REG;
- }
- else if (ISALPHA (*args))
- {
- unsigned long arg;
-
- arg = insn_extract (*args, opcode->encoding);
- debug (9, "%s : %08lX ------\n", opcode->name, arg);
- if (letter_signed (*args))
- {
- type |= OPTYPE_SIG;
- type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
- }
-
- /* Split argument to sequences of consecutive ones. */
- while (arg)
- {
- int shr = 0;
- unsigned long tmp = arg, mask = 0;
-
- while ((tmp & 1) == 0)
- {
- shr++;
- tmp >>= 1;
- }
- while (tmp & 1)
- {
- mask++;
- tmp >>= 1;
- }
- cur->type = type | shr;
- cur->data = mask;
- arg &= ~(((1 << mask) - 1) << shr);
- debug (6, "|%08lX %08lX\n", cur->type, cur->data);
- cur++;
- }
- args++;
- }
- else if (*args == '(')
- {
- /* Next param is displacement.
- Later we will treat them as one operand. */
- cur--;
- cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP;
- debug (9, ">%08lX %08lX\n", cur->type, cur->data);
- cur++;
- type = 0;
- i++;
- args++;
- }
- else if (*args == OPERAND_DELIM)
- {
- cur--;
- cur->type = type | cur->type | OPTYPE_OP;
- debug (9, ">%08lX %08lX\n", cur->type, cur->data);
- cur++;
- type = 0;
- i++;
- args++;
- }
- else if (*args == '0')
- {
- cur->type = type;
- cur->data = 0;
- debug (9, ">%08lX %08lX\n", cur->type, cur->data);
- cur++;
- type = 0;
- i++;
- args++;
- }
- else if (*args == ')')
- args++;
- else
- {
- fprintf (stderr, "%s : parse error in args.\n", opcode->name);
- exit (1);
- }
- }
-
- cur--;
- cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
- debug (9, "#%08lX %08lX\n", cur->type, cur->data);
- cur++;
-
- return cur;
-}
-
-/* Constructs new automata based on or32_opcodes array. */
-
-void
-build_automata (void)
-{
- unsigned int i;
- unsigned long *end;
- struct insn_op_struct *cur;
-
- automata = malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
- ti = malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes);
-
- nuncovered = or32_num_opcodes;
- printf ("Building automata... ");
- /* Build temporary information about instructions. */
- for (i = 0; i < or32_num_opcodes; i++)
- {
- unsigned long ones, zeros;
- char *encoding = or32_opcodes[i].encoding;
-
- ones = insn_extract('1', encoding);
- zeros = insn_extract('0', encoding);
-
- ti[i].insn_mask = ones | zeros;
- ti[i].insn = ones;
- ti[i].in_pass = curpass = 0;
-
- /*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
- or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn);*/
- }
-
- /* Until all are covered search for best criteria to separate them. */
- end = cover_insn (automata, curpass, 0xFFFFFFFF);
-
- if (end - automata > MAX_AUTOMATA_SIZE)
- {
- fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
- exit (1);
- }
-
- printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes);
- printf ("Parsing operands data... ");
-
- op_data = malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct));
- op_start = malloc (or32_num_opcodes * sizeof (struct insn_op_struct *));
- cur = op_data;
-
- for (i = 0; i < or32_num_opcodes; i++)
- {
- op_start[i] = cur;
- cur = parse_params (&or32_opcodes[i], cur);
-
- if (cur - op_data > MAX_OP_TABLE_SIZE)
- {
- fprintf (stderr, "Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
- exit (1);
- }
- }
- printf ("done.\n");
-}
-
-void
-destruct_automata (void)
-{
- free (ti);
- free (automata);
- free (op_data);
- free (op_start);
-}
-
-/* Decodes instruction and returns instruction index. */
-
-int
-insn_decode (unsigned int insn)
-{
- unsigned long *a = automata;
- int i;
-
- while (!(*a & LEAF_FLAG))
- {
- unsigned int first = *a;
-
- debug (9, "%li ", (long)(a - automata));
-
- a++;
- i = (insn >> first) & *a;
- a++;
- if (!*(a + i))
- {
- /* Invalid instruction found? */
- debug (9, "XXX\n");
- return -1;
- }
- a = automata + *(a + i);
- }
-
- i = *a & ~LEAF_FLAG;
-
- debug (9, "%i\n", i);
-
- /* Final check - do we have direct match?
- (based on or32_opcodes this should be the only possibility,
- but in case of invalid/missing instruction we must perform a check) */
- if ((ti[i].insn_mask & insn) == ti[i].insn)
- return i;
- else
- return -1;
-}
-
-static char disassembled_str[50];
-char *disassembled = &disassembled_str[0];
-
-/* Automagically does zero- or sign- extension and also finds correct
- sign bit position if sign extension is correct extension. Which extension
- is proper is figured out from letter description. */
-
-static unsigned long
-extend_imm (unsigned long imm, char l)
-{
- unsigned long mask;
- int letter_bits;
-
- /* First truncate all bits above valid range for this letter
- in case it is zero extend. */
- letter_bits = letter_range (l);
- mask = (1 << letter_bits) - 1;
- imm &= mask;
-
- /* Do sign extend if this is the right one. */
- if (letter_signed(l) && (imm >> (letter_bits - 1)))
- imm |= (~mask);
-
- return imm;
-}
-
-static unsigned long
-or32_extract (char param_ch, char *enc_initial, unsigned long insn)
-{
- char *enc;
- unsigned long ret = 0;
- int opc_pos = 0;
- int param_pos = 0;
-
- for (enc = enc_initial; *enc != '\0'; enc++)
- if (*enc == param_ch)
- {
- if (enc - 2 >= enc_initial && (*(enc - 2) == '0') && (*(enc - 1) == 'x'))
- continue;
- else
- param_pos++;
- }
-
-#if DEBUG
- printf ("or32_extract: %x ", param_pos);
-#endif
- opc_pos = 32;
-
- for (enc = enc_initial; *enc != '\0'; )
- if ((*enc == '0') && (*(enc + 1) == 'x'))
- {
- opc_pos -= 4;
- if ((param_ch == '0') || (param_ch == '1'))
- {
- unsigned long tmp = strtol (enc, NULL, 16);
-#if DEBUG
- printf (" enc=%s, tmp=%lx ", enc, tmp);
-#endif
- if (param_ch == '0')
- tmp = 15 - tmp;
- ret |= tmp << opc_pos;
- }
- enc += 3;
- }
- else if ((*enc == '0') || (*enc == '1'))
- {
- opc_pos--;
- if (param_ch == *enc)
- ret |= 1 << opc_pos;
- enc++;
- }
- else if (*enc == param_ch)
- {
- opc_pos--;
- param_pos--;
-#if DEBUG
- printf ("\n ret=%lx opc_pos=%x, param_pos=%x\n", ret, opc_pos, param_pos);
-#endif
- if (ISLOWER (param_ch))
- ret -= ((insn >> opc_pos) & 0x1) << param_pos;
- else
- ret += ((insn >> opc_pos) & 0x1) << param_pos;
- enc++;
- }
- else if (ISALPHA (*enc))
- {
- opc_pos--;
- enc++;
- }
- else if (*enc == '-')
- {
- opc_pos--;
- enc++;
- }
- else
- enc++;
-
-#if DEBUG
- printf ("ret=%lx\n", ret);
-#endif
- return ret;
-}
-
-/* Print register. Used only by print_insn. */
-
-static void
-or32_print_register (char param_ch, char *encoding, unsigned long insn)
-{
- int regnum = or32_extract(param_ch, encoding, insn);
- char s_regnum[20];
-
- sprintf (s_regnum, "r%d", regnum);
- strcat (disassembled, s_regnum);
-}
-
-/* Print immediate. Used only by print_insn. */
-
-static void
-or32_print_immediate (char param_ch, char *encoding, unsigned long insn)
-{
- int imm = or32_extract (param_ch, encoding, insn);
- char s_imm[20];
-
- imm = extend_imm (imm, param_ch);
-
- if (letter_signed (param_ch))
- {
- if (imm < 0)
- sprintf (s_imm, "%d", imm);
- else
- sprintf (s_imm, "0x%x", imm);
- }
- else
- sprintf (s_imm, "%#x", imm);
- strcat (disassembled, s_imm);
-}
-
-/* Disassemble one instruction from insn to disassemble.
- Return the size of the instruction. */
-
-int
-disassemble_insn (unsigned long insn)
-{
- int op_index;
- op_index = insn_decode (insn);
-
- if (op_index >= 0)
- {
- struct or32_opcode const *opcode = &or32_opcodes[op_index];
- char *s;
-
- sprintf (disassembled, "%s ", opcode->name);
- for (s = opcode->args; *s != '\0'; ++s)
- {
- switch (*s)
- {
- case '\0':
- return 4;
-
- case 'r':
- or32_print_register (*++s, opcode->encoding, insn);
- break;
-
- default:
- if (strchr (opcode->encoding, *s))
- or32_print_immediate (*s, opcode->encoding, insn);
- else
- {
- char s_encoding[2] = { *s, '\0' };
-
- strcat (disassembled, s_encoding);
- }
-
- }
- }
- }
- else
- {
- char s_insn[20];
-
- /* This used to be %8x for binutils. */
- sprintf (s_insn, ".word 0x%08lx", insn);
- strcat (disassembled, s_insn);
- }
-
- return insn_len (insn);
-}
--
1.7.10.4