[MIPS] avoiding certain instruction in delay slots

[Sven Anderson <sven at anderson dot de>]

Hi,

I'm working with an 24kc-based SoC for which - because of an errata - 
certain instructions must not appear in branch delay slots (mainly lw 
and sw). I could generally use gcc's -fno-delayed-branch to compile for 
the target. But this has the two disadvantages that, 1. I additionally 
have to manually patch assembler code, and 2. I disable more 
optimization than necessary. Therefore I tried to patch gas to produce 
according code by adapting the fix-24kc code in tc-mips.c, but it didn't 
work as expected. It's probably because I have no clue how exactly the 
process of assembling really works, that is when and if the delay slots 
are filled by gas, for instance.

Therefore I want to kindly ask to give me some advice how to implement 
this correctly. Would it even be possible to apply the constrain even to 
noreorder assembly-code or at least give a warning about it? If this is 
of general interest, I would be happy to submit a patch.

Thanks in advance and best regards,

Sven