This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH] MIPS/opcodes: Add MFCR and MTCR data dependencies
- From: "Maciej W. Rozycki" <macro at codesourcery dot com>
- To: <binutils at sourceware dot org>
- Cc: Richard Sandiford <rdsandiford at googlemail dot com>
- Date: Fri, 8 Nov 2013 01:03:31 +0000
- Subject: [PATCH] MIPS/opcodes: Add MFCR and MTCR data dependencies
- Authentication-results: sourceware.org; auth=none
Hi,
I've noticed we lack a data dependency for the other operand of the MFCR
and MTCR NetLogic-processor-specific instructions. These instructions
access a control register whose number is (indirectly) specified by the
contents of a GPR referred to as the second assembly instruction operand
or the `rs' operand field of the instruction word. Therefore the GPR is a
read data dependency of these instructions. The change below records it
in `pinfo' information.
No regressions in mips-linux-gnu testing (we should probably review
branch swapping tests to add instructions that are not covered there
already though). OK to apply?
2013-11-08 Maciej W. Rozycki <macro@codesourcery.com>
opcodes/
* mips-opc.c (mips_builtin_opcode): Add RD_2 to "mfcr" and
"mtcr".
Maciej
binutils-mips-opc-netlogic-cr.diff
Index: binutils-fsf-trunk-quilt/opcodes/mips-opc.c
===================================================================
--- binutils-fsf-trunk-quilt.orig/opcodes/mips-opc.c 2013-08-22 17:59:36.000000000 +0100
+++ binutils-fsf-trunk-quilt/opcodes/mips-opc.c 2013-11-07 22:20:55.887967321 +0000
@@ -1288,7 +1288,7 @@ const struct mips_opcode mips_builtin_op
{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
{"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR, 0, 0 },
+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 },
{"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
{"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
@@ -1381,7 +1381,7 @@ const struct mips_opcode mips_builtin_op
{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
{"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR, 0, 0 },
+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 },
{"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
{"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
{"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },