Index: gas/config/rx-defs.h =================================================================== RCS file: /cvs/cvsfiles/devo/gas/config/rx-defs.h,v retrieving revision 1.12 diff -u -3 -p -r1.12 rx-defs.h --- gas/config/rx-defs.h 20 Nov 2011 20:27:29 -0000 1.12 +++ gas/config/rx-defs.h 23 Jan 2013 11:37:43 -0000 @@ -34,8 +34,16 @@ #define RX_RELAX_IMM 2 #define RX_RELAX_DISP 3 +enum rx_cpu_types +{ + RX600, + RX610, + RX200 +}; + extern int rx_pid_register; extern int rx_gp_register; +extern enum rx_cpu_types rx_cpu; extern int rx_error (const char *); extern void rx_lex_init (char *, char *); Index: gas/config/rx-parse.y =================================================================== RCS file: /cvs/cvsfiles/devo/gas/config/rx-parse.y,v retrieving revision 1.34 diff -u -3 -p -r1.34 rx-parse.y --- gas/config/rx-parse.y 20 May 2012 16:36:13 -0000 1.34 +++ gas/config/rx-parse.y 23 Jan 2013 11:37:43 -0000 @@ -104,6 +104,7 @@ static int sizemap[] = { BSIZE, WSIZE, L #define id24(a,b2,b3) B3 (0xfb+a, b2, b3) +static void rx_check_float_support (void); static int rx_intop (expressionS, int, int); static int rx_uintop (expressionS, int); static int rx_disp3op (expressionS); @@ -884,14 +885,14 @@ op_shift float2_op : '#' EXPR ',' REG - { id24 (2, 0x72, sub_op << 4); F ($4, 20, 4); O4 ($2); } + { rx_check_float_support (); id24 (2, 0x72, sub_op << 4); F ($4, 20, 4); O4 ($2); } | float2_op_ni ; float2_op_ni : REG ',' REG - { id24 (1, 0x83 + (sub_op << 2), 0); F ($1, 16, 4); F ($3, 20, 4); } + { rx_check_float_support (); id24 (1, 0x83 + (sub_op << 2), 0); F ($1, 16, 4); F ($3, 20, 4); } | disp '[' REG ']' opt_l ',' REG - { id24 (1, 0x80 + (sub_op << 2), 0); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, LSIZE); } + { rx_check_float_support (); id24 (1, 0x80 + (sub_op << 2), 0); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, LSIZE); } ; /* ====================================================================== */ @@ -1629,3 +1630,10 @@ rx_range (expressionS exp, int minv, int if (val < minv || val > maxv) as_warn (_("Value %d out of range %d..%d"), val, minv, maxv); } + +static void +rx_check_float_support (void) +{ + if (rx_cpu == RX200) + rx_error (_("target CPU type does not support floating point instructions")); +} Index: gas/config/tc-rx.c =================================================================== RCS file: /cvs/cvsfiles/devo/gas/config/tc-rx.c,v retrieving revision 1.54 diff -u -3 -p -r1.54 tc-rx.c --- gas/config/tc-rx.c 18 Nov 2012 19:46:09 -0000 1.54 +++ gas/config/tc-rx.c 23 Jan 2013 11:37:44 -0000 @@ -56,6 +56,8 @@ static int rx_num_int_regs = 0; int rx_pid_register; int rx_gp_register; +enum rx_cpu_types rx_cpu = RX600; + static void rx_fetchalign (int ignore ATTRIBUTE_UNUSED); enum options @@ -72,6 +74,7 @@ enum options OPTION_INT_REGS, OPTION_USES_GCC_ABI, OPTION_USES_RX_ABI, + OPTION_CPU, }; #define RX_SHORTOPTS "" @@ -98,6 +101,7 @@ struct option md_longopts[] = {"mint-register", required_argument, NULL, OPTION_INT_REGS}, {"mgcc-abi", no_argument, NULL, OPTION_USES_GCC_ABI}, {"mrx-abi", no_argument, NULL, OPTION_USES_RX_ABI}, + {"mcpu",required_argument,NULL,OPTION_CPU}, {NULL, no_argument, NULL, 0} }; size_t md_longopts_size = sizeof (md_longopts); @@ -155,6 +159,20 @@ md_parse_option (int c ATTRIBUTE_UNUSED, case OPTION_USES_RX_ABI: elf_flags |= E_FLAG_RX_ABI; return 1; + + case OPTION_CPU: + if (strcasecmp (arg, "rx200") == 0) + rx_cpu = RX200; + else if (strcasecmp (arg, "rx600") == 0) + rx_cpu = RX600; + else if (strcasecmp (arg, "rx610") == 0) + rx_cpu = RX610; + else + { + as_warn (_("unrecognised RX CPU type %s"), arg); + break; + } + return 1; } return 0; } Index: gas/doc/c-rx.texi =================================================================== RCS file: /cvs/cvsfiles/devo/gas/doc/c-rx.texi,v retrieving revision 1.10 diff -u -3 -p -r1.10 c-rx.texi --- gas/doc/c-rx.texi 13 Nov 2012 12:33:54 -0000 1.10 +++ gas/doc/c-rx.texi 23 Jan 2013 11:37:44 -0000 @@ -106,6 +106,13 @@ by the assembled code. With this versio arguments that are passed on the stack are aligned to their natural alignments. This option is the default. +@cindex @samp{-mcpu=} +@item -mcpu=@var{name} +This option tells the assembler the target CPU type. Currently the +@code{rx200}, @code{rx600} and @code{rx610} are recognised as valid +cpu names. Attempting to assemble an instruction not supported by the +indicated cpu type will result in an error message being generated. + @end table @node RX-Modifiers Index: gcc/config/rx/rx.h =================================================================== RCS file: /cvs/cvsfiles/devo/gcc/config/rx/rx.h,v retrieving revision 1.99 diff -u -3 -p -r1.99 rx.h --- gcc/config/rx/rx.h 18 Nov 2012 22:25:46 -0000 1.99 +++ gcc/config/rx/rx.h 23 Jan 2013 11:37:47 -0000 @@ -85,7 +85,8 @@ %{mpid} \ %{mint-register=*} \ %{mgcc-abi:-mgcc-abi} %{!mgcc-abi:-mrx-abi} \ +%{mcpu=*} \ " #undef LIB_SPEC