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[PATCH] Full POWER8 binutils support
- From: Peter Bergner <bergner at vnet dot ibm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Alan Modra <amodra at gmail dot com>
- Date: Mon, 20 May 2013 19:18:38 -0500
- Subject: [PATCH] Full POWER8 binutils support
On May 10th, the Power Architecture Advisory Council announced the
public availability of Power ISA 2.07:
https://www.power.org/documentation/power-isa-version-2-07/
With this announcement, we (IBM) are now ready to submit the full
POWER8 binuitls support with the patch below.
This has passed bootstrap and make check. Ok for mainline?
Peter
opcodes/
* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
XLS_MASK, PPCVSX2): New defines.
(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
<lxvx, stxvx>: New extended mnemonics.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error
and clean up warning when using PRINT_OPCODE_TABLE.
gas/testsuite/
* gas/ppc/altivec2.d <bcdadd., bcdadd., vaddcuq, vaddecuq, vaddeuqm,
vaddudm, vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh,
vclzw, vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud.,
veqv, vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw,
vmuleuw, vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast,
vorc, vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd,
vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm,
vsubudm, vsubuqm, vupkhsw, vupklsw>: Add new tests.
* gas/ppc/altivec2.s: Likewise.
* gas/ppc/power8.d <bcdadd., bcdsub., bctar, bctarl, clrbhrb, fmrgew,
fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe, mfvsrd, mfvsrwz,
msgclrp, msgsndp, mtsle, mtvsrd, mtvsrwa, mtvsrwz, pbt., rfebb,
stqcx., stxsiwx, stxsspx, vaddcuq, vaddecuq, vaddeuqm, vaddudm,
vadduqm, vbpermq, vcipher, vcipherlast, vclzb, vclzd, vclzh, vclzw,
vcmpequd, vcmpequd., vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv,
vgbbd, vmaxsd, vmaxud, vminsd, vminud, vmrgow, vmulesw, vmuleuw,
vmulosw, vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc,
vpermxor, vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd,
vpmsumh, vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq, vsubeuqm,
vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp, xscvdpspn, xscvspdpn,
xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp, xsmaddmsp, xsmsubasp,
xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp, xsnmsubasp, xsnmsubmsp,
xsresp, xsrsp, xsrsqrtesp, xssqrtsp, xssubsp, xxleqv, xxlnand,
xxlorc>: Add new tests.
* gas/ppc/power8.s Likewise.
* gas/ppc/vsx.d <lxvd2x, stxvd2x>: Add new tests.
* gas/ppc/vsx.s Likewise.
* gas/ppc/vsx2.d: New test file.
* gas/ppc/vsx2.s: Likewise.
* gas/ppc/ppc.exp: Run it.
Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.62
diff -u -p -r1.62 ppc-dis.c
--- opcodes/ppc-dis.c 11 Jan 2013 02:25:36 -0000 1.62
+++ opcodes/ppc-dis.c 20 May 2013 23:50:59 -0000
@@ -315,10 +315,7 @@ powerpc_init_dialect (struct disassemble
dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE);
break;
default:
- dialect = (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
- | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
- | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
- | PPC_OPCODE_ANY);
+ dialect = ppc_parse_cpu (dialect, &sticky, "power8") | PPC_OPCODE_ANY;
}
arg = info->disassembler_options;
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.159
diff -u -p -r1.159 ppc-opc.c
--- opcodes/ppc-opc.c 9 May 2013 04:32:55 -0000 1.159
+++ opcodes/ppc-opc.c 20 May 2013 23:50:59 -0000
@@ -315,14 +315,18 @@ const struct powerpc_operand powerpc_ope
{ 0xfffc, 0, NULL, NULL,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
- /* The DUIS field in a XFX form instruction, 10 bits unsigned imediate */
+ /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
+ unsigned imediate */
#define DUIS DS + 1
+#define BHRBE DUIS
{ 0x3ff, 11, NULL, NULL, 0 },
/* The E field in a wrteei instruction. */
/* And the W bit in the pair singles instructions. */
+ /* And the ST field in a VX form instruction. */
#define E DUIS + 1
#define PSW E
+#define ST E
{ 0x1, 15, NULL, NULL, 0 },
/* The FL1 field in a POWER SC form instruction. */
@@ -695,8 +699,16 @@ const struct powerpc_operand powerpc_ope
#define UIMM3 UIMM + 1
{ 0x7, 16, NULL, NULL, 0 },
+ /* The SIX field in a VX form instruction. */
+#define SIX UIMM3 + 1
+ { 0xf, 11, NULL, NULL, 0 },
+
+ /* The PS field in a VX form instruction. */
+#define PS SIX + 1
+ { 0x1, 9, NULL, NULL, 0 },
+
/* The SHB field in a VA form instruction. */
-#define SHB UIMM3 + 1
+#define SHB PS + 1
{ 0xf, 6, NULL, NULL, 0 },
/* The other UIMM field in a half word EVX form instruction. */
@@ -751,8 +763,12 @@ const struct powerpc_operand powerpc_ope
#define S SP + 1
{ 0x1, 20, NULL, NULL, 0 },
+ /* The S field in a XL form instruction. */
+#define SXL S + 1
+ { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
/* SH field starting at bit position 16. */
-#define SH16 S + 1
+#define SH16 SXL + 1
/* The DCM and DGM fields in a Z form instruction. */
#define DCM SH16
#define DGM DCM
@@ -2325,6 +2341,9 @@ extract_vleil (unsigned long insn,
/* A VX_MASK with a UIMM2 field. */
#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
+/* A VX_MASK with a PS field. */
+#define VXPS_MASK (VX_MASK & ~(0x1 << 9))
+
/* A VA form instruction. */
#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
@@ -2379,6 +2398,9 @@ extract_vleil (unsigned long insn,
/* The mask for an XX1 form instruction. */
#define XX1_MASK X (0x3f, 0x3ff)
+/* An XX1_MASK with the RB field fixed. */
+#define XX1RB_MASK (XX1_MASK | RB_MASK)
+
/* The mask for an XX2 form instruction. */
#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
@@ -2516,6 +2538,9 @@ extract_vleil (unsigned long insn,
/* The mask for an XL form instruction. */
#define XL_MASK XLLK (0x3f, 0x3ff, 1)
+/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
+#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
+
/* An XL form instruction which explicitly sets the BO field. */
#define XLO(op, bo, xop, lk) \
(XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
@@ -2699,6 +2724,7 @@ extract_vleil (unsigned long insn,
#define PPCVEC PPC_OPCODE_ALTIVEC
#define PPCVEC2 PPC_OPCODE_ALTIVEC2
#define PPCVSX PPC_OPCODE_VSX
+#define PPCVSX2 PPC_OPCODE_VSX
#define POWER PPC_OPCODE_POWER
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
@@ -2845,6 +2871,7 @@ const struct powerpc_opcode powerpc_opco
{"vperm", VXA(4, 43), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, SHB}},
{"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
+{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}},
{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}},
@@ -2863,6 +2890,10 @@ const struct powerpc_opcode powerpc_opco
{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}},
{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
+{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
+{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}},
{"vadduhm", VX (4, 64), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vrlh", VX (4, 68), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
@@ -2886,6 +2917,8 @@ const struct powerpc_opcode powerpc_opco
{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vrlw", VX (4, 132), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vmrghw", VX (4, 140), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}},
@@ -2893,12 +2926,17 @@ const struct powerpc_opcode powerpc_opco
{"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
+{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+{"vrld", VX (4, 196), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"machhws", XO (4, 108,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"machhws.", XO (4, 108,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vslb", VX (4, 260), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vmulosb", VX (4, 264), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
@@ -2911,6 +2949,7 @@ const struct powerpc_opcode powerpc_opco
{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"macchwu", XO (4, 140,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vslh", VX (4, 324), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vmulosh", VX (4, 328), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
@@ -2926,11 +2965,13 @@ const struct powerpc_opcode powerpc_opco
{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vslw", VX (4, 388), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
{"vmrglw", VX (4, 396), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vpkshss", VX (4, 398), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"macchwsu", XO (4, 204,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vsl", VX (4, 452), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
@@ -3014,6 +3055,7 @@ const struct powerpc_opcode powerpc_opco
{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"evfsneg", VX (4, 646), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evfsmul", VX (4, 648), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
@@ -3039,11 +3081,13 @@ const struct powerpc_opcode powerpc_opco
{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}},
{"efsadd", VX (4, 704), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
{"efssub", VX (4, 705), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vminud", VX (4, 706), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"efsabs", VX (4, 708), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
{"vsr", VX (4, 708), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"efsnabs", VX (4, 709), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
{"efsneg", VX (4, 710), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}},
{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"efsmul", VX (4, 712), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
{"efsdiv", VX (4, 713), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
@@ -3163,12 +3207,16 @@ const struct powerpc_opcode powerpc_opco
{"vminsw", VX (4, 898), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vsraw", VX (4, 900), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vctuxs", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}},
{"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}},
{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}},
@@ -3177,6 +3225,7 @@ const struct powerpc_opcode powerpc_opco
{"nmaclhws", XO (4, 494,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"nmaclhws.", XO (4, 494,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"vsububm", VX (4,1024), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, PS}},
{"vavgub", VX (4,1026), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmhessf", VX (4,1027), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
@@ -3185,6 +3234,7 @@ const struct powerpc_opcode powerpc_opco
{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"evmhossf", VX (4,1031), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmheumi", VX (4,1032), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
@@ -3206,6 +3256,7 @@ const struct powerpc_opcode powerpc_opco
{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, PS}},
{"vavguh", VX (4,1090), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vandc", VX (4,1092), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
@@ -3213,11 +3264,13 @@ const struct powerpc_opcode powerpc_opco
{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vminfp", VX (4,1098), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vsro", VX (4,1100), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmwssf", VX (4,1107), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"machhwo", XO (4, 44,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
@@ -3243,6 +3296,7 @@ const struct powerpc_opcode powerpc_opco
{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vmr", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}},
{"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
@@ -3250,6 +3304,7 @@ const struct powerpc_opcode powerpc_opco
{"machhwsuo.", XO (4, 76,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
@@ -3259,18 +3314,22 @@ const struct powerpc_opcode powerpc_opco
{"evdivws", VX (4,1222), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"evdivwu", VX (4,1223), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}},
+{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"machhwso", XO (4, 108,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"machhwso.", XO (4, 108,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"nmachhwso", XO (4, 110,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"nmachhwso.", XO (4, 110,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
+{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vavgsb", VX (4,1282), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
@@ -3283,8 +3342,11 @@ const struct powerpc_opcode powerpc_opco
{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
@@ -3296,13 +3358,19 @@ const struct powerpc_opcode powerpc_opco
{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vavgsh", VX (4,1346), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vorc", VX (4,1348), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"macchwo", XO (4, 172,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
@@ -3316,6 +3384,7 @@ const struct powerpc_opcode powerpc_opco
{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vavgsw", VX (4,1410), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vnand", VX (4,1412), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
@@ -3337,11 +3406,14 @@ const struct powerpc_opcode powerpc_opco
{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vsld", VX (4,1476), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
+{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, PPCNONE, {VD, VA}},
{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
+{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"macchwso", XO (4, 236,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"evmwumian", VX (4,1496), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
@@ -3362,15 +3434,25 @@ const struct powerpc_opcode powerpc_opco
{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
{"vsubuws", VX (4,1664), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, ST, SIX}},
+{"veqv", VX (4,1668), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
+{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, ST, SIX}},
+{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
@@ -3378,6 +3460,8 @@ const struct powerpc_opcode powerpc_opco
{"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"vsubshs", VX (4,1856), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
@@ -3386,14 +3470,20 @@ const struct powerpc_opcode powerpc_opco
{"nmaclhwo", XO (4, 430,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"vsubsws", VX (4,1920), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
{"vsumsws", VX (4,1928), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
+{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
+{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}},
{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}},
{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
+{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
{"maclhwso", XO (4, 492,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
{"maclhwso.", XO (4, 492,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
@@ -3965,6 +4055,8 @@ const struct powerpc_opcode powerpc_opco
{"crandc", XL(19,129), XL_MASK, COM, PPCNONE, {BT, BA, BB}},
+{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCNONE, {SXL}},
+
{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCNONE, {0}},
{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCNONE, {0}},
@@ -4148,6 +4240,13 @@ const struct powerpc_opcode powerpc_opco
{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCNONE, {BO, BI, BH}},
{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCNONE, {BO, BI}},
+{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCNONE, {BOE, BI}},
+{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCNONE, {BOE, BI}},
+{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCNONE, {BOE, BI}},
+{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCNONE, {BOE, BI}},
+{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCNONE, {BO, BI, BH}},
+{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCNONE, {BO, BI, BH}},
+
{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
{"rlimi", M(20,0), M_MASK, PWRCOM, PPCNONE, {RA, RS, SH, MBE, ME}},
@@ -4276,6 +4375,8 @@ const struct powerpc_opcode powerpc_opco
{"mulhwu", XO(31,11,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
+{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, PPCNONE, {XT6, RA0, RB}},
+
{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, PPCNONE, {0}},
@@ -4316,6 +4417,9 @@ const struct powerpc_opcode powerpc_opco
{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
{"ldepx", X(31,29), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
+
+{"waitasec", X(31,30), XRTRARB_MASK,POWER8, PPCNONE, {0}},
+
{"lwepx", X(31,31), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}},
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM|PPCVLE, PPCNONE, {OBF, RA, RB}},
@@ -4335,6 +4439,8 @@ const struct powerpc_opcode powerpc_opco
{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, PPCNONE, {RT, RA, RB}},
+{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, PPCNONE, {XT6, RA0, RB}},
+
{"iseleq", X(31,79), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN|PPCVLE, PPCNONE, {RT, RA0, RB, CRB}},
@@ -4344,6 +4450,9 @@ const struct powerpc_opcode powerpc_opco
{"subf.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"sub.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}},
+{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}},
+{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, FRS}},
+{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
{"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}},
{"lbarx", X(31,52), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
@@ -4421,6 +4530,10 @@ const struct powerpc_opcode powerpc_opco
{"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
+{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, FRS}},
+{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {RA, VS}},
+{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, PPCNONE, {RA, XS6}},
+
{"lharx", X(31,116), XEH_MASK, POWER7|PPCVLE, PPCNONE, {RT, RA0, RB, EH}},
{"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}},
@@ -4453,6 +4566,9 @@ const struct powerpc_opcode powerpc_opco
{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, PPCNONE, {XS6, RA0, RB}},
+
+{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, PPCNONE, {RB}},
{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
@@ -4461,6 +4577,8 @@ const struct powerpc_opcode powerpc_opco
{"mtmsr", X(31,146), XRLARB_MASK, COM|PPCVLE, PPCNONE, {RS, A_L}},
+{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, PPCNONE, {L}},
+
{"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
@@ -4490,14 +4608,19 @@ const struct powerpc_opcode powerpc_opco
{"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, PPCNONE, {RB}},
{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}},
+{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, PPCNONE, {XT6, RA}},
+{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, PPCNONE, {FRT, RA}},
+{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {VD, RA}},
{"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}},
{"stdux", X(31,181), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RAS, RB}},
+{"stqcx.", XRC(31,182,1), X_MASK, POWER8, PPCNONE, {RSQ, RA0, RB}},
{"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}},
{"stwux", X(31,183), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RAS, RB}},
@@ -4527,6 +4650,9 @@ const struct powerpc_opcode powerpc_opco
{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
+{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, PPCNONE, {FRT, RA}},
+{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {VD, RA}},
+{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, PPCNONE, {XT6, RA}},
{"eratwe", X(31,211), X_MASK, PPCA2, PPCNONE, {RS, RA, WS}},
{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}},
@@ -4571,6 +4697,10 @@ const struct powerpc_opcode powerpc_opco
{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
+{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, PPCNONE, {FRT, RA}},
+{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, PPCNONE, {VD, RA}},
+{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, PPCNONE, {XT6, RA}},
+
{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA0, RB}},
{"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA0, RB, CT}},
{"dcbtst", X(31,246), X_MASK, PPC|PPCVLE, POWER4, {CT, RA0, RB}},
@@ -4608,6 +4738,8 @@ const struct powerpc_opcode powerpc_opco
{"mfapidi", X(31,275), X_MASK, BOOKE, TITAN, {RT, RA}},
+{"lqarx", X(31,276), XEH_MASK, POWER8, PPCNONE, {RTQ, RAX, RBX, EH}},
+
{"lscbx", XRC(31,277,0), X_MASK, M601, PPCNONE, {RT, RA, RB}},
{"lscbx.", XRC(31,277,1), X_MASK, M601, PPCNONE, {RT, RA, RB}},
@@ -4629,6 +4761,8 @@ const struct powerpc_opcode powerpc_opco
{"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}},
{"lvepx", X(31,295), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}},
+{"mfbhrbe", X(31,302), X_MASK, POWER8, PPCNONE, {RT, BHRBE}},
+
{"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}},
{"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}},
@@ -4937,6 +5071,8 @@ const struct powerpc_opcode powerpc_opco
{"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}},
+{"pbt.", XRC(31,404,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}},
+
{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}},
@@ -4958,6 +5094,8 @@ const struct powerpc_opcode powerpc_opco
{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}},
+{"clrbhrb", X(31,430), 0xffffffff, POWER8, PPCNONE, {0}},
+
{"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}},
{"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA0, RB}},
@@ -5246,6 +5384,8 @@ const struct powerpc_opcode powerpc_opco
{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
+{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, PPCNONE, {XT6, RA0, RB}},
+
{"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}},
{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}},
@@ -5340,6 +5480,8 @@ const struct powerpc_opcode powerpc_opco
{"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}},
{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
+{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, PPCNONE, {XS6, RA0, RB}},
+
{"tbegin.", XRC(31,654,1), XRTLRARB_MASK,PPCHTM, PPCNONE, {HTM_R}},
{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
@@ -5525,6 +5667,7 @@ const struct powerpc_opcode powerpc_opco
{"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}},
{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
+{"lxvx", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}},
{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}},
@@ -5636,6 +5779,7 @@ const struct powerpc_opcode powerpc_opco
{"divwuo.", XO(31,459,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}},
{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
+{"stxvx", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}},
{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}},
@@ -5868,14 +6012,25 @@ const struct powerpc_opcode powerpc_opco
{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
+{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}},
{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}},
{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}},
+{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
+{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
@@ -5929,14 +6084,18 @@ const struct powerpc_opcode powerpc_opco
{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}},
+{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
@@ -5949,12 +6108,15 @@ const struct powerpc_opcode powerpc_opco
{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}},
+{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
+{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}},
{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
@@ -5985,8 +6147,13 @@ const struct powerpc_opcode powerpc_opco
{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}},
{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
+{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
+{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}},
{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
@@ -6222,6 +6389,8 @@ const struct powerpc_opcode powerpc_opco
{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}},
+{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCNONE, {FRT, FRA, FRB}},
+
{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}},
{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}},
@@ -6236,6 +6405,8 @@ const struct powerpc_opcode powerpc_opco
{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
+{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCNONE, {FRT, FRA, FRB}},
+
{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}},
};
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.199
diff -u -p -r1.199 tc-ppc.c
--- gas/config/tc-ppc.c 20 May 2013 10:16:31 -0000 1.199
+++ gas/config/tc-ppc.c 20 May 2013 23:50:58 -0000
@@ -1526,10 +1526,10 @@ ppc_setup_opcodes (void)
int new_opcode = PPC_OP (op[0].opcode);
#ifdef PRINT_OPCODE_TABLE
- printf ("%-14s\t#%04d\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n",
- op->name, op - powerpc_opcodes, (unsigned int) new_opcode,
- (unsigned int) op->opcode, (unsigned int) op->mask,
- (unsigned long long) op->flags);
+ printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n",
+ op->name, (unsigned int) (op - powerpc_opcodes),
+ (unsigned int) new_opcode, (unsigned int) op->opcode,
+ (unsigned int) op->mask, (unsigned long long) op->flags);
#endif
/* The major opcodes had better be sorted. Code in the
@@ -1579,10 +1579,10 @@ ppc_setup_opcodes (void)
new_seg = VLE_OP_TO_SEG (new_seg);
#ifdef PRINT_OPCODE_TABLE
- printf ("%-14s\t#%04d\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n",
- op->name, op - powerpc_opcodes, (unsigned int) new_opcode,
- (unsigned int) op->opcode, (unsigned int) op->mask,
- (unsigned long long) op->flags);
+ printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%x\tmask: 0x%x\tflags: 0x%llx\n",
+ op->name, (unsigned int) (op - powerpc_opcodes),
+ (unsigned int) new_seg, (unsigned int) op->opcode,
+ (unsigned int) op->mask, (unsigned long long) op->flags);
#endif
/* The major opcodes had better be sorted. Code in the
disassembler assumes the insns are sorted according to
Index: gas/testsuite/gas/ppc/altivec2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/altivec2.d,v
retrieving revision 1.2
diff -u -p -r1.2 altivec2.d
--- gas/testsuite/gas/ppc/altivec2.d 29 Oct 2012 09:25:15 -0000 1.2
+++ gas/testsuite/gas/ppc/altivec2.d 20 May 2013 23:50:58 -0000
@@ -58,4 +58,68 @@ Disassembly of section \.text:
c0: (10 d1 84 03|03 84 d1 10) vabsdub v6,v17,v16
c4: (12 b2 24 43|43 24 b2 12) vabsduh v21,v18,v4
c8: (13 34 4c 83|83 4c 34 13) vabsduw v25,v20,v9
+ cc: (10 d1 a6 ad|ad a6 d1 10) vpermxor v6,v17,v20,v26
+ d0: (13 ba 7f 3c|3c 7f ba 13) vaddeuqm v29,v26,v15,v28
+ d4: (11 e8 3e 3d|3d 3e e8 11) vaddecuq v15,v8,v7,v24
+ d8: (10 46 a8 7e|7e a8 46 10) vsubeuqm v2,v6,v21,v1
+ dc: (13 a6 01 3f|3f 01 a6 13) vsubecuq v29,v6,v0,v4
+ e0: (11 c9 18 88|88 18 c9 11) vmulouw v14,v9,v3
+ e4: (13 10 90 89|89 90 10 13) vmuluwm v24,v16,v18
+ e8: (11 51 88 c0|c0 88 51 11) vaddudm v10,v17,v17
+ ec: (13 d9 20 c2|c2 20 d9 13) vmaxud v30,v25,v4
+ f0: (11 46 e0 c4|c4 e0 46 11) vrld v10,v6,v28
+ f4: (13 67 38 c7|c7 38 67 13) vcmpequd v27,v7,v7
+ f8: (12 d0 c9 00|00 c9 d0 12) vadduqm v22,v16,v25
+ fc: (10 35 e9 40|40 e9 35 10) vaddcuq v1,v21,v29
+ 100: (12 8b 99 88|88 99 8b 12) vmulosw v20,v11,v19
+ 104: (13 13 09 c2|c2 09 13 13) vmaxsd v24,v19,v1
+ 108: (11 bb f2 88|88 f2 bb 11) vmuleuw v13,v27,v30
+ 10c: (11 38 8a c2|c2 8a 38 11) vminud v9,v24,v17
+ 110: (11 52 e2 c7|c7 e2 52 11) vcmpgtud v10,v18,v28
+ 114: (10 1d b3 88|88 b3 1d 10) vmulesw v0,v29,v22
+ 118: (11 bc 0b c2|c2 0b bc 11) vminsd v13,v28,v1
+ 11c: (11 54 2b c4|c4 2b 54 11) vsrad v10,v20,v5
+ 120: (13 75 2b c7|c7 2b 75 13) vcmpgtsd v27,v21,v5
+ 124: (10 17 f6 01|01 f6 17 10) bcdadd\. v0,v23,v30,1
+ 128: (13 38 d4 08|08 d4 38 13) vpmsumb v25,v24,v26
+ 12c: (11 04 26 41|41 26 04 11) bcdsub\. v8,v4,v4,1
+ 130: (12 0e d4 48|48 d4 0e 12) vpmsumh v16,v14,v26
+ 134: (13 62 d4 4e|4e d4 62 13) vpkudum v27,v2,v26
+ 138: (10 d7 8c 88|88 8c d7 10) vpmsumw v6,v23,v17
+ 13c: (12 86 cc c8|c8 cc 86 12) vpmsumd v20,v6,v25
+ 140: (13 76 84 ce|ce 84 76 13) vpkudus v27,v22,v16
+ 144: (12 b4 94 c0|c0 94 b4 12) vsubudm v21,v20,v18
+ 148: (12 b4 95 00|00 95 b4 12) vsubuqm v21,v20,v18
+ 14c: (13 bd 35 08|08 35 bd 13) vcipher v29,v29,v6
+ 150: (10 4d a5 09|09 a5 4d 10) vcipherlast v2,v13,v20
+ 154: (12 80 95 0c|0c 95 80 12) vgbbd v20,v18
+ 158: (12 68 cd 40|40 cd 68 12) vsubcuq v19,v8,v25
+ 15c: (11 3a ed 44|44 ed 3a 11) vorc v9,v26,v29
+ 160: (12 94 6d 48|48 6d 94 12) vncipher v20,v20,v13
+ 164: (11 e5 dd 49|49 dd e5 11) vncipherlast v15,v5,v27
+ 168: (10 73 35 4c|4c 35 73 10) vbpermq v3,v19,v6
+ 16c: (13 c4 e5 4e|4e e5 c4 13) vpksdus v30,v4,v28
+ 170: (10 04 75 84|84 75 04 10) vnand v0,v4,v14
+ 174: (12 28 ed c4|c4 ed 28 12) vsld v17,v8,v29
+ 178: (13 b4 05 c8|c8 05 b4 13) vsbox v29,v20
+ 17c: (11 67 5d ce|ce 5d 67 11) vpksdss v11,v7,v11
+ 180: (10 73 84 c7|c7 84 73 10) vcmpequd\. v3,v19,v16
+ 184: (12 40 8e 4e|4e 8e 40 12) vupkhsw v18,v17
+ 188: (13 a8 6e 82|82 6e a8 13) vshasigmaw v29,v8,0,13
+ 18c: (12 fc d6 84|84 d6 fc 12) veqv v23,v28,v26
+ 190: (13 a0 17 8c|8c 17 a0 13) vmrgew v29,v0,v2
+ 194: (13 a0 16 8c|8c 16 a0 13) vmrgow v29,v0,v2
+ 198: (13 73 06 c2|c2 06 73 13) vshasigmad v27,v19,0,0
+ 19c: (12 9c e6 c4|c4 e6 9c 12) vsrd v20,v28,v28
+ 1a0: (12 40 ae ce|ce ae 40 12) vupklsw v18,v21
+ 1a4: (13 c0 3f 02|02 3f c0 13) vclzb v30,v7
+ 1a8: (13 a0 af 03|03 af a0 13) vpopcntb v29,v21
+ 1ac: (13 20 af 42|42 af 20 13) vclzh v25,v21
+ 1b0: (12 00 f7 43|43 f7 00 12) vpopcnth v16,v30
+ 1b4: (13 80 1f 82|82 1f 80 13) vclzw v28,v3
+ 1b8: (11 40 4f 83|83 4f 40 11) vpopcntw v10,v9
+ 1bc: (12 c0 4f c2|c2 4f c0 12) vclzd v22,v9
+ 1c0: (11 e0 f7 c3|c3 f7 e0 11) vpopcntd v15,v30
+ 1c4: (10 5f 36 c7|c7 36 5f 10) vcmpgtud\. v2,v31,v6
+ 1c8: (12 8f 17 c7|c7 17 8f 12) vcmpgtsd\. v20,v15,v2
#pass
Index: gas/testsuite/gas/ppc/altivec2.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/altivec2.s,v
retrieving revision 1.1
diff -u -p -r1.1 altivec2.s
--- gas/testsuite/gas/ppc/altivec2.s 5 Oct 2012 14:06:18 -0000 1.1
+++ gas/testsuite/gas/ppc/altivec2.s 20 May 2013 23:50:58 -0000
@@ -1,3 +1,4 @@
+ .text
start:
lvepxl 3,0,28
lvepxl 19,4,18
@@ -50,3 +51,67 @@ start:
vabsdub 6,17,16
vabsduh 21,18,4
vabsduw 25,20,9
+ vpermxor 6,17,20,26
+ vaddeuqm 29,26,15,28
+ vaddecuq 15,8,7,24
+ vsubeuqm 2,6,21,1
+ vsubecuq 29,6,0,4
+ vmulouw 14,9,3
+ vmuluwm 24,16,18
+ vaddudm 10,17,17
+ vmaxud 30,25,4
+ vrld 10,6,28
+ vcmpequd 27,7,7
+ vadduqm 22,16,25
+ vaddcuq 1,21,29
+ vmulosw 20,11,19
+ vmaxsd 24,19,1
+ vmuleuw 13,27,30
+ vminud 9,24,17
+ vcmpgtud 10,18,28
+ vmulesw 0,29,22
+ vminsd 13,28,1
+ vsrad 10,20,5
+ vcmpgtsd 27,21,5
+ bcdadd. 0,23,30,1
+ vpmsumb 25,24,26
+ bcdsub. 8,4,4,1
+ vpmsumh 16,14,26
+ vpkudum 27,2,26
+ vpmsumw 6,23,17
+ vpmsumd 20,6,25
+ vpkudus 27,22,16
+ vsubudm 21,20,18
+ vsubuqm 21,20,18
+ vcipher 29,29,6
+ vcipherlast 2,13,20
+ vgbbd 20,18
+ vsubcuq 19,8,25
+ vorc 9,26,29
+ vncipher 20,20,13
+ vncipherlast 15,5,27
+ vbpermq 3,19,6
+ vpksdus 30,4,28
+ vnand 0,4,14
+ vsld 17,8,29
+ vsbox 29,20
+ vpksdss 11,7,11
+ vcmpequd. 3,19,16
+ vupkhsw 18,17
+ vshasigmaw 29,8,0,13
+ veqv 23,28,26
+ vmrgew 29,0,2
+ vmrgow 29,0,2
+ vshasigmad 27,19,0,0
+ vsrd 20,28,28
+ vupklsw 18,21
+ vclzb 30,7
+ vpopcntb 29,21
+ vclzh 25,21
+ vpopcnth 16,30
+ vclzw 28,3
+ vpopcntw 10,9
+ vclzd 22,9
+ vpopcntd 15,30
+ vcmpgtud. 2,31,6
+ vcmpgtsd. 20,15,2
Index: gas/testsuite/gas/ppc/power8.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/power8.d,v
retrieving revision 1.2
diff -u -p -r1.2 power8.d
--- gas/testsuite/gas/ppc/power8.d 14 Jan 2013 06:42:00 -0000 1.2
+++ gas/testsuite/gas/ppc/power8.d 20 May 2013 23:50:58 -0000
@@ -27,3 +27,127 @@ Disassembly of section \.text:
44: (60 42 00 00|00 00 42 60) ori r2,r2,0
48: (60 00 00 00|00 00 00 60) nop
4c: (60 42 00 00|00 00 42 60) ori r2,r2,0
+ 50: (4c 00 01 24|24 01 00 4c) rfebb
+ 54: (4c 00 01 24|24 01 00 4c) rfebb
+ 58: (4c 00 09 24|24 09 00 4c) rfebb 1
+ 5c: (4d 95 04 60|60 04 95 4d) bctar- 12,4\*cr5\+gt
+ 60: (4c 87 04 61|61 04 87 4c) bctarl- 4,4\*cr1\+so
+ 64: (4d ac 04 60|60 04 ac 4d) bctar\+ 12,4\*cr3\+lt
+ 68: (4c a2 04 61|61 04 a2 4c) bctarl\+ 4,eq
+ 6c: (4c 88 0c 60|60 0c 88 4c) bctar 4,4\*cr2\+lt,1
+ 70: (4c 87 14 61|61 14 87 4c) bctarl 4,4\*cr1\+so,2
+ 74: (7c 00 00 3c|3c 00 00 7c) waitasec
+ 78: (7c 00 41 1c|1c 41 00 7c) msgsndp r8
+ 7c: (7c 20 01 26|26 01 20 7c) mtsle 1
+ 80: (7c 00 d9 5c|5c d9 00 7c) msgclrp r27
+ 84: (7d 4a 61 6d|6d 61 4a 7d) stqcx\. r10,r10,r12
+ 88: (7f 80 39 6d|6d 39 80 7f) stqcx\. r28,0,r7
+ 8c: (7f 13 5a 28|28 5a 13 7f) lqarx r24,r19,r11
+ 90: (7e c0 5a 28|28 5a c0 7e) lqarx r22,0,r11
+ 94: (7e 80 32 5c|5c 32 80 7e) mfbhrbe r20,6
+ 98: (7f b1 83 29|29 83 b1 7f) pbt\. r29,r17,r16
+ 9c: (7d c0 3b 29|29 3b c0 7d) pbt\. r14,0,r7
+ a0: (7c 00 03 5c|5c 03 00 7c) clrbhrb
+ a4: (11 6a 05 ed|ed 05 6a 11) vpermxor v11,v10,v0,v23
+ a8: (13 02 39 3c|3c 39 02 13) vaddeuqm v24,v2,v7,v4
+ ac: (11 4a 40 bd|bd 40 4a 11) vaddecuq v10,v10,v8,v2
+ b0: (10 af 44 fe|fe 44 af 10) vsubeuqm v5,v15,v8,v19
+ b4: (11 9f 87 7f|7f 87 9f 11) vsubecuq v12,v31,v16,v29
+ b8: (12 9d 68 88|88 68 9d 12) vmulouw v20,v29,v13
+ bc: (13 a0 d0 89|89 d0 a0 13) vmuluwm v29,v0,v26
+ c0: (11 15 e0 c0|c0 e0 15 11) vaddudm v8,v21,v28
+ c4: (10 3a 08 c2|c2 08 3a 10) vmaxud v1,v26,v1
+ c8: (12 83 08 c4|c4 08 83 12) vrld v20,v3,v1
+ cc: (10 93 58 c7|c7 58 93 10) vcmpequd v4,v19,v11
+ d0: (12 ee f1 00|00 f1 ee 12) vadduqm v23,v14,v30
+ d4: (11 08 69 40|40 69 08 11) vaddcuq v8,v8,v13
+ d8: (13 9b 21 88|88 21 9b 13) vmulosw v28,v27,v4
+ dc: (10 64 21 c2|c2 21 64 10) vmaxsd v3,v4,v4
+ e0: (10 13 aa 88|88 aa 13 10) vmuleuw v0,v19,v21
+ e4: (13 14 9a c2|c2 9a 14 13) vminud v24,v20,v19
+ e8: (10 1c 7a c7|c7 7a 1c 10) vcmpgtud v0,v28,v15
+ ec: (12 a0 13 88|88 13 a0 12) vmulesw v21,v0,v2
+ f0: (11 3a 4b c2|c2 4b 3a 11) vminsd v9,v26,v9
+ f4: (13 3d 5b c4|c4 5b 3d 13) vsrad v25,v29,v11
+ f8: (11 7c 5b c7|c7 5b 7c 11) vcmpgtsd v11,v28,v11
+ fc: (10 a8 d6 01|01 d6 a8 10) bcdadd\. v5,v8,v26,1
+ 100: (10 83 64 08|08 64 83 10) vpmsumb v4,v3,v12
+ 104: (13 5f ae 41|41 ae 5f 13) bcdsub\. v26,v31,v21,1
+ 108: (10 b1 84 48|48 84 b1 10) vpmsumh v5,v17,v16
+ 10c: (12 f1 a4 4e|4e a4 f1 12) vpkudum v23,v17,v20
+ 110: (13 15 ec 88|88 ec 15 13) vpmsumw v24,v21,v29
+ 114: (11 36 6c c8|c8 6c 36 11) vpmsumd v9,v22,v13
+ 118: (12 53 94 ce|ce 94 53 12) vpkudus v18,v19,v18
+ 11c: (13 d0 b5 00|00 b5 d0 13) vsubuqm v30,v16,v22
+ 120: (11 cb 3d 08|08 3d cb 11) vcipher v14,v11,v7
+ 124: (11 42 b5 09|09 b5 42 11) vcipherlast v10,v2,v22
+ 128: (12 e0 6d 0c|0c 6d e0 12) vgbbd v23,v13
+ 12c: (12 19 85 40|40 85 19 12) vsubcuq v16,v25,v16
+ 130: (13 e1 2d 44|44 2d e1 13) vorc v31,v1,v5
+ 134: (10 91 fd 48|48 fd 91 10) vncipher v4,v17,v31
+ 138: (13 02 dd 49|49 dd 02 13) vncipherlast v24,v2,v27
+ 13c: (12 f5 bd 4c|4c bd f5 12) vbpermq v23,v21,v23
+ 140: (13 72 4d 4e|4e 4d 72 13) vpksdus v27,v18,v9
+ 144: (13 7d dd 84|84 dd 7d 13) vnand v27,v29,v27
+ 148: (12 73 c5 c4|c4 c5 73 12) vsld v19,v19,v24
+ 14c: (10 ad 05 c8|c8 05 ad 10) vsbox v5,v13
+ 150: (13 23 3d ce|ce 3d 23 13) vpksdss v25,v3,v7
+ 154: (13 88 04 c7|c7 04 88 13) vcmpequd\. v28,v8,v0
+ 158: (13 40 d6 4e|4e d6 40 13) vupkhsw v26,v26
+ 15c: (10 a7 36 82|82 36 a7 10) vshasigmaw v5,v7,0,6
+ 160: (13 95 76 84|84 76 95 13) veqv v28,v21,v14
+ 164: (10 28 9e 8c|8c 9e 28 10) vmrgow v1,v8,v19
+ 168: (10 0a 56 c2|c2 56 0a 10) vshasigmad v0,v10,0,10
+ 16c: (10 bb 76 c4|c4 76 bb 10) vsrd v5,v27,v14
+ 170: (11 60 6e ce|ce 6e 60 11) vupklsw v11,v13
+ 174: (11 c0 87 02|02 87 c0 11) vclzb v14,v16
+ 178: (12 80 df 03|03 df 80 12) vpopcntb v20,v27
+ 17c: (13 80 5f 42|42 5f 80 13) vclzh v28,v11
+ 180: (13 00 4f 43|43 4f 00 13) vpopcnth v24,v9
+ 184: (13 60 ff 82|82 ff 60 13) vclzw v27,v31
+ 188: (12 20 9f 83|83 9f 20 12) vpopcntw v17,v19
+ 18c: (11 80 ef c2|c2 ef 80 11) vclzd v12,v29
+ 190: (12 e0 b7 c3|c3 b7 e0 12) vpopcntd v23,v22
+ 194: (13 14 ee c7|c7 ee 14 13) vcmpgtud\. v24,v20,v29
+ 198: (11 26 df c7|c7 df 26 11) vcmpgtsd\. v9,v6,v27
+ 19c: (7f ce d0 19|19 d0 ce 7f) lxsiwzx vs62,r14,r26
+ 1a0: (7d 00 c8 19|19 c8 00 7d) lxsiwzx vs40,0,r25
+ 1a4: (7f 20 d0 98|98 d0 20 7f) lxsiwax vs25,0,r26
+ 1a8: (7c 60 18 98|98 18 60 7c) lxsiwax vs3,0,r3
+ 1ac: (7f cc 00 67|67 00 cc 7f) mfvsrd r12,vs62
+ 1b0: (7d 94 00 e6|e6 00 94 7d) mffprwz r20,f12
+ 1b4: (7d c9 71 18|18 71 c9 7d) stxsiwx vs14,r9,r14
+ 1b8: (7e a0 41 18|18 41 a0 7e) stxsiwx vs21,0,r8
+ 1bc: (7e 0b 01 67|67 01 0b 7e) mtvsrd vs48,r11
+ 1c0: (7f f7 01 a7|a7 01 f7 7f) mtvrwa v31,r23
+ 1c4: (7e 1a 01 e6|e6 01 1a 7e) mtfprwz f16,r26
+ 1c8: (7d b3 6c 18|18 6c b3 7d) lxsspx vs13,r19,r13
+ 1cc: (7e 40 6c 18|18 6c 40 7e) lxsspx vs18,0,r13
+ 1d0: (7d 62 25 19|19 25 62 7d) stxsspx vs43,r2,r4
+ 1d4: (7e e0 5d 19|19 5d e0 7e) stxsspx vs55,0,r11
+ 1d8: (f2 d0 c8 05|05 c8 d0 f2) xsaddsp vs54,vs48,vs25
+ 1dc: (f1 d2 08 0c|0c 08 d2 f1) xsmaddasp vs14,vs50,vs1
+ 1e0: (f3 56 50 42|42 50 56 f3) xssubsp vs26,vs22,vs42
+ 1e4: (f3 75 a0 4e|4e a0 75 f3) xsmaddmsp vs27,vs53,vs52
+ 1e8: (f1 00 d8 2a|2a d8 00 f1) xsrsqrtesp vs8,vs59
+ 1ec: (f1 80 48 2e|2e 48 80 f1) xssqrtsp vs12,vs41
+ 1f0: (f3 2b 00 83|83 00 2b f3) xsmulsp vs57,vs11,vs32
+ 1f4: (f0 d4 d0 89|89 d0 d4 f0) xsmsubasp vs38,vs20,vs26
+ 1f8: (f3 53 30 c0|c0 30 53 f3) xsdivsp vs26,vs19,vs6
+ 1fc: (f0 65 b8 cf|cf b8 65 f0) xsmsubmsp vs35,vs37,vs55
+ 200: (f3 60 40 69|69 40 60 f3) xsresp vs59,vs8
+ 204: (f1 81 0c 0f|0f 0c 81 f1) xsnmaddasp vs44,vs33,vs33
+ 208: (f2 3e f4 4c|4c f4 3e f2) xsnmaddmsp vs17,vs62,vs30
+ 20c: (f2 d4 fc 8d|8d fc d4 f2) xsnmsubasp vs54,vs52,vs31
+ 210: (f0 a5 d4 cb|cb d4 a5 f0) xsnmsubmsp vs37,vs5,vs58
+ 214: (f3 d6 65 56|56 65 d6 f3) xxlorc vs30,vs54,vs44
+ 218: (f2 2e ed 91|91 ed 2e f2) xxlnand vs49,vs14,vs29
+ 21c: (f3 d6 f5 d1|d1 f5 d6 f3) xxleqv vs62,vs22,vs30
+ 220: (f3 80 b4 2f|2f b4 80 f3) xscvdpspn vs60,vs54
+ 224: (f2 c0 6c 66|66 6c c0 f2) xsrsp vs22,vs45
+ 228: (f3 40 dc a2|a2 dc 40 f3) xscvuxdsp vs26,vs59
+ 22c: (f0 c0 8c e3|e3 8c c0 f0) xscvsxdsp vs38,vs49
+ 230: (f3 60 d5 2d|2d d5 60 f3) xscvspdpn vs59,vs26
+ 234: (ff 0e 16 8c|8c 16 0e ff) fmrgow f24,f14,f2
+ 238: (fe c7 2f 8c|8c 2f c7 fe) fmrgew f22,f7,f5
+#pass
Index: gas/testsuite/gas/ppc/power8.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/power8.s,v
retrieving revision 1.2
diff -u -p -r1.2 power8.s
--- gas/testsuite/gas/ppc/power8.s 14 Jan 2013 06:42:00 -0000 1.2
+++ gas/testsuite/gas/ppc/power8.s 20 May 2013 23:50:58 -0000
@@ -19,3 +19,126 @@ power8:
tresume.
ori 2,2,0
.p2align 4,,15
+ rfebb 0
+ rfebb
+ rfebb 1
+ bctar- 12,21
+ bctarl- 4,7
+ bctar+ 12,12
+ bctarl+ 4,2
+ bctar 4,8,1
+ bctarl 4,7,2
+ waitasec
+ msgsndp 8
+ mtsle 1
+ msgclrp 27
+ stqcx. 10,10,12
+ stqcx. 28,0,7
+ lqarx 24,19,11,0
+ lqarx 22,0,11,0
+ mfbhrbe 20,6
+ pbt. 29,17,16
+ pbt. 14,0,7
+ clrbhrb
+ vpermxor 11,10,0,23
+ vaddeuqm 24,2,7,4
+ vaddecuq 10,10,8,2
+ vsubeuqm 5,15,8,19
+ vsubecuq 12,31,16,29
+ vmulouw 20,29,13
+ vmuluwm 29,0,26
+ vaddudm 8,21,28
+ vmaxud 1,26,1
+ vrld 20,3,1
+ vcmpequd 4,19,11
+ vadduqm 23,14,30
+ vaddcuq 8,8,13
+ vmulosw 28,27,4
+ vmaxsd 3,4,4
+ vmuleuw 0,19,21
+ vminud 24,20,19
+ vcmpgtud 0,28,15
+ vmulesw 21,0,2
+ vminsd 9,26,9
+ vsrad 25,29,11
+ vcmpgtsd 11,28,11
+ bcdadd. 5,8,26,1
+ vpmsumb 4,3,12
+ bcdsub. 26,31,21,1
+ vpmsumh 5,17,16
+ vpkudum 23,17,20
+ vpmsumw 24,21,29
+ vpmsumd 9,22,13
+ vpkudus 18,19,18
+ vsubuqm 30,16,22
+ vcipher 14,11,7
+ vcipherlast 10,2,22
+ vgbbd 23,13
+ vsubcuq 16,25,16
+ vorc 31,1,5
+ vncipher 4,17,31
+ vncipherlast 24,2,27
+ vbpermq 23,21,23
+ vpksdus 27,18,9
+ vnand 27,29,27
+ vsld 19,19,24
+ vsbox 5,13
+ vpksdss 25,3,7
+ vcmpequd. 28,8,0
+ vupkhsw 26,26
+ vshasigmaw 5,7,0,6
+ veqv 28,21,14
+ vmrgow 1,8,19
+ vshasigmad 0,10,0,10
+ vsrd 5,27,14
+ vupklsw 11,13
+ vclzb 14,16
+ vpopcntb 20,27
+ vclzh 28,11
+ vpopcnth 24,9
+ vclzw 27,31
+ vpopcntw 17,19
+ vclzd 12,29
+ vpopcntd 23,22
+ vcmpgtud. 24,20,29
+ vcmpgtsd. 9,6,27
+ lxsiwzx 62,14,26
+ lxsiwzx 40,0,25
+ lxsiwax 25,0,26
+ lxsiwax 3,0,3
+ mfvsrd 12,62
+ mfvsrwz 20,12
+ stxsiwx 14,9,14
+ stxsiwx 21,0,8
+ mtvsrd 48,11
+ mtvsrwa 63,23
+ mtvsrwz 16,26
+ lxsspx 13,19,13
+ lxsspx 18,0,13
+ stxsspx 43,2,4
+ stxsspx 55,0,11
+ xsaddsp 54,48,25
+ xsmaddasp 14,50,1
+ xssubsp 26,22,42
+ xsmaddmsp 27,53,52
+ xsrsqrtesp 8,59
+ xssqrtsp 12,41
+ xsmulsp 57,11,32
+ xsmsubasp 38,20,26
+ xsdivsp 26,19,6
+ xsmsubmsp 35,37,55
+ xsresp 59,8
+ xsnmaddasp 44,33,33
+ xsnmaddmsp 17,62,30
+ xsnmsubasp 54,52,31
+ xsnmsubmsp 37,5,58
+ xxlorc 30,54,44
+ xxlnand 49,14,29
+ xxleqv 62,22,30
+ xscvdpspn 60,54
+ xsrsp 22,45
+ xscvuxdsp 26,59
+ xscvsxdsp 38,49
+ xscvspdpn 59,26
+ fmrgow 24,14,2
+ fmrgew 22,7,5
Index: gas/testsuite/gas/ppc/ppc.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/ppc.exp,v
retrieving revision 1.34
diff -u -p -r1.34 ppc.exp
--- gas/testsuite/gas/ppc/ppc.exp 16 May 2013 15:37:50 -0000 1.34
+++ gas/testsuite/gas/ppc/ppc.exp 20 May 2013 23:50:58 -0000
@@ -85,6 +85,7 @@ if { [istarget powerpc*-*-*] } then {
run_dump_test "power7"
run_dump_test "power8"
run_dump_test "vsx"
+ run_dump_test "vsx2"
run_dump_test "htm"
run_dump_test "titan"
}
Index: gas/testsuite/gas/ppc/vsx.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/vsx.d,v
retrieving revision 1.3
diff -u -p -r1.3 vsx.d
--- gas/testsuite/gas/ppc/vsx.d 29 Oct 2012 09:25:15 -0000 1.3
+++ gas/testsuite/gas/ppc/vsx.d 20 May 2013 23:50:58 -0000
@@ -166,3 +166,8 @@ Disassembly of section \.text:
26c: (f1 12 e7 bf|bf e7 12 f1) xxsel vs40,vs50,vs60,vs62
270: (f1 12 e2 17|17 e2 12 f1) xxsldwi vs40,vs50,vs60,2
274: (f1 02 e2 93|93 e2 02 f1) xxspltw vs40,vs60,2
+ 278: (7d 00 a6 99|99 a6 00 7d) lxvd2x vs40,0,r20
+ 27c: (7d 0a a6 99|99 a6 0a 7d) lxvd2x vs40,r10,r20
+ 280: (7d 00 a7 99|99 a7 00 7d) stxvd2x vs40,0,r20
+ 284: (7d 0a a7 99|99 a7 0a 7d) stxvd2x vs40,r10,r20
+#pass
Index: gas/testsuite/gas/ppc/vsx.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/vsx.s,v
retrieving revision 1.3
diff -u -p -r1.3 vsx.s
--- gas/testsuite/gas/ppc/vsx.s 29 Oct 2012 09:25:15 -0000 1.3
+++ gas/testsuite/gas/ppc/vsx.s 20 May 2013 23:50:58 -0000
@@ -158,3 +158,7 @@ start:
xxsel 40,50,60,62
xxsldwi 40,50,60,2
xxspltw 40,60,2
+ lxvx 40,0,20
+ lxvx 40,10,20
+ stxvx 40,0,20
+ stxvx 40,10,20
Index: gas/testsuite/gas/ppc/vsx2.d
===================================================================
RCS file: gas/testsuite/gas/ppc/vsx2.d
diff -N gas/testsuite/gas/ppc/vsx2.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/ppc/vsx2.d 20 May 2013 23:50:58 -0000
@@ -0,0 +1,65 @@
+#as: -mvsx
+#objdump: -dr -Mvsx
+#name: VSX ISA 2.07 instructions
+
+.*
+
+Disassembly of section \.text:
+
+0+00 <vsx2>:
+ 0: 7f ce d0 19 lxsiwzx vs62,r14,r26
+ 4: 7d 00 c8 19 lxsiwzx vs40,0,r25
+ 8: 7f 20 d0 98 lxsiwax vs25,0,r26
+ c: 7c 60 18 98 lxsiwax vs3,0,r3
+ 10: 7f cc 00 66 mfvsrd r12,vs30
+ 14: 7f cc 00 66 mfvsrd r12,vs30
+ 18: 7f cc 00 67 mfvsrd r12,vs62
+ 1c: 7f cc 00 67 mfvsrd r12,vs62
+ 20: 7d 94 00 e6 mffprwz r20,f12
+ 24: 7d 94 00 e6 mffprwz r20,f12
+ 28: 7d 95 00 e7 mfvrwz r21,v12
+ 2c: 7d 95 00 e7 mfvrwz r21,v12
+ 30: 7d c9 71 18 stxsiwx vs14,r9,r14
+ 34: 7e a0 41 18 stxsiwx vs21,0,r8
+ 38: 7d 7c 01 66 mtvsrd vs11,r28
+ 3c: 7d 7c 01 66 mtvsrd vs11,r28
+ 40: 7d 7d 01 67 mtvsrd vs43,r29
+ 44: 7d 7d 01 67 mtvsrd vs43,r29
+ 48: 7f 16 01 a6 mtfprwa f24,r22
+ 4c: 7f 16 01 a6 mtfprwa f24,r22
+ 50: 7f 37 01 a7 mtvrwa v25,r23
+ 54: 7f 37 01 a7 mtvrwa v25,r23
+ 58: 7f 5b 01 e6 mtfprwz f26,r27
+ 5c: 7f 5b 01 e6 mtfprwz f26,r27
+ 60: 7f 7c 01 e7 mtvrwz v27,r28
+ 64: 7f 7c 01 e7 mtvrwz v27,r28
+ 68: 7d b3 6c 18 lxsspx vs13,r19,r13
+ 6c: 7e 40 6c 18 lxsspx vs18,0,r13
+ 70: 7d 62 25 19 stxsspx vs43,r2,r4
+ 74: 7e e0 5d 19 stxsspx vs55,0,r11
+ 78: f2 d0 c8 05 xsaddsp vs54,vs48,vs25
+ 7c: f1 d2 08 0c xsmaddasp vs14,vs50,vs1
+ 80: f3 56 50 42 xssubsp vs26,vs22,vs42
+ 84: f3 75 a0 4e xsmaddmsp vs27,vs53,vs52
+ 88: f1 00 d8 2a xsrsqrtesp vs8,vs59
+ 8c: f1 80 48 2e xssqrtsp vs12,vs41
+ 90: f3 2b 00 83 xsmulsp vs57,vs11,vs32
+ 94: f0 d4 d0 89 xsmsubasp vs38,vs20,vs26
+ 98: f3 53 30 c0 xsdivsp vs26,vs19,vs6
+ 9c: f0 65 b8 cf xsmsubmsp vs35,vs37,vs55
+ a0: f3 60 40 69 xsresp vs59,vs8
+ a4: f1 81 0c 0f xsnmaddasp vs44,vs33,vs33
+ a8: f2 3e f4 4c xsnmaddmsp vs17,vs62,vs30
+ ac: f2 d4 fc 8d xsnmsubasp vs54,vs52,vs31
+ b0: f0 a5 d4 cb xsnmsubmsp vs37,vs5,vs58
+ b4: f3 d6 65 56 xxlorc vs30,vs54,vs44
+ b8: f2 2e ed 91 xxlnand vs49,vs14,vs29
+ bc: f3 d6 f5 d1 xxleqv vs62,vs22,vs30
+ c0: f3 80 b4 2f xscvdpspn vs60,vs54
+ c4: f2 c0 6c 66 xsrsp vs22,vs45
+ c8: f3 40 dc a2 xscvuxdsp vs26,vs59
+ cc: f0 c0 8c e3 xscvsxdsp vs38,vs49
+ d0: f3 60 d5 2d xscvspdpn vs59,vs26
+ d4: ff 0e 16 8c fmrgow f24,f14,f2
+ d8: fe c7 2f 8c fmrgew f22,f7,f5
+#pass
Index: gas/testsuite/gas/ppc/vsx2.s
===================================================================
RCS file: gas/testsuite/gas/ppc/vsx2.s
diff -N gas/testsuite/gas/ppc/vsx2.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/ppc/vsx2.s 20 May 2013 23:50:58 -0000
@@ -0,0 +1,57 @@
+ .text
+vsx2:
+ lxsiwzx 62,14,26
+ lxsiwzx 40,0,25
+ lxsiwax 25,0,26
+ lxsiwax 3,0,3
+ mfvsrd 12,30
+ mffprd 12,30
+ mfvsrd 12,62
+ mfvrd 12,30
+ mfvsrwz 20,12
+ mffprwz 20,12
+ mfvsrwz 21,44
+ mfvrwz 21,12
+ stxsiwx 14,9,14
+ stxsiwx 21,0,8
+ mtvsrd 11,28
+ mtfprd 11,28
+ mtvsrd 43,29
+ mtvrd 11,29
+ mtvsrwa 24,22
+ mtfprwa 24,22
+ mtvsrwa 57,23
+ mtvrwa 25,23
+ mtvsrwz 26,27
+ mtfprwz 26,27
+ mtvsrwz 59,28
+ mtvrwz 27,28
+ lxsspx 13,19,13
+ lxsspx 18,0,13
+ stxsspx 43,2,4
+ stxsspx 55,0,11
+ xsaddsp 54,48,25
+ xsmaddasp 14,50,1
+ xssubsp 26,22,42
+ xsmaddmsp 27,53,52
+ xsrsqrtesp 8,59
+ xssqrtsp 12,41
+ xsmulsp 57,11,32
+ xsmsubasp 38,20,26
+ xsdivsp 26,19,6
+ xsmsubmsp 35,37,55
+ xsresp 59,8
+ xsnmaddasp 44,33,33
+ xsnmaddmsp 17,62,30
+ xsnmsubasp 54,52,31
+ xsnmsubmsp 37,5,58
+ xxlorc 30,54,44
+ xxlnand 49,14,29
+ xxleqv 62,22,30
+ xscvdpspn 60,54
+ xsrsp 22,45
+ xscvuxdsp 26,59
+ xscvsxdsp 38,49
+ xscvspdpn 59,26
+ fmrgow 24,14,2
+ fmrgew 22,7,5