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Re: [PATCH, v3]: AMD btver1 and btver2 enablement

On Thu, Aug 16, 2012 at 11:28 PM, Eggone, NagaJyothi
<> wrote:
> Hello H.J.,
>> -----Original Message-----
>> From: H.J. Lu []
>> Sent: Thursday, August 16, 2012 11:31 PM
>> To: Eggone, NagaJyothi
>> Cc:
>> Subject: Re: [PATCH, v2]: AMD btver1 and btver2 enablement
>> >>
>> >> Do you really need Cpu3dnowPrfch? Where will it be used?
>> >
>> > The 3dnow 'prefetch' and 'prefetchw' instructions are available both
>> on the btver1 and btver2 cores. I could not have enabled both these
>> instructions for these cores without adding a cpu flag bit (this
>> corresponds to the cpuid ECX bit 8 on AMD processors).
>> Please drop Cpu3dnowPrfch and add CpuPRFCHW to
>> prefetch.
>> gas/testsuite changes should be in gas/testsuite/ChangeLog.
>> --
>> H.J.
> I have changed the patch as per suggestions above. This patch also includes the diffs of files opcodes/i386-init.h and opcodes/i386-tbl.h.
> Please review and if OK, commit to trunk.

Please reformat your ChangeLog entries to follow
existing ones.  You have extra blank lines and
missing '.'.

+  /* Supports prefetchw and 3dnow prefetch instructions.  */

Please drop 3dnow here.


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