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Re: [PATCH, v2] gas/x86-64: properly distinguish low and high register ranges


On Tue, Aug 7, 2012 at 3:24 AM, Jan Beulich <JBeulich@suse.com> wrote:
>>>> On 31.07.12 at 20:45, "H.J. Lu" <hjl.tools@gmail.com> wrote:
>> I'd like to see the impact of broken behaviors and verify that
>> the change fixes them.
>
> Here you go.
>
> Jan
>
> There were several cases where the registers in the REX encoded range
> got treated identically to the ones in the base range, due to not
> paying attention to the fact that reg_entry's reg_num field doesn't
> fully specify the register number (reg_flags also needs to be checked
> for RegRex). This patch introduces and uses a new (inline) function to
> obtain the full register number, and uses it to fix all those cases.
>
> It additionally adds the missing operand checks for SVME instructions
> (which match the monitor/mwait ones).
>
> gas/
> 2012-08-07  Jan Beulich <jbeulich@suse.com>
>
>         * config/tc-i386.c (register_number): New function.
>         (build_vex_prefix, process_immext, process_operands,
>         build_modrm_byte, i386_index_check): Use it.
>
> gas/testsuite/
> 2012-08-07  Jan Beulich <jbeulich@suse.com>
>
>         * gas/i386/x86-64-specific-reg.{s,l}: New.
>         * gas/i386/i386.exp: Run new test.
>
> opcodes/
> 2012-08-07  Jan Beulich <jbeulich@suse.com>
>
>         * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
>
> --- 2012-08-07/gas/config/tc-i386.c     2012-07-31 09:45:03.000000000 +0200
> +++ 2012-08-07/gas/config/tc-i386.c     2012-08-07 11:37:29.000000000 +0200
> @@ -1758,6 +1758,17 @@ operand_type_register_match (i386_operan
>  }
>
>  static INLINE unsigned int
> +register_number (const reg_entry *r)
> +{
> +  unsigned int nr = r->reg_num;
> +
> +  if (r->reg_flags & RegRex)
> +    nr += 8;
> +
> +  return nr;
> +}
> +
> +static INLINE unsigned int
>  mode_from_disp_size (i386_operand_type t)
>  {
>    if (t.bitfield.disp8)
> @@ -2830,12 +2841,7 @@ build_vex_prefix (const insn_template *t
>
>    /* Check register specifier.  */
>    if (i.vex.register_specifier)
> -    {
> -      register_specifier = i.vex.register_specifier->reg_num;
> -      if ((i.vex.register_specifier->reg_flags & RegRex))
> -       register_specifier += 8;
> -      register_specifier = ~register_specifier & 0xf;
> -    }
> +    register_specifier = ~register_number (i.vex.register_specifier) & 0xf;
>    else
>      register_specifier = 0xf;
>
> @@ -2974,16 +2980,15 @@ process_immext (void)
>  {
>    expressionS *exp;
>
> -  if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
> +  if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
> +      && i.operands > 0)
>      {
> -      /* SSE3 Instructions have the fixed operands with an opcode
> -        suffix which is coded in the same place as an 8-bit immediate
> -        field would be.  Here we check those operands and remove them
> -        afterwards.  */
> +      /* MONITOR/MWAIT as well as SVME instructions have fixed operands.
> +        Here we check those operands and remove them afterwards.  */
>        unsigned int x;
>

Please keep "with an opcode suffix which is coded in the same place
as an 8-bit immediate field would be."  OK with this change.

Thanks.


-- 
H.J.


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