[PATCH] x86/Intel: relax requirements for memory operands

["Jan Beulich" <JBeulich at suse dot com>]

MASM accepts ESP/RSP being specified second in a memory address
operand, by silently making it the base register despite not being
specified first.

Consequently, we also permit an xmm/ymm index to be specified first
(possibly alone), nevertheless putting it in as index register.

2012-07-24  Jan Beulich <jbeulich@suse.com>

	* config/tc-i386-intel.c (i386_intel_simplify_register): Handle
	xmm/ymm index register being specified first as well as esp/rsp
	base register being specified last in a memory operand.

--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -278,10 +278,24 @@ i386_intel_simplify_register (expression
 	}
       i.op[this_operand].regs = i386_regtab + reg_num;
     }
+  else if (!intel_state.index
+	   && (i386_regtab[reg_num].reg_type.bitfield.regxmm
+	       || i386_regtab[reg_num].reg_type.bitfield.regymm))
+    intel_state.index = i386_regtab + reg_num;
   else if (!intel_state.base && !intel_state.in_scale)
     intel_state.base = i386_regtab + reg_num;
   else if (!intel_state.index)
-    intel_state.index = i386_regtab + reg_num;
+    {
+      if (intel_state.in_scale
+	  || i386_regtab[reg_num].reg_type.bitfield.baseindex)
+	intel_state.index = i386_regtab + reg_num;
+      else
+	{
+	  /* Convert base to index and make ESP/RSP the base.  */
+	  intel_state.index = intel_state.base;
+	  intel_state.base = i386_regtab + reg_num;
+	}
+    }
   else
     {
       /* esp is invalid as index */

Attachment: binutils-mainline-x86-intel-index-base.patch
Description: Text document