Index: opcodes/ppc-dis.c =================================================================== RCS file: /cvs/src/src/opcodes/ppc-dis.c,v retrieving revision 1.54 diff -u -p -r1.54 ppc-dis.c --- opcodes/ppc-dis.c 16 Mar 2012 12:14:32 -0000 1.54 +++ opcodes/ppc-dis.c 9 May 2012 15:32:14 -0000 @@ -23,6 +23,9 @@ #include #include "sysdep.h" #include "dis-asm.h" +#include "elf-bfd.h" +#include "elf32-ppc.h" +#include "elf/ppc.h" #include "opintl.h" #include "opcode/ppc.h" @@ -181,18 +184,38 @@ struct ppc_mopt ppc_opts[] = { { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), 0 }, + { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE), + PPC_OPCODE_VLE }, { "vsx", (PPC_OPCODE_PPC), PPC_OPCODE_VSX }, }; +/* Switch between Booke and VLE dialects for interlinked dumps. */ +static ppc_cpu_t +get_powerpc_dialect (struct disassemble_info *info) +{ + ppc_cpu_t dialect = 0; + + dialect = POWERPC_DIALECT (info); + + /* Disassemble according to the section headers flags for VLE-mode. */ + if (dialect & PPC_OPCODE_VLE + && is_ppc_vle (info->section)) + return dialect; + else + return dialect & ~ PPC_OPCODE_VLE; +} + /* Handle -m and -M options that set cpu type, and .machine arg. */ ppc_cpu_t ppc_parse_cpu (ppc_cpu_t ppc_cpu, const char *arg) { + const ppc_cpu_t retain_mask = (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX + | PPC_OPCODE_SPE | PPC_OPCODE_ANY + | PPC_OPCODE_VLE | PPC_OPCODE_PMR); /* Sticky bits. */ - ppc_cpu_t retain_flags = ppc_cpu & (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX - | PPC_OPCODE_SPE | PPC_OPCODE_ANY); + ppc_cpu_t retain_flags = ppc_cpu & retain_mask; unsigned int i; for (i = 0; i < sizeof (ppc_opts) / sizeof (ppc_opts[0]); i++) @@ -201,8 +224,7 @@ ppc_parse_cpu (ppc_cpu_t ppc_cpu, const if (ppc_opts[i].sticky) { retain_flags |= ppc_opts[i].sticky; - if ((ppc_cpu & ~(ppc_cpu_t) (PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX - | PPC_OPCODE_SPE | PPC_OPCODE_ANY)) != 0) + if ((ppc_cpu & ~retain_mask) != 0) break; } ppc_cpu = ppc_opts[i].cpu; @@ -256,16 +278,22 @@ powerpc_init_dialect (struct disassemble dialect |= PPC_OPCODE_64; else dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; - /* Choose a reasonable default. */ - dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601 - | PPC_OPCODE_ALTIVEC); + if (info->mach == bfd_mach_ppc_vle) + dialect |= PPC_OPCODE_PPC | PPC_OPCODE_VLE; + else + /* Choose a reasonable default. */ + dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601 + | PPC_OPCODE_ALTIVEC); } info->private_data = priv; POWERPC_DIALECT(info) = dialect; } -static unsigned short powerpc_opcd_indices[65]; +#define PPC_OPCD_SEGS 64 +static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1]; +#define VLE_OPCD_SEGS 32 +static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1]; /* Calculate opcode table indices to speed up disassembly, and init dialect. */ @@ -285,13 +313,30 @@ disassemble_init_powerpc (struct disasse } last = powerpc_num_opcodes; - for (i = 64; i > 0; --i) + for (i = PPC_OPCD_SEGS; i > 0; --i) { if (powerpc_opcd_indices[i] == 0) powerpc_opcd_indices[i] = last; last = powerpc_opcd_indices[i]; } + i = vle_num_opcodes; + while (--i >= 0) + { + unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask); + unsigned seg = VLE_OP_TO_SEG (op); + + vle_opcd_indices[seg] = i; + } + + last = vle_num_opcodes; + for (i = VLE_OPCD_SEGS; i > 0; --i) + { + if (vle_opcd_indices[i] == 0) + vle_opcd_indices[i] = last; + last = vle_opcd_indices[i]; + } + if (info->arch == bfd_arch_powerpc) powerpc_init_dialect (info); } @@ -301,7 +346,7 @@ disassemble_init_powerpc (struct disasse int print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) { - return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info)); + return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info)); } /* Print a little endian PowerPC instruction. */ @@ -309,7 +354,7 @@ print_insn_big_powerpc (bfd_vma memaddr, int print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) { - return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info)); + return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info)); } /* Print a POWER (RS/6000) instruction. */ @@ -333,11 +378,14 @@ operand_value_powerpc (const struct powe value = (*operand->extract) (insn, dialect, &invalid); else { - value = (insn >> operand->shift) & operand->bitm; + if (operand->shift >= 0) + value = (insn >> operand->shift) & operand->bitm; + else + value = (insn << -operand->shift) & operand->bitm; if ((operand->flags & PPC_OPERAND_SIGNED) != 0) { /* BITM is always some number of zeros followed by some - number of ones, followed by some numer of zeros. */ + number of ones, followed by some number of zeros. */ unsigned long top = operand->bitm; /* top & -top gives the rightmost 1 bit, so this fills in any trailing zeros. */ @@ -372,7 +420,7 @@ skip_optional_operands (const unsigned c /* Find a match for INSN in the opcode table, given machine DIALECT. A DIALECT of -1 is special, matching all machine opcode variations. */ - + static const struct powerpc_opcode * lookup_powerpc (unsigned long insn, ppc_cpu_t dialect) { @@ -416,6 +464,60 @@ lookup_powerpc (unsigned long insn, ppc_ return NULL; } +/* Find a match for INSN in the VLE opcode table. */ + +static const struct powerpc_opcode * +lookup_vle (unsigned long insn) +{ + const struct powerpc_opcode *opcode; + const struct powerpc_opcode *opcode_end; + unsigned op, seg; + + op = PPC_OP (insn); + if (op >= 0x20 && op <= 0x37) + { + /* This insn has a 4-bit opcode. */ + op &= 0x3c; + } + seg = VLE_OP_TO_SEG (op); + + /* Find the first match in the opcode table for this major opcode. */ + opcode_end = vle_opcodes + vle_opcd_indices[seg + 1]; + for (opcode = vle_opcodes + vle_opcd_indices[seg]; + opcode < opcode_end; + ++opcode) + { + unsigned long table_opcd = opcode->opcode; + unsigned long table_mask = opcode->mask; + bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask); + unsigned long insn2; + const unsigned char *opindex; + const struct powerpc_operand *operand; + int invalid; + + insn2 = insn; + if (table_op_is_short) + insn2 >>= 16; + if ((insn2 & table_mask) != table_opcd) + continue; + + /* Check validity of operands. */ + invalid = 0; + for (opindex = opcode->operands; *opindex != 0; ++opindex) + { + operand = powerpc_operands + *opindex; + if (operand->extract) + (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); + } + if (invalid) + continue; + + return opcode; + } + + return NULL; +} + /* Print a PowerPC or POWER instruction. */ static int @@ -428,12 +530,28 @@ print_insn_powerpc (bfd_vma memaddr, int status; unsigned long insn; const struct powerpc_opcode *opcode; + bfd_boolean insn_is_short; status = (*info->read_memory_func) (memaddr, buffer, 4, info); if (status != 0) { - (*info->memory_error_func) (status, memaddr, info); - return -1; + /* The final instruction may be a 2-byte VLE insn. */ + if ((dialect & PPC_OPCODE_VLE) != 0) + { + /* Clear buffer so unused bytes will not have garbage in them. */ + buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0; + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + } + else + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } } if (bigendian) @@ -441,7 +559,17 @@ print_insn_powerpc (bfd_vma memaddr, else insn = bfd_getl32 (buffer); - opcode = lookup_powerpc (insn, dialect); + /* Get the major opcode of the insn. */ + opcode = NULL; + insn_is_short = FALSE; + if ((dialect & PPC_OPCODE_VLE) != 0) + { + opcode = lookup_vle (insn); + if (opcode != NULL) + insn_is_short = PPC_OP_SE_VLE(opcode->mask); + } + if (opcode == NULL) + opcode = lookup_powerpc (insn, dialect); if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) opcode = lookup_powerpc (insn, (ppc_cpu_t) -1); @@ -458,6 +586,10 @@ print_insn_powerpc (bfd_vma memaddr, else (*info->fprintf_func) (info->stream, "%s", opcode->name); + if (insn_is_short) + /* The operands will be fetched out of the 16-bit instruction. */ + insn >>= 16; + /* Now extract and print the operands. */ need_comma = 0; need_paren = 0; @@ -513,26 +645,26 @@ print_insn_powerpc (bfd_vma memaddr, (*info->fprintf_func) (info->stream, "fcr%ld", value); else if ((operand->flags & PPC_OPERAND_UDI) != 0) (*info->fprintf_func) (info->stream, "%ld", value); - else if ((operand->flags & PPC_OPERAND_CR) != 0 - && (dialect & PPC_OPCODE_PPC) != 0) + else if ((operand->flags & PPC_OPERAND_CR_REG) != 0 + && (((dialect & PPC_OPCODE_PPC) != 0) + || ((dialect & PPC_OPCODE_VLE) != 0))) + (*info->fprintf_func) (info->stream, "cr%ld", value); + else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0) + && (((dialect & PPC_OPCODE_PPC) != 0) + || ((dialect & PPC_OPCODE_VLE) != 0))) { - if (operand->bitm == 7) - (*info->fprintf_func) (info->stream, "cr%ld", value); - else - { - static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; - int cr; - int cc; - - cr = value >> 2; - if (cr != 0) - (*info->fprintf_func) (info->stream, "4*cr%d+", cr); - cc = value & 3; - (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); - } + static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; + int cr; + int cc; + + cr = value >> 2; + if (cr != 0) + (*info->fprintf_func) (info->stream, "4*cr%d+", cr); + cc = value & 3; + (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); } else - (*info->fprintf_func) (info->stream, "%ld", value); + (*info->fprintf_func) (info->stream, "%d", value); if (need_paren) { @@ -549,8 +681,16 @@ print_insn_powerpc (bfd_vma memaddr, } } - /* We have found and printed an instruction; return. */ - return 4; + /* We have found and printed an instruction. + If it was a short VLE instruction we have more to do. */ + if (insn_is_short) + { + memaddr += 2; + return 2; + } + else + /* Otherwise, return. */ + return 4; } /* We could not find a match. */ Index: opcodes/ppc-opc.c =================================================================== RCS file: /cvs/src/src/opcodes/ppc-opc.c,v retrieving revision 1.141 diff -u -p -r1.141 ppc-opc.c --- opcodes/ppc-opc.c 9 Mar 2012 23:39:02 -0000 1.141 +++ opcodes/ppc-opc.c 9 May 2012 15:32:14 -0000 @@ -39,6 +39,10 @@ /* Local insertion and extraction functions. */ +static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **); +static long extract_arx (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **); +static long extract_ary (unsigned long, ppc_cpu_t, int *); static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **); static long extract_bat (unsigned long, ppc_cpu_t, int *); static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **); @@ -53,6 +57,8 @@ static unsigned long insert_boe (unsigne static long extract_boe (unsigned long, ppc_cpu_t, int *); static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); static long extract_fxm (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_li20 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **); static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **); static long extract_mbe (unsigned long, ppc_cpu_t, int *); @@ -62,6 +68,8 @@ static long extract_nb (unsigned long, p static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **); static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **); static long extract_nsi (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **); +static long extract_oimm (unsigned long, ppc_cpu_t, int *); static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **); static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **); static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **); @@ -69,8 +77,20 @@ static unsigned long insert_ras (unsigne static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **); static long extract_rbs (unsigned long, ppc_cpu_t, int *); static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **); +static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **); +static long extract_rx (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **); +static long extract_ry (unsigned long, ppc_cpu_t, int *); static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **); static long extract_sh6 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_sci8 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **); +static long extract_sci8n (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **); +static long extract_sd4h (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **); +static long extract_sd4w (unsigned long, ppc_cpu_t, int *); static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **); static long extract_spr (unsigned long, ppc_cpu_t, int *); static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **); @@ -89,6 +109,14 @@ static unsigned long insert_xc6 (unsigne static long extract_xc6 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **); static long extract_dm (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **); +static long extract_vlesi (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **); +static long extract_vlensi (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **); +static long extract_vleui (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **); +static long extract_vleil (unsigned long, ppc_cpu_t, int *); /* The operands table. @@ -113,7 +141,7 @@ const struct powerpc_operand powerpc_ope /* The BI field in a B form or XL form instruction. */ #define BI BA #define BI_MASK (0x1f << 16) - { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR }, + { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, /* The BA field in an XL form instruction when it must be the same as the BT field in the same instruction. */ @@ -123,7 +151,7 @@ const struct powerpc_operand powerpc_ope /* The BB field in an XL form instruction. */ #define BB BAT + 1 #define BB_MASK (0x1f << 11) - { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR }, + { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, /* The BB field in an XL form instruction when it must be the same as the BA field in the same instruction. */ @@ -168,7 +196,9 @@ const struct powerpc_operand powerpc_ope #define BF BDPA + 1 /* The CRFD field in an X form instruction. */ #define CRFD BF - { 0x7, 23, NULL, NULL, PPC_OPERAND_CR }, + /* The CRD field in an XL form instruction. */ +#define CRD BF + { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, /* The BF field in an X or XL form instruction. */ #define BFF BF + 1 @@ -177,11 +207,11 @@ const struct powerpc_operand powerpc_ope /* An optional BF field. This is used for comparison instructions, in which an omitted BF field is taken as zero. */ #define OBF BFF + 1 - { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, /* The BFA field in an X or XL form instruction. */ #define BFA OBF + 1 - { 0x7, 18, NULL, NULL, PPC_OPERAND_CR }, + { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, /* The BO field in a B form instruction. Certain values are illegal. */ @@ -199,14 +229,40 @@ const struct powerpc_operand powerpc_ope /* The BT field in an X or XL form instruction. */ #define BT BH + 1 - { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR }, + { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, + + /* The BI16 field in a BD8 form instruction. */ +#define BI16 BT + 1 + { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, + + /* The BI32 field in a BD15 form instruction. */ +#define BI32 BI16 + 1 + { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, + + /* The BO32 field in a BD15 form instruction. */ +#define BO32 BI32 + 1 + { 0x3, 20, NULL, NULL, 0 }, + + /* The B8 field in a BD8 form instruction. */ +#define B8 BO32 + 1 + { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The B15 field in a BD15 form instruction. The lowest bit is + forced to zero. */ +#define B15 B8 + 1 + { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, + + /* The B24 field in a BD24 form instruction. The lowest bit is + forced to zero. */ +#define B24 B15 + 1 + { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, /* The condition register number portion of the BI field in a B form or XL form instruction. This is used for the extended conditional branch mnemonics, which set the lower two bits of the BI field. This field is optional. */ -#define CR BT + 1 - { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, +#define CR B24 + 1 + { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, /* The CRB field in an X form instruction. */ #define CRB CR + 1 @@ -215,12 +271,19 @@ const struct powerpc_operand powerpc_ope #define MB_MASK (0x1f << 6) { 0x1f, 6, NULL, NULL, 0 }, + /* The CRD32 field in an XL form instruction. */ +#define CRD32 CRB + 1 + { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, + /* The CRFS field in an X form instruction. */ -#define CRFS CRB + 1 - { 0x7, 0, NULL, NULL, PPC_OPERAND_CR }, +#define CRFS CRD32 + 1 + { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, + +#define CRS CRFS + 1 + { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, /* The CT field in an X form instruction. */ -#define CT CRFS + 1 +#define CT CRS + 1 /* The MO field in an mbar instruction. */ #define MO CT { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, @@ -231,9 +294,15 @@ const struct powerpc_operand powerpc_ope #define D CT + 1 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + /* The D8 field in a D form instruction. This is a displacement off + a register, and implies that the next operand is a register in + parentheses. */ +#define D8 D + 1 + { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + /* The DQ field in a DQ form instruction. This is like D, but the lower four bits are forced to zero. */ -#define DQ D + 1 +#define DQ D8 + 1 { 0xfff0, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, @@ -310,8 +379,12 @@ const struct powerpc_operand powerpc_ope #define FXM4 FXM + 1 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, + /* The IMM20 field in an LI instruction. */ +#define IMM20 FXM4 + 1 + { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, + /* The L field in a D or X form instruction. */ -#define L FXM4 + 1 +#define L IMM20 + 1 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, /* The LEV field in a POWER SVC form instruction. */ @@ -436,6 +509,7 @@ const struct powerpc_operand powerpc_ope #define RS RBOPT + 1 #define RT RS #define RT_MASK (0x1f << 21) +#define RD RS { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, /* The RS and RT fields of the DS form stq instruction, which have @@ -449,8 +523,47 @@ const struct powerpc_operand powerpc_ope #define RTO RSO { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, + /* The RX field of the SE_RR form instruction. */ +#define RX RSO + 1 + { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, + + /* The ARX field of the SE_RR form instruction. */ +#define ARX RX + 1 + { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, + + /* The RY field of the SE_RR form instruction. */ +#define RY ARX + 1 +#define RZ RY + { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, + + /* The ARY field of the SE_RR form instruction. */ +#define ARY RY + 1 + { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, + + /* The SCLSCI8 field in a D form instruction. */ +#define SCLSCI8 ARY + 1 + { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, + + /* The SCLSCI8N field in a D form instruction. This is the same as the + SCLSCI8 field, only negated. */ +#define SCLSCI8N SCLSCI8 + 1 + { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, + PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, + + /* The SD field of the SD4 form instruction. */ +#define SE_SD SCLSCI8N + 1 + { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, + + /* The SD field of the SD4 form instruction, for halfword. */ +#define SE_SDH SE_SD + 1 + { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS }, + + /* The SD field of the SD4 form instruction, for word. */ +#define SE_SDW SE_SDH + 1 + { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS }, + /* The SH field in an X or M form instruction. */ -#define SH RSO + 1 +#define SH SE_SDW + 1 #define SH_MASK (0x1f << 11) /* The other UIMM field in a EVX form instruction. */ #define EVUIMM SH @@ -459,7 +572,7 @@ const struct powerpc_operand powerpc_ope /* The SH field in an MD form instruction. This is split. */ #define SH6 SH + 1 #define SH6_MASK ((0x1f << 11) | (1 << 1)) - { 0x3f, -1, insert_sh6, extract_sh6, 0 }, + { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, /* The SH field of the tlbwe instruction, which is optional. */ #define SHO SH6 + 1 @@ -474,9 +587,13 @@ const struct powerpc_operand powerpc_ope #define SISIGNOPT SI + 1 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, + /* The SI8 field in a D form instruction. */ +#define SI8 SISIGNOPT + 1 + { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, + /* The SPR field in an XFX form instruction. This is flipped--the lower 5 bits are stored in the upper 5 and vice- versa. */ -#define SPR SISIGNOPT + 1 +#define SPR SI8 + 1 #define PMR SPR #define TMR SPR #define SPR_MASK (0x3ff << 11) @@ -524,8 +641,20 @@ const struct powerpc_operand powerpc_ope #define UI TO + 1 { 0xffff, 0, NULL, NULL, 0 }, + /* The IMM field in an SE_IM5 instruction. */ +#define UI5 UI + 1 + { 0x1f, 4, NULL, NULL, 0 }, + + /* The OIMM field in an SE_OIM5 instruction. */ +#define OIMM5 UI5 + 1 + { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, + + /* The UI7 field in an SE_LI instruction. */ +#define UI7 OIMM5 + 1 + { 0x7f, 4, NULL, NULL, 0 }, + /* The VA field in a VA, VX or VXR form instruction. */ -#define VA UI + 1 +#define VA UI7 + 1 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, /* The VB field in a VA, VX or VXR form instruction. */ @@ -574,6 +703,8 @@ const struct powerpc_operand powerpc_ope /* PowerPC paired singles extensions. */ /* W bit in the pair singles instructions for x type instructions. */ #define PSWM WS + 1 + /* The BO16 field in a BD8 form instruction. */ +#define BO16 PSWM { 0x1, 10, 0, 0, 0 }, /* IDX bits for quantization in the pair singles instructions. */ @@ -643,28 +774,46 @@ const struct powerpc_operand powerpc_ope #define URC URB + 1 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, + /* The VLESIMM field in a D form instruction. */ +#define VLESIMM URC + 1 + { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, + PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, + + /* The VLENSIMM field in a D form instruction. */ +#define VLENSIMM VLESIMM + 1 + { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, + PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, + + /* The VLEUIMM field in a D form instruction. */ +#define VLEUIMM VLENSIMM + 1 + { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, + + /* The VLEUIMML field in a D form instruction. */ +#define VLEUIMML VLEUIMM + 1 + { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, + /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ -#define XS6 URC + 1 +#define XS6 VLEUIMML + 1 #define XT6 XS6 - { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, + { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, /* The XA field in an XX3 form instruction. This is split. */ #define XA6 XT6 + 1 - { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, + { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, /* The XB field in an XX2 or XX3 form instruction. This is split. */ #define XB6 XA6 + 1 - { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, + { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, /* The XB field in an XX3 form instruction when it must be the same as the XA field in the instruction. This is used in extended mnemonics like xvmovdp. This is split. */ #define XB6S XB6 + 1 - { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, + { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, /* The XC field in an XX4 form instruction. This is split. */ #define XC6 XB6S + 1 - { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, + { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, /* The DM or SHW field in an XX3 form instruction. */ #define DM XC6 + 1 @@ -688,6 +837,112 @@ const unsigned int num_powerpc_operands /* The functions used to insert and extract complicated operands. */ +/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ + +static unsigned long +insert_arx (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value >= 8 && value < 24) + return insn | ((value - 8) & 0xf); + else + { + *errmsg = _("invalid register"); + return 0; + } +} + +static long +extract_arx (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return (insn & 0xf) + 8; +} + +static unsigned long +insert_ary (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value >= 8 && value < 24) + return insn | (((value - 8) & 0xf) << 4); + else + { + *errmsg = _("invalid register"); + return 0; + } +} + +static long +extract_ary (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 4) & 0xf) + 8; +} + +static unsigned long +insert_rx (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value >= 0 && value < 8) + return insn | value; + else if (value >= 24 && value <= 31) + return insn | (value - 16); + else + { + *errmsg = _("invalid register"); + return 0; + } +} + +static long +extract_rx (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + int value = insn & 0xf; + if (value >= 0 && value < 8) + return value; + else + return value + 16; +} + +static unsigned long +insert_ry (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value >= 0 && value < 8) + return insn | (value << 4); + else if (value >= 24 && value <= 31) + return insn | ((value - 16) << 4); + else + { + *errmsg = _("invalid register"); + return 0; + } +} + +static long +extract_ry (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 4) & 0xf; + if (value >= 0 && value < 8) + return value; + else + return value + 16; +} + /* The BA field in an XL form instruction when it must be the same as the BT field in the same instruction. This operand is marked FAKE. The insertion function just copies the BT field into the BA field, @@ -1043,6 +1298,29 @@ extract_fxm (unsigned long insn, return mask; } +static unsigned long +insert_li20 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff); +} + +static long +extract_li20 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000; + + return ext + | (((insn >> 11) & 0xf) << 16) + | (((insn >> 17) & 0xf) << 12) + | (((insn >> 16) & 0x1) << 11) + | (insn & 0x7ff); +} + /* The LS field in a sync instruction that accepts 2 operands Values 2 and 3 are reserved, must be treated as 0 for future compatibility @@ -1338,6 +1616,166 @@ insert_rbx (unsigned long insn, return insn | ((value & 0x1f) << 11); } +/* The SCI8 field is made up of SCL and {U,N}I8 fields. */ +static unsigned long +insert_sci8 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + int fill = 0; + int scale_factor = 0; + long ui8 = value; + + if ((value & 0xff000000) == (unsigned int) value) + { + scale_factor = 3; + ui8 = value >> 24; + fill = 0; + } + else if ((value & 0xff0000) == (unsigned int) value) + { + scale_factor = 2; + ui8 = value >> 16; + fill = 0; + } + else if ((value & 0xff00) == (unsigned int) value) + { + scale_factor = 1; + ui8 = value >> 8; + fill = 0; + } + else if ((value & 0xff) == value) + { + scale_factor = 0; + ui8 = value; + fill = 0; + } + else if ((value & 0xffffff00) == 0xffffff00) + { + scale_factor = 0; + ui8 = (value & 0xff); + fill = 1; + } + else if ((value & 0xffff00ff) == 0xffff00ff) + { + scale_factor = 1; + ui8 = (value & 0xff00) >> 8; + fill = 1; + } + else if ((value & 0xff00ffff) == 0xff00ffff) + { + scale_factor = 2; + ui8 = (value & 0xff0000) >> 16; + fill = 1; + } + else if ((value & 0x00ffffff) == 0x00ffffff) + { + scale_factor = 3; + ui8 = (value & 0xff000000) >> 24; + fill = 1; + } + else + *errmsg = _("illegal immediate value"); + + return insn | (fill << 10) | (scale_factor << 8) | (ui8 & 0xff); +} + +static long +extract_sci8 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + int scale_factor, fill; + scale_factor = (insn & 0x300) >> 8; + fill = (insn & 0x00000400) >> 10; + + if (fill == 0) + return (insn & 0xff) << (scale_factor << 3); + + /* Fill is one. */ + if (scale_factor == 0) + return (insn & 0xff) | 0xffffff00; + else if (scale_factor == 1) + return 0xffff00ff | ((insn & 0xff) << (scale_factor << 3)); + else if (scale_factor == 2) + return 0xff00ffff | (insn & 0xff << (scale_factor << 3)); + else /* scale_factor 3 */ + return 0x00ffffff | (insn & 0xff << (scale_factor << 3)); +} + +static unsigned long +insert_sci8n (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + insn = insert_sci8 (insn, -(value & 0xff) & 0xff, 0, errmsg); + /* Set the F bit. */ + return insn | 0x400; +} + +static long +extract_sci8n (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + int scale_factor; + scale_factor = (insn & 0x300) >> 8; + return -(((insn & 0xff) ^ 0x80) - 0x80) << (scale_factor << 3); +} + +static unsigned long +insert_sd4h (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1e) << 7); +} + +static long +extract_sd4h (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 8) & 0xf) << 1; +} + +static unsigned long +insert_sd4w (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x3c) << 6); +} + +static long +extract_sd4w (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 8) & 0xf) << 2; +} + +static unsigned long +insert_oimm (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (((value - 1) & 0x1f) << 4); +} + +static long +extract_oimm (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 4) & 0x1f) + 1; +} + /* The SH field in an MD form instruction. This is split. */ static unsigned long @@ -1378,6 +1816,7 @@ extract_spr (unsigned long insn, } /* Some dialects have 8 SPRG registers instead of the standard 4. */ +#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE) static unsigned long insert_sprg (unsigned long insn, @@ -1387,7 +1826,7 @@ insert_sprg (unsigned long insn, { if (value > 7 || (value > 3 - && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)) + && (dialect & ALLOW8_SPRG) == 0)) *errmsg = _("invalid sprg number"); /* If this is mfsprg4..7 then use spr 260..263 which can be read in @@ -1574,6 +2013,89 @@ extract_dm (unsigned long insn, *invalid = 1; return (value) ? 1 : 0; } +/* The VLESIMM field in an I16A form instruction. This is split. */ + +static unsigned long +insert_vlesi (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0xf800) << 10) | (value & 0x7ff); +} + +static long +extract_vlesi (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + /* RWRW Because I don't know how to make int be 16 and long be 32 */ + /* I can't rely on casting an int to long to get sign extension. */ + long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); + if (value & 0x8000) + value |= 0xffff0000; + return value; +} + +static unsigned long +insert_vlensi (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + value = -value; + return insn | ((value & 0xf800) << 10) | (value & 0x7ff); +} +static long +extract_vlensi (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); + if (value & 0x8000) + value |= 0xffff0000; + *invalid = 1; + return -value; +} + +/* The VLEUIMM field in an I16A form instruction. This is split. */ + +static unsigned long +insert_vleui (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0xf800) << 10) | (value & 0x7ff); +} + +static long +extract_vleui (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 10) & 0xf800) | (insn & 0x7ff); +} + +/* The VLEUIMML field in an I16L form instruction. This is split. */ + +static unsigned long +insert_vleil (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0xf800) << 5) | (value & 0x7ff); +} + +static long +extract_vleil (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 5) & 0xf800) | (insn & 0x7ff); +} + /* Macros used to form opcodes. */ @@ -1593,6 +2115,11 @@ extract_dm (unsigned long insn, #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) #define OPL_MASK OPL (0x3f,1) +/* The main opcode combined with an update code in D form instruction. + Used for extended mnemonics for VLE memory instructions. */ +#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8)) +#define OPVUP_MASK OPVUP (0x3f, 0xff) + /* An A form instruction. */ #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) #define A_MASK A (0x3f, 0x1f, 1) @@ -1613,6 +2140,43 @@ extract_dm (unsigned long insn, #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) #define B_MASK B (0x3f, 1, 1) +/* A BD8 form instruction. This is a 16-bit instruction. */ +#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8)) +#define BD8_MASK BD8 (0x3f, 1, 1) + +/* Another BD8 form instruction. This is a 16-bit instruction. */ +#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11) +#define BD8IO_MASK BD8IO (0x1f) + +/* A BD8 form instruction for simplified mnemonics. */ +#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) +/* A mask that excludes BO32 and BI32. */ +#define EBD8IO1_MASK 0xf800 +/* A mask that includes BO32 and excludes BI32. */ +#define EBD8IO2_MASK 0xfc00 +/* A mask that include BO32 AND BI32. */ +#define EBD8IO3_MASK 0xff00 + +/* A BD15 form instruction. */ +#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1)) +#define BD15_MASK BD15 (0x3f, 0xf, 1) + +/* A BD15 form instruction for extended conditional branch mnemonics. */ +#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1) +#define EBD15_MASK 0xfff00001 + +/* A BD15 form instruction for extended conditional branch mnemonics with BI. */ +#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \ + | (((aa) & 0xf) << 22) \ + | (((bo) & 0x3) << 20) \ + | (((bi) & 0x3) << 16) \ + | ((lk) & 1) +#define EBD15BI_MASK 0xfff30001 + +/* A BD24 form instruction. */ +#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1)) +#define BD24_MASK BD24 (0x3f, 1, 1) + /* A B form instruction setting the BO field. */ #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) @@ -1641,6 +2205,12 @@ extract_dm (unsigned long insn, #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) +/* A VLE C form instruction. */ +#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1)) +#define C_LK_MASK C_LK(0x7fff, 1) +#define C(x) ((((unsigned long)(x)) & 0xffff)) +#define C_MASK C(0xffff) + /* An Context form instruction. */ #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) #define CTX_MASK CTX(0x3f, 0x7) @@ -1660,10 +2230,30 @@ extract_dm (unsigned long insn, #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) #define EVSEL_MASK EVSEL(0x3f, 0xff) +/* An IA16 form instruction. */ +#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) +#define IA16_MASK IA16(0x3f, 0x1f) + +/* An I16A form instruction. */ +#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) +#define I16A_MASK I16A(0x3f, 0x1f) + +/* An I16L form instruction. */ +#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) +#define I16L_MASK I16L(0x3f, 0x1f) + +/* An IM7 form instruction. */ +#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11) +#define IM7_MASK IM7(0x1f) + /* An M form instruction. */ #define M(op, rc) (OP (op) | ((rc) & 1)) #define M_MASK M (0x3f, 1) +/* An LI20 form instruction. */ +#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15) +#define LI20_MASK LI20(0x3f, 0x1) + /* An M form instruction with the ME field specified. */ #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) @@ -1694,19 +2284,43 @@ extract_dm (unsigned long insn, #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) -/* An VX form instruction. */ +/* An SCI8 form instruction. */ +#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11)) +#define SCI8_MASK SCI8(0x3f, 0x1f) + +/* An SCI8 form instruction. */ +#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23)) +#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) + +/* An SD4 form instruction. This is a 16-bit instruction. */ +#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12) +#define SD4_MASK SD4(0xf) + +/* An SE_IM5 form instruction. This is a 16-bit instruction. */ +#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9)) +#define SE_IM5_MASK SE_IM5(0x3f, 1) + +/* An SE_R form instruction. This is a 16-bit instruction. */ +#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4)) +#define SE_R_MASK SE_R(0x3f, 0x3f) + +/* An SE_RR form instruction. This is a 16-bit instruction. */ +#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8)) +#define SE_RR_MASK SE_RR(0x3f, 3) + +/* A VX form instruction. */ #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) /* The mask for an VX form instruction. */ #define VX_MASK VX(0x3f, 0x7ff) -/* An VA form instruction. */ +/* A VA form instruction. */ #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) /* The mask for an VA form instruction. */ #define VXA_MASK VXA(0x3f, 0x3f) -/* An VXR form instruction. */ +/* A VXR form instruction. */ #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) /* The mask for a VXR form instruction. */ @@ -1715,6 +2329,12 @@ extract_dm (unsigned long insn, /* An X form instruction. */ #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) +/* An EX form instruction. */ +#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) + +/* The mask for an EX form instruction. */ +#define EX_MASK EX (0x3f, 0x7ff) + /* An XX2 form instruction. */ #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2)) @@ -1986,6 +2606,16 @@ extract_dm (unsigned long insn, #define BOU (0x14) +/* The BO16 encodings used in extended VLE conditional branch mnemonics. */ +#define BO16F (0x0) +#define BO16T (0x1) + +/* The BO32 encodings used in extended VLE conditional branch mnemonics. */ +#define BO32F (0x0) +#define BO32T (0x1) +#define BO32DNZ (0x2) +#define BO32DZ (0x3) + /* The BI condition bit encodings used in extended conditional branch mnemonics. */ #define CBLT (0) @@ -2046,11 +2676,11 @@ extract_dm (unsigned long insn, #define MFDEC1 PPC_OPCODE_POWER #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN #define BOOKE PPC_OPCODE_BOOKE -#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_EFS +#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS | PPC_OPCODE_VLE #define PPCE300 PPC_OPCODE_E300 -#define PPCSPE PPC_OPCODE_SPE -#define PPCISEL PPC_OPCODE_ISEL -#define PPCEFS PPC_OPCODE_EFS +#define PPCSPE PPC_OPCODE_SPE | PPC_OPCODE_VLE +#define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE +#define PPCEFS PPC_OPCODE_EFS | PPC_OPCODE_VLE #define PPCBRLK PPC_OPCODE_BRLOCK #define PPCPMR PPC_OPCODE_PMR #define PPCTMR PPC_OPCODE_TMR @@ -2059,9 +2689,10 @@ extract_dm (unsigned long insn, #define E500MC PPC_OPCODE_E500MC #define PPCA2 PPC_OPCODE_A2 #define TITAN PPC_OPCODE_TITAN -#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN +#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE #define E500 PPC_OPCODE_E500 #define E6500 PPC_OPCODE_E6500 +#define PPCVLE PPC_OPCODE_VLE /* The opcode table. @@ -2135,54 +2766,54 @@ const struct powerpc_opcode powerpc_opco {"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}}, {"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, -{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vrlb", VX (4, 4), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vaddubm", VX (4, 0), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmaxub", VX (4, 2), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vrlb", VX (4, 4), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmuloub", VX (4, 8), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vaddfp", VX (4, 10), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, -{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmrghb", VX (4, 12), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}}, -{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, -{"machhwu", XO (4, 12,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhwu", XO (4, 12,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, -{"machhwu.", XO (4, 12,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhwu.", XO (4, 12,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, -{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, -{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, +{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, +{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, -{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, -{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, -{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, -{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, +{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, +{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, -{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, -{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, -{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, +{"vsel", VXA(4, 42), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, -{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, VC}}, -{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VB, SHB}}, +{"vperm", VXA(4, 43), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}}, +{"vsldoi", VXA(4, 44), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, SHB}}, {"ps_sel", A (4, 23,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}}, +{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}}, {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, PPCNONE, {VD, VA, VC, VB}}, +{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}}, {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, @@ -2198,536 +2829,536 @@ const struct powerpc_opcode powerpc_opco {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, -{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vrlh", VX (4, 68), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vadduhm", VX (4, 64), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vrlh", VX (4, 68), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmulouh", VX (4, 72), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vsubfp", VX (4, 74), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, -{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmrghh", VX (4, 76), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, PPCNONE, {FRS,RA,RB,PSWM,PSQM}}, -{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, -{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"mulhhw", XRC(4, 40,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, -{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"machhw", XO (4, 44,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"machhw.", XO (4, 44,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmachhw", XO (4, 46,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmachhw.", XO (4, 46,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"machhw", XO (4, 44,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"machhw.", XO (4, 44,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmachhw", XO (4, 46,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmachhw.", XO (4, 46,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, -{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vrlw", VX (4, 132), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vadduwm", VX (4, 128), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vrlw", VX (4, 132), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmrghw", VX (4, 140), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, -{"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, {"vabsdub", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, -{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"machhws", XO (4, 108,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"machhws.", XO (4, 108,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"machhws", XO (4, 108,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"machhws.", XO (4, 108,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vabsduh", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, -{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vrefp", VX (4, 266), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vslb", VX (4, 260), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmulosb", VX (4, 264), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vrefp", VX (4, 266), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"vmrglb", VX (4, 268), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vpkshus", VX (4, 270), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, -{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"mulchwu", XRC(4, 136,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, -{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"macchwu", XO (4, 140,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"macchwu", XO (4, 140,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vabsduw", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, -{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vslh", VX (4, 324), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmulosh", VX (4, 328), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vrsqrtefp", VX (4, 330), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"vmrglh", VX (4, 332), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vpkswus", VX (4, 334), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"mulchw", XRC(4, 168,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"macchw", XO (4, 172,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"macchw.", XO (4, 172,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"nmacchw", XO (4, 174,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"nmacchw.", XO (4, 174,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vslw", VX (4, 388), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vexptefp", VX (4, 394), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"macchwsu", XO (4, 204,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"vsl", VX (4, 452), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vlogefp", VX (4, 458), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"macchws", XO (4, 236,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"macchws.", XO (4, 236,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmacchws", XO (4, 238,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmacchws.", XO (4, 238,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evaddw", VX (4, 512), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}}, -{"vminub", VX (4, 514), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vslw", VX (4, 388), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vexptefp", VX (4, 394), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"vmrglw", VX (4, 396), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vpkshss", VX (4, 398), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"macchwsu", XO (4, 204,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"vsl", VX (4, 452), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vlogefp", VX (4, 458), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"vpkswss", VX (4, 462), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"macchws", XO (4, 236,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"macchws.", XO (4, 236,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmacchws", XO (4, 238,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmacchws.", XO (4, 238,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evaddiw", VX (4, 514), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB, UIMM}}, +{"vminub", VX (4, 514), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evsubfw", VX (4, 516), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evsubw", VX (4, 516), VX_MASK, PPCSPE, PPCNONE, {RS, RB, RA}}, -{"vsrb", VX (4, 516), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, UIMM, RB}}, +{"vsrb", VX (4, 516), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evsubifw", VX (4, 518), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, UIMM, RB}}, {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, PPCNONE, {RS, RB, UIMM}}, -{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evabs", VX (4, 520), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evneg", VX (4, 521), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evextsb", VX (4, 522), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"vrfin", VX (4, 522), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"evextsh", VX (4, 523), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evrndw", VX (4, 524), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"vspltb", VX (4, 524), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, -{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"brinc", VX (4, 527), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evabs", VX (4, 520), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"vmuleub", VX (4, 520), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evneg", VX (4, 521), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evextsb", VX (4, 522), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"vrfin", VX (4, 522), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"evextsh", VX (4, 523), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evrndw", VX (4, 524), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"vspltb", VX (4, 524), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"vupkhsb", VX (4, 526), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"brinc", VX (4, 527), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, -{"evand", VX (4, 529), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evandc", VX (4, 530), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evxor", VX (4, 534), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmr", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}}, -{"evor", VX (4, 535), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evnor", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evnot", VX (4, 536), VX_MASK, PPCSPE, PPCNONE, {RS, RA, BBA}}, +{"evand", VX (4, 529), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evandc", VX (4, 530), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evxor", VX (4, 534), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmr", VX (4, 535), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, BBA}}, +{"evor", VX (4, 535), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evnor", VX (4, 536), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evnot", VX (4, 536), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, BBA}}, {"get", APU(4, 268,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, -{"eveqv", VX (4, 537), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evorc", VX (4, 539), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evnand", VX (4, 542), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evsrws", VX (4, 545), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, -{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, -{"evslw", VX (4, 548), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evslwi", VX (4, 550), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, -{"evrlw", VX (4, 552), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evsplati", VX (4, 553), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}}, -{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, PPCNONE, {RS, RA, EVUIMM}}, -{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, PPCNONE, {RS, SIMM}}, -{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, -{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, -{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, -{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, -{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"eveqv", VX (4, 537), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evorc", VX (4, 539), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evnand", VX (4, 542), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evsrwu", VX (4, 544), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evsrws", VX (4, 545), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}}, +{"evsrwis", VX (4, 547), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}}, +{"evslw", VX (4, 548), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evslwi", VX (4, 550), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}}, +{"evrlw", VX (4, 552), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evsplati", VX (4, 553), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, SIMM}}, +{"evrlwi", VX (4, 554), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, EVUIMM}}, +{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, SIMM}}, +{"evmergehi", VX (4, 556), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmergelo", VX (4, 557), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"evcmplts", VX (4, 563), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, -{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vminuh", VX (4, 578), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vsrh", VX (4, 580), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vrfiz", VX (4, 586), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"vsplth", VX (4, 588), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, -{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, +{"vadduhs", VX (4, 576), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vminuh", VX (4, 578), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vsrh", VX (4, 580), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vrfiz", VX (4, 586), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"vsplth", VX (4, 588), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vupkhsh", VX (4, 590), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, -{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, PPCNONE, {RS, RA, RB, CRFS}}, +{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB, CRFS}}, {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, -{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vadduws", VX (4, 640), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evfssub", VX (4, 641), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vminuw", VX (4, 642), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"vsrw", VX (4, 644), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vrfip", VX (4, 650), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, -{"vspltw", VX (4, 652), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, -{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, -{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, -{"vupklsb", VX (4, 654), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, -{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, -{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, -{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, -{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, -{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, -{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, -{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, -{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, +{"evfsadd", VX (4, 640), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vadduws", VX (4, 640), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evfssub", VX (4, 641), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vminuw", VX (4, 642), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evfsabs", VX (4, 644), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"vsrw", VX (4, 644), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evfsneg", VX (4, 646), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evfsmul", VX (4, 648), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vrfip", VX (4, 650), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"vspltw", VX (4, 652), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"vupklsb", VX (4, 654), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"evfscfui", VX (4, 656), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, +{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, +{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, +{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, +{"evfsctui", VX (4, 660), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, +{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, +{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, +{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, +{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, {"put", APU(4, 332,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, -{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, PPCNONE, {RS, RB}}, -{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, -{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, -{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, PPCNONE, {CRFD, RA, RB}}, +{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB}}, +{"evfststgt", VX (4, 668), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"evfststlt", VX (4, 669), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"evfststeq", VX (4, 670), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, -{"efsadd", VX (4, 704), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, -{"efssub", VX (4, 705), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, -{"efsabs", VX (4, 708), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, -{"vsr", VX (4, 708), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, -{"efsneg", VX (4, 710), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, -{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"efsmul", VX (4, 712), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, -{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, -{"vrfim", VX (4, 714), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"vupklsh", VX (4, 718), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"efscfd", VX (4, 719), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efscfui", VX (4, 720), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efsctui", VX (4, 724), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efsadd", VX (4, 704), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"efssub", VX (4, 705), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"efsabs", VX (4, 708), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, +{"vsr", VX (4, 708), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"efsnabs", VX (4, 709), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, +{"efsneg", VX (4, 710), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, +{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"efsmul", VX (4, 712), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"efsdiv", VX (4, 713), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vrfim", VX (4, 714), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"efscmplt", VX (4, 717), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"vupklsh", VX (4, 718), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"efscfd", VX (4, 719), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efscfui", VX (4, 720), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efscfsi", VX (4, 721), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efscfuf", VX (4, 722), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efscfsf", VX (4, 723), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efsctui", VX (4, 724), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efsctsi", VX (4, 725), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efsctuf", VX (4, 726), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efsctsf", VX (4, 727), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, -{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efststgt", VX (4, 732), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"efststlt", VX (4, 733), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"efststeq", VX (4, 734), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"efdadd", VX (4, 736), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, -{"efdsub", VX (4, 737), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, -{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdabs", VX (4, 740), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, -{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, -{"efdneg", VX (4, 742), VX_MASK, PPCEFS, PPCNONE, {RS, RA}}, -{"efdmul", VX (4, 744), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, -{"efddiv", VX (4, 745), VX_MASK, PPCEFS, PPCNONE, {RS, RA, RB}}, -{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdctui", VX (4, 756), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, +{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efststgt", VX (4, 732), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"efststlt", VX (4, 733), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"efststeq", VX (4, 734), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"efdadd", VX (4, 736), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"efdsub", VX (4, 737), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdabs", VX (4, 740), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, +{"efdnabs", VX (4, 741), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, +{"efdneg", VX (4, 742), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA}}, +{"efdmul", VX (4, 744), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"efddiv", VX (4, 745), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"efdcfs", VX (4, 751), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdcfui", VX (4, 752), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdctui", VX (4, 756), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdctsi", VX (4, 757), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdctuf", VX (4, 758), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdctsf", VX (4, 759), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, PPCNONE, {RA, FSL}}, -{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, PPCNONE, {RS, RB}}, -{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, PPCNONE, {CRFD, RA, RB}}, -{"evlddx", VX (4, 768), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evldd", VX (4, 769), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, -{"evldwx", VX (4, 770), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vminsb", VX (4, 770), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evldw", VX (4, 771), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, -{"evldhx", VX (4, 772), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vsrab", VX (4, 772), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evldh", VX (4, 773), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, -{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, -{"vcfux", VX (4, 778), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, -{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vspltisb", VX (4, 780), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, -{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, -{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_2, RA}}, -{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, -{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, -{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, -{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, -{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, -{"evstddx", VX (4, 800), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evstdd", VX (4, 801), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, -{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evstdw", VX (4, 803), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, -{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evstdh", VX (4, 805), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_8, RA}}, -{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, -{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evstwho", VX (4, 821), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, -{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, -{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, PPCNONE, {RS, EVUIMM_4, RA}}, -{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vminsh", VX (4, 834), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vsrah", VX (4, 836), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, -{"vspltish", VX (4, 844), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, -{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"mullhw", XRC(4, 424,0), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vminsw", VX (4, 898), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vsraw", VX (4, 900), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, -{"vspltisw", VX (4, 908), VX_MASK, PPCVEC, PPCNONE, {VD, SIMM}}, -{"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, PPCNONE, {VD, VB, UIMM}}, -{"vupklpx", VX (4, 974), VX_MASK, PPCVEC, PPCNONE, {VD, VB}}, -{"maclhws", XO (4, 492,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmaclhws", XO (4, 494,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmaclhws.", XO (4, 494,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"vsububm", VX (4,1024), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vavgub", VX (4,1026), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vand", VX (4,1028), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RB}}, +{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"evlddx", VX (4, 768), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evldd", VX (4, 769), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"evldwx", VX (4, 770), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vminsb", VX (4, 770), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evldw", VX (4, 771), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"evldhx", VX (4, 772), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vsrab", VX (4, 772), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evldh", VX (4, 773), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vmulesb", VX (4, 776), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, +{"vcfux", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vspltisb", VX (4, 780), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, +{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, +{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vpkpx", VX (4, 782), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, +{"mullhwu", XRC(4, 392,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evlwhex", VX (4, 784), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evlwhe", VX (4, 785), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evlwhou", VX (4, 789), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evlwhos", VX (4, 791), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evstddx", VX (4, 800), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evstdd", VX (4, 801), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"evstdwx", VX (4, 802), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evstdw", VX (4, 803), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"evstdhx", VX (4, 804), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evstdh", VX (4, 805), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_8, RA}}, +{"evstwhex", VX (4, 816), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evstwhe", VX (4, 817), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evstwhox", VX (4, 820), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evstwho", VX (4, 821), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evstwwex", VX (4, 824), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evstwwe", VX (4, 825), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"evstwwox", VX (4, 828), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evstwwo", VX (4, 829), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, +{"vaddshs", VX (4, 832), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vminsh", VX (4, 834), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vsrah", VX (4, 836), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmulesh", VX (4, 840), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcfsx", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vspltish", VX (4, 844), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, +{"vupkhpx", VX (4, 846), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"mullhw", XRC(4, 424,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"mullhw.", XRC(4, 424,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"vaddsws", VX (4, 896), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vminsw", VX (4, 898), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vsraw", VX (4, 900), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vctuxs", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vspltisw", VX (4, 908), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, +{"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vupklpx", VX (4, 974), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, +{"maclhws", XO (4, 492,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmaclhws", XO (4, 494,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmaclhws.", XO (4, 494,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"vsububm", VX (4,1024), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vavgub", VX (4,1026), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evmhessf", VX (4,1027), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vand", VX (4,1028), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, -{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vslo", VX (4,1036), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"machhwuo", XO (4, 12,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"machhwuo.", XO (4, 12,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmhossf", VX (4,1031), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmheumi", VX (4,1032), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vslo", VX (4,1036), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"machhwuo", XO (4, 12,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"machhwuo.", XO (4, 12,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, -{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vavguh", VX (4,1090), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vandc", VX (4,1092), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmheumia", VX (4,1064), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vavguh", VX (4,1090), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vandc", VX (4,1092), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, -{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vminfp", VX (4,1098), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vsro", VX (4,1100), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"machhwo", XO (4, 44,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"machhwo.", XO (4, 44,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"nmachhwo", XO (4, 46,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmachhwo.", XO (4, 46,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vminfp", VX (4,1098), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vsro", VX (4,1100), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwssf", VX (4,1107), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"machhwo", XO (4, 44,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evmwumi", VX (4,1112), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"machhwo.", XO (4, 44,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"nmachhwo", XO (4, 46,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmachhwo.", XO (4, 46,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, -{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vavguw", VX (4,1154), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vor", VX (4,1156), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwumia", VX (4,1144), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vavguw", VX (4,1154), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, -{"machhwsuo", XO (4, 76,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"machhwsuo.", XO (4, 76,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"machhwsuo", XO (4, 76,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"machhwsuo.", XO (4, 76,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, -{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evmra", VX (4,1220), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"vxor", VX (4,1220), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evdivws", VX (4,1222), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evmra", VX (4,1220), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"vxor", VX (4,1220), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evdivws", VX (4,1222), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, -{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, PPCNONE, {RS, RA}}, -{"machhwso", XO (4, 108,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"machhwso.", XO (4, 108,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmachhwso", XO (4, 110,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmachhwso.", XO (4, 110,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"evdivwu", VX (4,1223), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"machhwso", XO (4, 108,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"machhwso.", XO (4, 108,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmachhwso", XO (4, 110,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmachhwso.", XO (4, 110,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, -{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vnor", VX (4,1284), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vavgsb", VX (4,1282), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vnor", VX (4,1284), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, -{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"macchwuo", XO (4, 140,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"macchwuo.", XO (4, 140,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"macchwuo", XO (4, 140,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"macchwuo.", XO (4, 140,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vavgsh", VX (4,1346), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, -{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"macchwo", XO (4, 172,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"macchwo.", XO (4, 172,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"nmacchwo", XO (4, 174,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmacchwo.", XO (4, 174,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, +{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"macchwo", XO (4, 172,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"macchwo.", XO (4, 172,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"nmacchwo", XO (4, 174,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmacchwo.", XO (4, 174,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vavgsw", VX (4,1410), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, -{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"macchwsuo", XO (4, 204,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"macchwsuo.", XO (4, 204,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"macchwsuo", XO (4, 204,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"macchwsuo.", XO (4, 204,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, -{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"macchwso", XO (4, 236,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"macchwso.", XO (4, 236,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, PPCNONE, {RS, RA, RB}}, -{"nmacchwso", XO (4, 238,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmacchwso.", XO (4, 238,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"vsububs", VX (4,1536), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"mfvscr", VX (4,1540), VX_MASK, PPCVEC, PPCNONE, {VD}}, -{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"macchwso", XO (4, 236,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evmwumian", VX (4,1496), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"macchwso.", XO (4, 236,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"nmacchwso", XO (4, 238,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmacchwso.", XO (4, 238,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"vsububs", VX (4,1536), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"mfvscr", VX (4,1540), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD}}, +{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, -{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"mtvscr", VX (4,1604), VX_MASK, PPCVEC, PPCNONE, {VB}}, -{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"mtvscr", VX (4,1604), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VB}}, +{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, -{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsubuws", VX (4,1664), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, -{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, -{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, -{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"vsubshs", VX (4,1856), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, -{"maclhwo", XO (4, 428,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"maclhwo.", XO (4, 428,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmaclhwo", XO (4, 430,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, +{"maclhwo", XO (4, 428,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"maclhwo.", XO (4, 428,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmaclhwo", XO (4, 430,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmaclhwo.", XO (4, 430,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"vsubsws", VX (4,1920), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, -{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, -{"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vsumsws", VX (4,1928), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, -{"maclhwso", XO (4, 492,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"maclhwso.", XO (4, 492,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmaclhwso", XO (4, 494,1,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, -{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"maclhwso", XO (4, 492,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"maclhwso.", XO (4, 492,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmaclhwso", XO (4, 494,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"nmaclhwso.", XO (4, 494,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, PPCNONE, {RA, RB}}, {"mulli", OP(7), OP_MASK, PPCCOM, PPCNONE, {RT, RA, SI}}, @@ -3547,62 +4178,62 @@ const struct powerpc_opcode powerpc_opco {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, -{"cmp", X(31,0), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}}, +{"cmp", X(31,0), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}}, {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, -{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, PPCNONE, {RA, RB}}, +{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, -{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, PPCNONE, {0}}, -{"tw", X(31,4), X_MASK, PPCCOM, PPCNONE, {TO, RA, RB}}, +{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM|PPCVLE, PPCNONE, {0}}, +{"tw", X(31,4), X_MASK, PPCCOM|PPCVLE, PPCNONE, {TO, RA, RB}}, {"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}}, {"lvsl", X(31,6), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, {"lvebx", X(31,7), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}}, -{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"subc", XO(31,8,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}}, +{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}}, - -{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, -{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, - -{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}}, + +{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, + +{"addc", XO(31,10,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"a", XO(31,10,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, -{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"mulhwu", XO(31,11,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, {"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}}, @@ -3612,43 +4243,43 @@ const struct powerpc_opcode powerpc_opco {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, PPCNONE, {T, RA0, RB}}, {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}}, -{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}}, +{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM|PPCVLE, POWER4, {RT}}, {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}}, -{"lwarx", X(31,20), XEH_MASK, PPC, PPCNONE, {RT, RA0, RB, EH}}, - -{"ldx", X(31,21), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}}, - -{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}}, - -{"lwzx", X(31,23), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, +{"lwarx", X(31,20), XEH_MASK, PPC|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, + +{"ldx", X(31,21), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}}, + +{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA, RB}}, + +{"lwzx", X(31,23), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}}, {"lx", X(31,23), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"slw", XRC(31,24,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"slw", XRC(31,24,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"sl", XRC(31,24,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, -{"slw.", XRC(31,24,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"slw.", XRC(31,24,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"sl.", XRC(31,24,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, -{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, +{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}}, {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, -{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, +{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}}, {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, {"sld", XRC(31,27,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, {"sld.", XRC(31,27,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, -{"and", XRC(31,28,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, -{"and.", XRC(31,28,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"and", XRC(31,28,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, +{"and.", XRC(31,28,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, -{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, -{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, +{"ldepx", X(31,29), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"lwepx", X(31,31), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA, RB}}, -{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, PPCNONE, {OBF, RA, RB}}, +{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM|PPCVLE, PPCNONE, {OBF, RA, RB}}, {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, PPCNONE, {OBF, RA, RB}}, -{"cmpl", X(31,32), XCMP_MASK, PPC, PPCNONE, {BF, L, RA, RB}}, +{"cmpl", X(31,32), XCMP_MASK, PPC|PPCVLE, PPCNONE, {BF, L, RA, RB}}, {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, {"lvsr", X(31,38), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, @@ -3665,33 +4296,33 @@ const struct powerpc_opcode powerpc_opco {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE, {RT, RA, RB, CRB}}, -{"subf", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, -{"sub", XO(31,40,0,0), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, -{"subf.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, -{"sub.", XO(31,40,0,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, +{"subf", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"sub", XO(31,40,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}}, +{"subf.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"sub.", XO(31,40,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RB, RA}}, {"eratilx", X(31,51), X_MASK, PPCA2, PPCNONE, {ERAT_T, RA, RB}}, {"lbarx", X(31,52), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}}, -{"ldux", X(31,53), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}}, - -{"dcbst", X(31,54), XRT_MASK, PPC, PPCNONE, {RA, RB}}, - -{"lwzux", X(31,55), X_MASK, PPCCOM, PPCNONE, {RT, RAL, RB}}, +{"ldux", X(31,53), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}}, + +{"dcbst", X(31,54), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA, RB}}, + +{"lwzux", X(31,55), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RAL, RB}}, {"lux", X(31,55), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, -{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, +{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}}, +{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}}, -{"andc", XRC(31,60,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, -{"andc.", XRC(31,60,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"andc", XRC(31,60,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, +{"andc.", XRC(31,60,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}}, {"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}}, -{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2, PPCNONE, {WC}}, - -{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}}, +{"wait", X(31,62), XWC_MASK, POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}}, + +{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA, RB}}, {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, @@ -3707,38 +4338,38 @@ const struct powerpc_opcode powerpc_opco {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, -{"td", X(31,68), X_MASK, PPC64, PPCNONE, {TO, RA, RB}}, +{"td", X(31,68), X_MASK, PPC64|PPCVLE, PPCNONE, {TO, RA, RB}}, {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, -{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, - -{"mulhw", XO(31,75,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, -{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"mulhd", XO(31,73,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, + +{"mulhw", XO(31,75,0,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"mulhw.", XO(31,75,0,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}}, {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE, {RA, RS, RB}}, {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, PPCNONE, {SR, RS}}, -{"mfmsr", X(31,83), XRARB_MASK, COM, PPCNONE, {RT}}, - -{"ldarx", X(31,84), XEH_MASK, PPC64, PPCNONE, {RT, RA0, RB, EH}}, +{"mfmsr", X(31,83), XRARB_MASK, COM|PPCVLE, PPCNONE, {RT}}, + +{"ldarx", X(31,84), XEH_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB, EH}}, {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA, RB}}, -{"dcbf", X(31,86), XLRT_MASK, PPC, PPCNONE, {RA, RB, L}}, - -{"lbzx", X(31,87), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, +{"dcbf", X(31,86), XLRT_MASK, PPC|PPCVLE, PPCNONE, {RA, RB, L}}, -{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, +{"lbzx", X(31,87), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}}, + +{"lbepx", X(31,95), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA, RB}}, {"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}}, {"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"neg", XO(31,104,0,0), XORB_MASK, COM, PPCNONE, {RT, RA}}, -{"neg.", XO(31,104,0,1), XORB_MASK, COM, PPCNONE, {RT, RA}}, +{"neg", XO(31,104,0,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}}, +{"neg.", XO(31,104,0,1), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}}, {"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, @@ -3751,32 +4382,32 @@ const struct powerpc_opcode powerpc_opco {"clf", X(31,118), XTO_MASK, POWER, PPCNONE, {RA, RB}}, -{"lbzux", X(31,119), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, - -{"popcntb", X(31,122), XRB_MASK, POWER5, PPCNONE, {RA, RS}}, +{"lbzux", X(31,119), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}}, + +{"popcntb", X(31,122), XRB_MASK, POWER5|PPCVLE, PPCNONE, {RA, RS}}, {"not", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, -{"nor", XRC(31,124,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"nor", XRC(31,124,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"not.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, -{"nor.", XRC(31,124,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, - -{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}}, +{"nor.", XRC(31,124,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, -{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}}, - -{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, +{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA, RB}}, + +{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}}, + +{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}}, {"stvebx", X(31,135), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"adde", XO(31,138,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"mviwsplt", X(31,142), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}}, @@ -3787,16 +4418,16 @@ const struct powerpc_opcode powerpc_opco {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}}, {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}}, -{"mtmsr", X(31,146), XRLARB_MASK, COM, PPCNONE, {RS, A_L}}, +{"mtmsr", X(31,146), XRLARB_MASK, COM|PPCVLE, PPCNONE, {RS, A_L}}, {"eratsx", XRC(31,147,0), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}}, {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}}, -{"stdx", X(31,149), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}}, - -{"stwcx.", XRC(31,150,1), X_MASK, PPC, PPCNONE, {RS, RA0, RB}}, - -{"stwx", X(31,151), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, +{"stdx", X(31,149), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}}, + +{"stwcx.", XRC(31,150,1), X_MASK, PPC|PPCVLE, PPCNONE, {RS, RA0, RB}}, + +{"stwx", X(31,151), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}}, {"stx", X(31,151), X_MASK, PWRCOM, PPCNONE, {RS, RA, RB}}, {"slq", XRC(31,152,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, @@ -3807,13 +4438,13 @@ const struct powerpc_opcode powerpc_opco {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS}}, -{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}}, - -{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}}, - -{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {E}}, - -{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, +{"stdepx", X(31,157), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA, RB}}, + +{"stwepx", X(31,159), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA, RB}}, + +{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {E}}, + +{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}}, {"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, @@ -3824,11 +4455,11 @@ const struct powerpc_opcode powerpc_opco {"eratre", X(31,179), X_MASK, PPCA2, PPCNONE, {RT, RA, WS}}, -{"stdux", X(31,181), X_MASK, PPC64, PPCNONE, {RS, RAS, RB}}, +{"stdux", X(31,181), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RAS, RB}}, {"wchkall", X(31,182), X_MASK, PPCA2, PPCNONE, {OBF}}, -{"stwux", X(31,183), X_MASK, PPCCOM, PPCNONE, {RS, RAS, RB}}, +{"stwux", X(31,183), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RAS, RB}}, {"stux", X(31,183), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, {"sliq", XRC(31,184,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, @@ -3841,17 +4472,17 @@ const struct powerpc_opcode powerpc_opco {"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE, {RB}}, +{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}}, {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, @@ -3859,9 +4490,9 @@ const struct powerpc_opcode powerpc_opco {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, PPCNONE, {RT, RA0, RB}}, -{"stdcx.", XRC(31,214,1), X_MASK, PPC64, PPCNONE, {RS, RA0, RB}}, - -{"stbx", X(31,215), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, +{"stdcx.", XRC(31,214,1), X_MASK, PPC64|PPCVLE, PPCNONE, {RS, RA0, RB}}, + +{"stbx", X(31,215), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}}, {"sllq", XRC(31,216,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"sllq.", XRC(31,216,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, @@ -3869,41 +4500,41 @@ const struct powerpc_opcode powerpc_opco {"sleq", XRC(31,217,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"sleq.", XRC(31,217,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, -{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}}, - -{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, +{"stbepx", X(31,223), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA, RB}}, + +{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}}, {"stvx", X(31,231), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"mulld", XO(31,233,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, -{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, - -{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"mulld", XO(31,233,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"mulld.", XO(31,233,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, + +{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, -{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE, {RB}}, +{"msgclr", XRTRA(31,238,0,0),XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RB}}, {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}}, {"dcbtst", X(31,246), X_MASK, POWER4, PPCNONE, {RA, RB, CT}}, -{"dcbtst", X(31,246), X_MASK, PPC, POWER4, {CT, RA, RB}}, - -{"stbux", X(31,247), X_MASK, COM, PPCNONE, {RS, RAS, RB}}, +{"dcbtst", X(31,246), X_MASK, PPC|PPCVLE, POWER4, {CT, RA, RB}}, + +{"stbux", X(31,247), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}}, {"slliq", XRC(31,248,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, {"slliq.", XRC(31,248,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, @@ -3912,7 +4543,7 @@ const struct powerpc_opcode powerpc_opco {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, -{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, +{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RS, RA}}, {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}}, {"lvexbx", X(31,261), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, @@ -3925,9 +4556,9 @@ const struct powerpc_opcode powerpc_opco {"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, -{"add", XO(31,266,0,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"add", XO(31,266,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"add.", XO(31,266,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, PPCNONE, {0}}, @@ -3941,18 +4572,18 @@ const struct powerpc_opcode powerpc_opco {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, PPCNONE, {RA, RB}}, {"dcbt", X(31,278), X_MASK, POWER4, PPCNONE, {RA, RB, CT}}, -{"dcbt", X(31,278), X_MASK, PPC, POWER4, {CT, RA, RB}}, - -{"lhzx", X(31,279), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, +{"dcbt", X(31,278), X_MASK, PPC|PPCVLE, POWER4, {CT, RA, RB}}, + +{"lhzx", X(31,279), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}}, {"cdtbcd", X(31,282), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, -{"eqv", XRC(31,284,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, -{"eqv.", XRC(31,284,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"eqv", XRC(31,284,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, +{"eqv.", XRC(31,284,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, -{"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}}, +{"mfdcrux", X(31,291), X_MASK, PPC464|PPCVLE, PPCNONE, {RS, RA}}, {"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, {"lvepx", X(31,295), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, @@ -3962,12 +4593,12 @@ const struct powerpc_opcode powerpc_opco {"eciwx", X(31,310), X_MASK, PPC, TITAN, {RT, RA, RB}}, -{"lhzux", X(31,311), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, +{"lhzux", X(31,311), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}}, {"cbcdtd", X(31,314), XRB_MASK, POWER6, PPCNONE, {RA, RS}}, -{"xor", XRC(31,316,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, -{"xor.", XRC(31,316,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"xor", XRC(31,316,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, +{"xor.", XRC(31,316,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, @@ -4005,7 +4636,7 @@ const struct powerpc_opcode powerpc_opco {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, PPCNONE, {RT}}, {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, PPCNONE, {RT}}, {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, PPCNONE, {RT}}, -{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT, SPR}}, +{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {RT, SPR}}, {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}}, {"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, @@ -4017,16 +4648,16 @@ const struct powerpc_opcode powerpc_opco {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, -{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}}, +{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}}, {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}}, {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}}, -{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}}, +{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}}, {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, PPCNONE, {RT}}, -{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, PPCNONE, {RT}}, -{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, PPCNONE, {RT}}, +{"mflr", XSPR(31,339, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}}, +{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}}, {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, PPCNONE, {RT}}, {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}}, @@ -4036,12 +4667,12 @@ const struct powerpc_opcode powerpc_opco {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, PPCNONE, {RT}}, {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, PPCNONE, {RT}}, {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, PPCNONE, {RT}}, -{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, PPCNONE, {RT}}, {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, PPCNONE, {RT}}, {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, PPCNONE, {RT}}, @@ -4059,53 +4690,53 @@ const struct powerpc_opcode powerpc_opco {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, PPCNONE, {RT}}, {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, PPCNONE, {RT}}, {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, PPCNONE, {RT}}, -{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, PPCNONE, {RT, SPRG}}, -{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, -{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, -{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, -{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RT}}, -{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, PPCNONE, {RT}}, -{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, PPCNONE, {RT}}, -{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, PPCNONE, {RT}}, -{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, PPCNONE, {RT}}, +{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE, {RT, SPRG}}, +{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mftb", XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}}, +{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}}, +{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}}, +{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}}, {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, PPCNONE, {RT}}, {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, -{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, PPCNONE, {RT}}, -{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, PPCNONE, {RT}}, -{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, PPCNONE, {RT}}, +{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RT}}, +{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, +{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RT}}, {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, PPCNONE, {RT}}, {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, PPCNONE, {RT}}, {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, PPCNONE, {RT}}, @@ -4216,13 +4847,13 @@ const struct powerpc_opcode powerpc_opco {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, PPCNONE, {RT}}, {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, PPCNONE, {RT}}, {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, PPCNONE, {RT}}, -{"mfspr", X(31,339), X_MASK, COM, PPCNONE, {RT, SPR}}, - -{"lwax", X(31,341), X_MASK, PPC64, PPCNONE, {RT, RA0, RB}}, +{"mfspr", X(31,339), X_MASK, COM|PPCVLE, PPCNONE, {RT, SPR}}, + +{"lwax", X(31,341), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA0, RB}}, {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, -{"lhax", X(31,343), X_MASK, COM, PPCNONE, {RT, RA0, RB}}, +{"lhax", X(31,343), X_MASK, COM|PPCVLE, PPCNONE, {RT, RA0, RB}}, {"lvxl", X(31,359), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, @@ -4238,20 +4869,20 @@ const struct powerpc_opcode powerpc_opco {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371, {RT}}, {"mftb", X(31,371), X_MASK, PPC|PPCA2, NO371|POWER7, {RT, TBR}}, -{"lwaux", X(31,373), X_MASK, PPC64, PPCNONE, {RT, RAL, RB}}, +{"lwaux", X(31,373), X_MASK, PPC64|PPCVLE, PPCNONE, {RT, RAL, RB}}, {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, PPCNONE, {RA, RB, STRM}}, -{"lhaux", X(31,375), X_MASK, COM, PPCNONE, {RT, RAL, RB}}, +{"lhaux", X(31,375), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}}, {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, PPCNONE, {RA, RS}}, {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, -{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}}, +{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2|PPCVLE, PPCNONE, {RA, RS}}, {"stvexbx", X(31,389), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, -{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, +{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}}, {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, @@ -4266,14 +4897,14 @@ const struct powerpc_opcode powerpc_opco {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}}, {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}}, -{"sthx", X(31,407), X_MASK, COM, PPCNONE, {RS, RA0, RB}}, +{"sthx", X(31,407), X_MASK, COM|PPCVLE, PPCNONE, {RS, RA0, RB}}, -{"orc", XRC(31,412,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, -{"orc.", XRC(31,412,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"orc", XRC(31,412,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, +{"orc.", XRC(31,412,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, -{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, PPCNONE, {RS, RA, RB}}, +{"sthepx", X(31,415), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA, RB}}, -{"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}}, +{"mtdcrux", X(31,419), X_MASK, PPC464|PPCVLE, PPCNONE, {RA, RS}}, {"stvexhx", X(31,421), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, @@ -4288,16 +4919,16 @@ const struct powerpc_opcode powerpc_opco {"ecowx", X(31,438), X_MASK, PPC, TITAN, {RT, RA, RB}}, -{"sthux", X(31,439), X_MASK, COM, PPCNONE, {RS, RAS, RB}}, +{"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}}, {"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}}, {"miso", 0x7f5ad378, 0xffffffff, E6500, PPCNONE, {0}}, -{"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, -{"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, -{"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, -{"or.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"mr", XRC(31,444,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RBS}}, +{"or", XRC(31,444,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, +{"mr.", XRC(31,444,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RBS}}, +{"or.", XRC(31,444,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, PPCNONE, {RS}}, {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, PPCNONE, {RS}}, @@ -4333,16 +4964,16 @@ const struct powerpc_opcode powerpc_opco {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, PPCNONE, {RS}}, {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, PPCNONE, {RS}}, {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, PPCNONE, {RS}}, -{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {SPR, RS}}, +{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN, {SPR, RS}}, {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}}, {"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}}, -{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}}, - -{"divdu", XO(31,457,0,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, -{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}}, + +{"divdu", XO(31,457,0,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"divdu.", XO(31,457,0,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, {"divwu", XO(31,459,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, {"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, @@ -4351,9 +4982,9 @@ const struct powerpc_opcode powerpc_opco {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}}, {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}}, -{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}}, -{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, PPCNONE, {RS}}, -{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, PPCNONE, {RS}}, +{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, +{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, +{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, PPCNONE, {RS}}, {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}}, @@ -4362,16 +4993,16 @@ const struct powerpc_opcode powerpc_opco {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, PPCNONE, {RS}}, {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, PPCNONE, {RS}}, {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}}, -{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, PPCNONE, {RS}}, -{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, PPCNONE, {RS}}, +{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, +{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, PPCNONE, {RS}}, -{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, PPCNONE, {RS}}, {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, PPCNONE, {RS}}, {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, PPCNONE, {RS}}, @@ -4389,50 +5020,50 @@ const struct powerpc_opcode powerpc_opco {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, PPCNONE, {RS}}, {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, PPCNONE, {RS}}, {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, PPCNONE, {RS}}, -{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, PPCNONE, {SPRG, RS}}, -{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, PPCNONE, {RS}}, -{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, PPCNONE, {RS}}, -{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, PPCNONE, {RS}}, -{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, PPCNONE, {RS}}, -{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, -{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, -{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, -{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE, {RS}}, +{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC|PPCVLE, PPCNONE, {SPRG, RS}}, +{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}}, +{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}}, +{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}}, +{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE, PPCNONE, {RS}}, +{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE, {RS}}, {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, PPCNONE, {RS}}, {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, PPCNONE, {RS}}, {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, PPCNONE, {RS}}, -{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, PPCNONE, {RS}}, -{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, PPCNONE, {RS}}, +{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, +{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE, PPCNONE, {RS}}, {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, PPCNONE, {RS}}, {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, PPCNONE, {RS}}, {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, PPCNONE, {RS}}, @@ -4444,8 +5075,8 @@ const struct powerpc_opcode powerpc_opco {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, PPCNONE, {RS}}, {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}}, -{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, -{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, +{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE, {RS}}, +{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE, PPCNONE, {RS}}, {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, PPCNONE, {RS}}, {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, PPCNONE, {RS}}, {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, PPCNONE, {RS}}, @@ -4510,18 +5141,18 @@ const struct powerpc_opcode powerpc_opco {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, PPCNONE, {RS}}, {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, PPCNONE, {RS}}, {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, PPCNONE, {RS}}, -{"mtspr", X(31,467), X_MASK, COM, PPCNONE, {SPR, RS}}, +{"mtspr", X(31,467), X_MASK, COM|PPCVLE, PPCNONE, {SPR, RS}}, + +{"dcbi", X(31,470), XRT_MASK, PPC|PPCVLE, PPCNONE, {RA, RB}}, -{"dcbi", X(31,470), XRT_MASK, PPC, PPCNONE, {RA, RB}}, - -{"nand", XRC(31,476,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, -{"nand.", XRC(31,476,1), X_MASK, COM, PPCNONE, {RA, RS, RB}}, +{"nand", XRC(31,476,0), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, +{"nand.", XRC(31,476,1), X_MASK, COM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"dsn", X(31,483), XRT_MASK, E500MC, PPCNONE, {RA, RB}}, {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA, RB}}, -{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, +{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}}, {"stvxl", X(31,487), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, @@ -4553,33 +5184,33 @@ const struct powerpc_opcode powerpc_opco {"lvlx", X(31,519), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}}, -{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"subco", XO(31,8,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}}, +{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RB, RA}}, - -{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RB, RA}}, + +{"addco", XO(31,10,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"clcs", X(31,531), XRB_MASK, M601, PPCNONE, {RT, RA}}, {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}}, -{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}}, +{"lswx", X(31,533), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RA0, RB}}, {"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}}, +{"lwbrx", X(31,534), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA0, RB}}, {"lbrx", X(31,534), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, -{"srw", XRC(31,536,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"srw", XRC(31,536,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"sr", XRC(31,536,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, -{"srw.", XRC(31,536,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"srw.", XRC(31,536,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"sr.", XRC(31,536,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, {"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, @@ -4605,7 +5236,7 @@ const struct powerpc_opcode powerpc_opco {"subfo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, {"subo.", XO(31,40,1,1), XO_MASK, PPC, PPCNONE, {RT, RB, RA}}, -{"tlbsync", X(31,566), 0xffffffff, PPC, PPCNONE, {0}}, +{"tlbsync", X(31,566), 0xffffffff, PPC|PPCVLE, PPCNONE, {0}}, {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, @@ -4619,13 +5250,13 @@ const struct powerpc_opcode powerpc_opco {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, -{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RA0, NBI}}, +{"lswi", X(31,597), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RT, RA0, NB}}, {"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}}, {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}}, {"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}}, -{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, +{"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476, {LS}}, {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}}, {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, {"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}}, @@ -4634,7 +5265,7 @@ const struct powerpc_opcode powerpc_opco {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, -{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, PPCNONE, {FRT, RA, RB}}, +{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRT, RA, RB}}, {"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, @@ -4659,24 +5290,24 @@ const struct powerpc_opcode powerpc_opco {"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}}, -{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, +{"stswx", X(31,661), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, RB}}, {"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, -{"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}}, +{"stwbrx", X(31,662), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RS, RA0, RB}}, {"stbrx", X(31,662), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}}, {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, @@ -4709,17 +5340,17 @@ const struct powerpc_opcode powerpc_opco {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, -{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, +{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, +{"stswi", X(31,725), X_MASK, PPCCOM|PPCVLE, E500|E500MC, {RS, RA0, NB}}, {"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}}, {"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, @@ -4733,7 +5364,7 @@ const struct powerpc_opcode powerpc_opco {"sreq.", XRC(31,729,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, -{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, PPCNONE, {FRS, RA, RB}}, +{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {FRS, RA, RB}}, {"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, @@ -4746,8 +5377,8 @@ const struct powerpc_opcode powerpc_opco {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, -{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, -{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"mulldo", XO(31,233,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, @@ -4775,14 +5406,14 @@ const struct powerpc_opcode powerpc_opco {"dozo", XO(31,264,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"dozo.", XO(31,264,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, -{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"addo", XO(31,266,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, +{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, -{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}}, +{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA, RB}}, {"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, @@ -4791,9 +5422,9 @@ const struct powerpc_opcode powerpc_opco {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA, RB}}, {"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, -{"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"sraw", XRC(31,792,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, -{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}}, +{"sraw.", XRC(31,792,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, RB}}, {"sra.", XRC(31,792,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}}, {"srad", XRC(31,794,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, @@ -4815,13 +5446,13 @@ const struct powerpc_opcode powerpc_opco {"lfqux", X(31,823), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}}, -{"srawi", XRC(31,824,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, +{"srawi", XRC(31,824,0), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, SH}}, {"srai", XRC(31,824,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}}, -{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, PPCNONE, {RA, RS, SH}}, +{"srawi.", XRC(31,824,1), X_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS, SH}}, {"srai.", XRC(31,824,1), X_MASK, PWRCOM, PPCNONE, {RA, RS, SH}}, -{"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, -{"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, +{"sradi", XS(31,413,0), XS_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, SH6}}, +{"sradi.", XS(31,413,1), XS_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS, SH6}}, {"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, @@ -4837,8 +5468,8 @@ const struct powerpc_opcode powerpc_opco {"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, -{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, PPCNONE, {MO}}, -{"eieio", XMBAR(31,854,1),0xffffffff, E500, PPCNONE, {0}}, +{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {MO}}, +{"eieio", XMBAR(31,854,1),0xffffffff, E500, PPCNONE, {0}}, {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, PPCNONE, {0}}, {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}}, @@ -4883,9 +5514,9 @@ const struct powerpc_opcode powerpc_opco {"srea", XRC(31,921,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"srea.", XRC(31,921,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, -{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, +{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}}, {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, -{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, PPCNONE, {RA, RS}}, +{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RS}}, {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, PPCNONE, {RA, RS}}, {"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, @@ -4917,19 +5548,19 @@ const struct powerpc_opcode powerpc_opco {"sraiq", XRC(31,952,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, {"sraiq.", XRC(31,952,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, -{"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}}, -{"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}}, +{"extsb", XRC(31,954,0), XRB_MASK, PPC|PPCVLE, PPCNONE, {RA, RS}}, +{"extsb.", XRC(31,954,1), XRB_MASK, PPC|PPCVLE, PPCNONE, {RA, RS}}, {"stvflxl", X(31,965), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}}, -{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}}, - -{"divduo", XO(31,457,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, -{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, - -{"divwuo", XO(31,459,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, -{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, +{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE, {CT}}, + +{"divduo", XO(31,457,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"divduo.", XO(31,457,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, + +{"divwuo", XO(31,459,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"divwuo.", XO(31,459,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, @@ -4944,23 +5575,24 @@ const struct powerpc_opcode powerpc_opco {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, -{"extsw", XRC(31,986,0), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, -{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, PPCNONE, {RA, RS}}, +{"extsw", XRC(31,986,0), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}}, +{"extsw.", XRC(31,986,1), XRB_MASK, PPC64|PPCVLE, PPCNONE, {RA, RS}}, -{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}}, +{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA, RB}}, {"stvswxl", X(31,997), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, -{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}}, +{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA, RB}}, {"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, {"nabso.", XO(31,488,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, -{"divdo", XO(31,489,1,0), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, -{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, PPCNONE, {RT, RA, RB}}, +{"divdo", XO(31,489,1,0), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"divdo.", XO(31,489,1,1), XO_MASK, PPC64|PPCVLE, PPCNONE, {RT, RA, RB}}, + +{"divwo", XO(31,491,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"divwo.", XO(31,491,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, -{"divwo", XO(31,491,1,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, -{"divwo.", XO(31,491,1,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, @@ -4969,7 +5601,7 @@ const struct powerpc_opcode powerpc_opco {"dcbz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}}, {"dclz", X(31,1014), XRT_MASK, PPC, PPCNONE, {RA, RB}}, -{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}}, +{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA, RB}}, {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA, RB}}, @@ -5537,6 +6169,236 @@ const struct powerpc_opcode powerpc_opco const int powerpc_num_opcodes = sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); +/* The VLE opcode table. + + The format of this opcode table is the same as the main opcode table. */ + +const struct powerpc_opcode vle_opcodes[] = { + +{"se_illegal", C(0), C_MASK, PPCVLE, PPCNONE, {}}, +{"se_isync", C(1), C_MASK, PPCVLE, PPCNONE, {}}, +{"se_sc", C(2), C_MASK, PPCVLE, PPCNONE, {}}, +{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, PPCNONE, {}}, +{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, PPCNONE, {}}, +{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, PPCNONE, {}}, +{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, PPCNONE, {}}, +{"se_rfi", C(8), C_MASK, PPCVLE, PPCNONE, {}}, +{"se_rfci", C(9), C_MASK, PPCVLE, PPCNONE, {}}, +{"se_rfdi", C(10), C_MASK, PPCVLE, PPCNONE, {}}, +{"se_rfmci", C(11), C_MASK, PPCVLE, PPCNONE, {}}, +{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, +{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, +{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, +{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, +{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, +{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, +{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, +{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, +{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, +{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, PPCNONE, {RX}}, +{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, PPCNONE, {ARX, RY}}, +{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, ARY}}, +{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, + +{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}}, +{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, PPCNONE, {CRD32, RA, SCLSCI8}}, +{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, +{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}}, +{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, +{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, +{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}}, +{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, +{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8N}}, +{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, +{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, +{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, PPCNONE, {RT, RA, SCLSCI8}}, +{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, +{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, +{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, PPCNONE, {0}}, +{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, +{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, +{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, +{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, PPCNONE, {RA, RS, SCLSCI8}}, +{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, +{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, +{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, +{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, +{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, +{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, +{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, +{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, +{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, PPCNONE, {RT, D8, RA0}}, +{"e_add16i", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, RA, SI}}, +{"e_la", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, +{"e_sub16i", OP(7), OP_MASK, PPCVLE, PPCNONE, {RT, RA, NSI}}, + +{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}}, +{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}}, +{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}}, +{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, OIMM5}}, +{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, +{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, +{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, + +{"e_lbz", OP(12), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, +{"e_stb", OP(13), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, +{"e_lha", OP(14), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, + +{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, PPCNONE, {0}}, +{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, PPCNONE, {RX, RY}}, +{"se_li", IM7(9), IM7_MASK, PPCVLE, PPCNONE, {RX, UI7}}, + +{"e_lwz", OP(20), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, +{"e_stw", OP(21), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, +{"e_lhz", OP(22), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, +{"e_sth", OP(23), OP_MASK, PPCVLE, PPCNONE, {RT, D, RA0}}, + +{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, +{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, +{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, +{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, +{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, +{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, +{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, PPCNONE, {RX, UI5}}, + +{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}}, +{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}}, +{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}}, +{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}}, +{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, PPCNONE, {RD, VLEUIMML}}, +{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, PPCNONE, {RA, VLEUIMM}}, +{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, +{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, PPCNONE, {RA, VLEUIMM}}, +{"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, +{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, +{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, +{"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, +{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, PPCNONE, {RA, VLENSIMM}}, +{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, +{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, PPCNONE, {RA, VLENSIMM}}, +{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, PPCNONE, {RA, VLESIMM}}, +{"e_li", LI20(28,0), LI20_MASK, PPCVLE, PPCNONE, {RT, IMM20}}, +{"e_rlwimi", M(29,0), M_MASK, PPCVLE, PPCNONE, {RA, RS, SH, MB, ME}}, +{"e_rlwinm", M(29,1), M_MASK, PPCVLE, PPCNONE, {RA, RT, SH, MBE, ME}}, +{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, PPCNONE, {B24}}, +{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, PPCNONE, {B24}}, +{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, PPCNONE, {B15}}, +{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, PPCNONE, {B15}}, +{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, PPCNONE, {B15}}, +{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, PPCNONE, {B15}}, +{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, PPCNONE, {CRS,B15}}, +{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, PPCNONE, {BO32, BI32, B15}}, +{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, PPCNONE, {BO32, BI32, B15}}, + +{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}}, +{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}}, +{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}}, +{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, PPCNONE, {BI32,B15}}, + +{"e_cmph", X(31,14), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}}, +{"e_cmphl", X(31,46), X_MASK, PPCVLE, PPCNONE, {CRD, RA, RB}}, +{"e_crandc", XL(31,129), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, +{"e_crnand", XL(31,225), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, +{"e_crnot", XL(31,33), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}}, +{"e_crnor", XL(31,33), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, +{"e_crclr", XL(31,193), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}}, +{"e_crxor", XL(31,193), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, +{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, PPCNONE, {CRD, CR}}, +{"e_slwi", EX(31,112), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, +{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, + +{"e_crand", XL(31,257), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, + +{"e_rlw", EX(31,560), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}}, +{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, PPCNONE, {RA, RS, RB}}, + +{"e_crset", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BAT, BBA}}, +{"e_creqv", XL(31,289), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, + +{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, +{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, + +{"e_crorc", XL(31,417), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, + +{"e_crmove", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BBA}}, +{"e_cror", XL(31,449), XL_MASK, PPCVLE, PPCNONE, {BT, BA, BB}}, + +{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, PPCNONE, {RS}}, + +{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, +{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, PPCNONE, {RA, RS, SH}}, + +{"se_lbz", SD4(8), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}}, + +{"se_stb", SD4(9), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SD, RX}}, + +{"se_lhz", SD4(10), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}}, + +{"se_sth", SD4(11), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDH, RX}}, + +{"se_lwz", SD4(12), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}}, + +{"se_stw", SD4(13), SD4_MASK, PPCVLE, PPCNONE, {RZ, SE_SDW, RX}}, + +{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, PPCNONE, {BI16, B8}}, +{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, PPCNONE, {BI16, B8}}, +{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, PPCNONE, {BO16, BI16, B8}}, +{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, PPCNONE, {B8}}, +{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, PPCNONE, {B8}}, +}; + +const int vle_num_opcodes = + sizeof (vle_opcodes) / sizeof (vle_opcodes[0]); + /* The macro table. This is only used by the assembler. */ /* The expressions of the form (-x ! 31) & (x | 31) have the value 0