RE: [Patch ARM Gas] - strexh/strexb warn for bad addressing modes.

[hazelnusse <hazelnusse at gmail dot com>]

James Greenhalgh-2 wrote:
> 
> Hi Nick,
> 
> Apologies for the lack of clarity.
> 
> strexh and strexb do not have writeback modes in either arm or thumb
> mode. An unpatched assembler will return an error for the following
> under ARM, but not for thumb. 
> 
> 	strexh r1, r2, [r3, #0]!
> 
> This was line 9 of strex-bad-t.s which `FAIL's on an unpatched assembler
> for me.
> 
> Likewise,
> 
> 	strexb r1, r2, [r3, #0]!
> 
> The patch adds the error for thumb mode.
> 
> The test cases are perhaps a little... over-enthusiastic in testing bad
> addressing modes for strexh/strexb, but form a thorough check that
> problem cases for this instruction are reported.
> 
> Thanks,
> James
> 
> 

I am working on a STMicroelectronics Cortex M-3, and just updated to
binutils as 2.21.53.20110915, and when compiling the core_cm3.c and
core_cm3.h as provided by ARM, I get this error:

/tmp/ccRg7rUW.s: Assembler messages:
/tmp/ccRg7rUW.s:511: Error: registers may not be the same -- `strexb
r0,r0,[r1]'
/tmp/ccRg7rUW.s:536: Error: registers may not be the same -- `strexh
r0,r0,[r1]'

This error is arising from this code in the ARM provided CMSIS files
core_cm3.c and core_cm3.h:

/**
 * @brief  STR Exclusive (8 bit)
 *
 * @param  value  value to store
 * @param  *addr  address pointer
 * @return        successful / failed
 *
 * Exclusive STR command for 8 bit values
 */
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
  __ASM("strexb r0, r0, [r1]");
  __ASM("bx lr");
}

/**
 * @brief  STR Exclusive (16 bit)
 *
 * @param  value  value to store
 * @param  *addr  address pointer
 * @return        successful / failed
 *
 * Exclusive STR command for 16 bit values
 */
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
  __ASM("strexh r0, r0, [r1]");
  __ASM("bx lr");
}

Looking into the ARM Cortex M3 documentation about these instructions [0],
it says:
Syntax
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]

...

Restrictions
In these instructions:
do not use PC
do not use SP for Rd and Rt
for STREX, Rd must be different from both Rt and Rn
the value of offset must be a multiple of four in the range 0-1020.

If you read this literally, it only says STREX has the restriction that
you've added to gas, and that it doesn't apply to any of the other ones (in
particular STREXH and STREXB).  I'm not sure if this is the same across all
the ARM7/9/11 processors, but it certainly seems that this should be an
allowed instruction for Cortex M3, given that they are shipping this
instruction with their CMSIS stuff.

[0] --
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABFFBJB.html
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