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[PATCH, ARM] MSR/MRS assembly and disassembly tweaks
- From: Julian Brown <julian at codesourcery dot com>
- To: binutils at sourceware dot org
- Date: Mon, 4 Apr 2011 15:07:28 +0100
- Subject: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
Hi,
This patch improves handling of MSR and MRS instructions in GAS, and
also improves disassembly output in a couple of cases.
In more detail:
1. It should be possible to use APSR as a synonym for CPSR on e.g.
ARMv7-A and ARMv7-R cores, but the current implementation assembles an
MSR instruction with the "fc" fields set on such cores. I think this is
wrong: I fixed it to only set the "f" field in such cases.
2. Also in MSR instructions, "nzcvqg" bits can now be written in any
order, to bring them in line with other PSR instructions (e.g. "msr
CPSR_<fields>, rX", where <fields> can be in any order). You may only
write "g" if the selected processor for assembly supports the DSP
extension, else you will get an error.
3. Disassembling MSR instructions referring to IAPSR, EAPSR or XPSR now
shows bitfield syntax, "nzcvq" or "g". For APSR itself, the instruction
is still disassembled as CPSR_<fields> though, regardless of
architecture version.
4. BASEPRI_MASK is renamed to BASEPRI_MAX in disassembly (presumably
that was simply a typo).
5. Using plain "APSR" in MSR instructions (as an alias for "APSR_nzcvq")
is deprecated (DDI0403D_armv7m_arm.pdf, B5-799). I've implemented that
by emitting an assembler warning, but that might be a little too
aggressive.
6. VFP control registers are no longer accepted during parsing of
MSR/MRS. There's no testsuite coverage for that feature, and I'm not
sure what it was supposed to do. I didn't find any sign of it in the
ARM ARM, though I may have missed something.
I've added several new test cases to cover the modified functionality.
(Some may be a little redundant: I wrote this patch off an older branch
originally and didn't know about the new tests. They won't hurt though.)
OK to apply?
Thanks,
Julian
ChangeLog
gas/
* config/tc-arm.c (parse_psr): Add LHS argument. Improve support
for *APSR bitmasks.
(operand_parse_code): Replace OP_PSR with OP_wPSR and OP_rPSR.
Remove OP_RVC_PSR.
(parse_operands): Likewise.
(do_mrs): Tweak error message for constraint.
(do_t_mrs): Update constraints for changes to APSR support.
(do_t_msr): Likewise. Don't set PSR_f flag here.
(psrs): Remove "g", "nzcvq", "nzcvqg".
(insns): Tweak entries for msr and mrs instructions.
opcodes/
* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
(print_insn_thumb32): Add APSR bitmask support.
gas/testsuite/
* gas/arm/mrs-msr-thumb-v7-m.s: New.
* gas/arm/mrs-msr-thumb-v7-m.d: New.
* gas/arm/mrs-msr-thumb-v7-m-bad.d: New.
* gas/arm/mrs-msr-thumb-v7-m-bad.l: New.
* gas/arm/mrs-msr-thumb-v7-m-bad.s: New.
* gas/arm/mrs-msr-thumb-v7e-m.d: New.
* gas/arm/mrs-msr-thumb-v7e-m.s: New.
* gas/arm/mrs-msr-arm-v7-a-bad.d: New.
* gas/arm/mrs-msr-arm-v7-a-bad.l: New.
* gas/arm/mrs-msr-arm-v7-a-bad.s: New.
* gas/arm/mrs-msr-arm-v7-a.d: New.
* gas/arm/mrs-msr-arm-v7-a.s: New.
* gas/arm/mrs-msr-arm-v6.d: New.
* gas/arm/mrs-msr-arm-v6.s: New.
* gas/arm/mrs-msr-thumb-v6t2.d: New.
* gas/arm/mrs-msr-thumb-v6t2.s: New.
* gas/arm/arch7.d: Fix typo in disassembly for BASEPRI_MAX,
bitmasks for IAPSR etc.
* gas/arm/arch7.s: Specify bitmask for APSR writes.
* gas/arm/archv6m.s: Likewise.
* msr-imm-bad.l: Tweak expected disassembly in error message.
* msr-reg-bad.l: Likewise.
* msr-imm.d: Tweak expected disassembly.
* msr-reg.d: Likewise.
* msr-reg-thumb.d: Likewise.
* msr-imm.s: Specify bitmask on APSR writes.
* msr-reg.s: Add comment about deprecated usage.? gas/testsuite/gas/arm/a.out
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.478
diff -c -p -r1.478 tc-arm.c
*** gas/config/tc-arm.c 14 Mar 2011 16:04:12 -0000 1.478
--- gas/config/tc-arm.c 4 Apr 2011 13:57:22 -0000
*************** parse_half (char **str)
*** 5347,5385 ****
/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
or a bitmask suitable to be or-ed into the ARM msr instruction. */
static int
! parse_psr (char **str)
{
char *p;
unsigned long psr_field;
const struct asm_psr *psr;
char *start;
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
feature for ease of use and backwards compatibility. */
p = *str;
if (strncasecmp (p, "SPSR", 4) == 0)
! psr_field = SPSR_BIT;
! else if (strncasecmp (p, "CPSR", 4) == 0
! || (strncasecmp (p, "APSR", 4) == 0
! && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)))
! psr_field = 0;
! else
{
start = p;
do
p++;
while (ISALNUM (*p) || *p == '_');
psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
p - start);
if (!psr)
return FAIL;
*str = p;
! return psr->field;
}
p += 4;
if (*p == '_')
{
/* A suffix follows. */
--- 5347,5425 ----
/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
or a bitmask suitable to be or-ed into the ARM msr instruction. */
static int
! parse_psr (char **str, bfd_boolean lhs)
{
char *p;
unsigned long psr_field;
const struct asm_psr *psr;
char *start;
+ bfd_boolean is_apsr = FALSE;
+ bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m);
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
feature for ease of use and backwards compatibility. */
p = *str;
if (strncasecmp (p, "SPSR", 4) == 0)
! {
! if (m_profile)
! goto unsupported_psr;
!
! psr_field = SPSR_BIT;
! }
! else if (strncasecmp (p, "CPSR", 4) == 0)
! {
! if (m_profile)
! goto unsupported_psr;
!
! psr_field = 0;
! }
! else if (strncasecmp (p, "APSR", 4) == 0)
! {
! /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
! and ARMv7-R architecture CPUs. */
! is_apsr = TRUE;
! psr_field = 0;
! }
! else if (m_profile)
{
start = p;
do
p++;
while (ISALNUM (*p) || *p == '_');
+ if (strncasecmp (start, "iapsr", 5) == 0
+ || strncasecmp (start, "eapsr", 5) == 0
+ || strncasecmp (start, "xpsr", 4) == 0
+ || strncasecmp (start, "psr", 3) == 0)
+ p = start + strcspn (start, "rR") + 1;
+
psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
p - start);
+
if (!psr)
return FAIL;
+ /* If APSR is being written, a bitfield may be specified. Note that
+ APSR itself is handled above. */
+ if (psr->field <= 3)
+ {
+ psr_field = psr->field;
+ is_apsr = TRUE;
+ goto check_suffix;
+ }
+
*str = p;
! /* M-profile MSR instructions have the mask field set to "10", except
! *PSR variants which modify APSR, which may use a different mask (and
! have been handled already). Do that by setting the PSR_f field
! here. */
! return psr->field | (lhs ? PSR_f : 0);
}
+ else
+ goto unsupported_psr;
p += 4;
+ check_suffix:
if (*p == '_')
{
/* A suffix follows. */
*************** parse_psr (char **str)
*** 5390,5412 ****
p++;
while (ISALNUM (*p) || *p == '_');
! psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
! p - start);
! if (!psr)
! goto error;
! psr_field |= psr->field;
}
else
{
if (ISALNUM (*p))
goto error; /* Garbage after "[CS]PSR". */
! psr_field |= (PSR_c | PSR_f);
}
*str = p;
return psr_field;
error:
inst.error = _("flag for {c}psr instruction expected");
return FAIL;
--- 5430,5535 ----
p++;
while (ISALNUM (*p) || *p == '_');
! if (is_apsr)
! {
! /* APSR uses a notation for bits, rather than fields. */
! unsigned int nzcvq_bits = 0;
! unsigned int g_bit = 0;
! char *bit;
!
! for (bit = start; bit != p; bit++)
! {
! switch (TOLOWER (*bit))
! {
! case 'n':
! nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
! break;
!
! case 'z':
! nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
! break;
!
! case 'c':
! nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
! break;
!
! case 'v':
! nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
! break;
!
! case 'q':
! nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
! break;
!
! case 'g':
! g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
! break;
!
! default:
! inst.error = _("unexpected bit specified after APSR");
! return FAIL;
! }
! }
!
! if (nzcvq_bits == 0x1f)
! psr_field |= PSR_f;
!
! if (g_bit == 0x1)
! {
! if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
! {
! inst.error = _("selected processor does not "
! "support DSP extension");
! return FAIL;
! }
!
! psr_field |= PSR_s;
! }
!
! if ((nzcvq_bits & 0x20) != 0
! || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
! || (g_bit & 0x2) != 0)
! {
! inst.error = _("bad bitmask specified after APSR");
! return FAIL;
! }
! }
! else
! {
! psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
! p - start);
! if (!psr)
! goto error;
! psr_field |= psr->field;
! }
}
else
{
if (ISALNUM (*p))
goto error; /* Garbage after "[CS]PSR". */
! /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
! is deprecated, but allow it anyway. */
! if (is_apsr && lhs)
! {
! psr_field |= PSR_f;
! as_tsktsk (_("writing to APSR without specifying a bitmask is "
! "deprecated"));
! }
! else if (!m_profile)
! /* These bits are never right for M-profile devices: don't set them
! (only code paths which read/write APSR reach here). */
! psr_field |= (PSR_c | PSR_f);
}
*str = p;
return psr_field;
+ unsupported_psr:
+ inst.error = _("selected processor does not support requested special "
+ "purpose register");
+ return FAIL;
+
error:
inst.error = _("flag for {c}psr instruction expected");
return FAIL;
*************** enum operand_parse_code
*** 5932,5942 ****
OP_CPSF, /* CPS flags */
OP_ENDI, /* Endianness specifier */
! OP_PSR, /* CPSR/SPSR mask for msr */
OP_COND, /* conditional code */
OP_TB, /* Table branch. */
- OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */
OP_APSR_RR, /* ARM register or "APSR_nzcv". */
OP_RRnpc_I0, /* ARM register or literal 0 */
--- 6055,6065 ----
OP_CPSF, /* CPS flags */
OP_ENDI, /* Endianness specifier */
! OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
! OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
OP_COND, /* conditional code */
OP_TB, /* Table branch. */
OP_APSR_RR, /* ARM register or "APSR_nzcv". */
OP_RRnpc_I0, /* ARM register or literal 0 */
*************** parse_operands (char *str, const unsigne
*** 6402,6408 ****
case OP_CPSF: val = parse_cps_flags (&str); break;
case OP_ENDI: val = parse_endian_specifier (&str); break;
case OP_oROR: val = parse_ror (&str); break;
- case OP_PSR: val = parse_psr (&str); break;
case OP_COND: val = parse_cond (&str); break;
case OP_oBARRIER_I15:
po_barrier_or_imm (str); break;
--- 6525,6530 ----
*************** parse_operands (char *str, const unsigne
*** 6411,6421 ****
goto failure;
break;
! case OP_RVC_PSR:
! po_reg_or_goto (REG_TYPE_VFC, try_banked_reg);
! inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
! break;
! try_banked_reg:
po_reg_or_goto (REG_TYPE_RNB, try_psr);
if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
{
--- 6533,6540 ----
goto failure;
break;
! case OP_wPSR:
! case OP_rPSR:
po_reg_or_goto (REG_TYPE_RNB, try_psr);
if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
{
*************** parse_operands (char *str, const unsigne
*** 6424,6432 ****
goto failure;
}
break;
! try_psr:
! val = parse_psr (&str);
! break;
case OP_APSR_RR:
po_reg_or_goto (REG_TYPE_RN, try_apsr);
--- 6543,6551 ----
goto failure;
}
break;
! try_psr:
! val = parse_psr (&str, op_parse_code == OP_wPSR);
! break;
case OP_APSR_RR:
po_reg_or_goto (REG_TYPE_RN, try_apsr);
*************** parse_operands (char *str, const unsigne
*** 6583,6590 ****
case OP_CPSF:
case OP_ENDI:
case OP_oROR:
! case OP_PSR:
! case OP_RVC_PSR:
case OP_COND:
case OP_oBARRIER_I15:
case OP_REGLST:
--- 6702,6709 ----
case OP_CPSF:
case OP_ENDI:
case OP_oROR:
! case OP_wPSR:
! case OP_rPSR:
case OP_COND:
case OP_oBARRIER_I15:
case OP_REGLST:
*************** do_mrs (void)
*** 7912,7918 ****
/* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
!= (PSR_c|PSR_f),
! _("'CPSR' or 'SPSR' expected"));
br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
}
--- 8031,8037 ----
/* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
!= (PSR_c|PSR_f),
! _("'APSR', 'CPSR' or 'SPSR' expected"));
br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
}
*************** do_t_mrs (void)
*** 10828,10848 ****
{
int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
! if (flags == 0)
! {
! constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
! _("selected processor does not support "
! "requested special purpose register"));
! }
! else
! {
! constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
! _("selected processor does not support "
! "requested special purpose register"));
! /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
! constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
! _("'CPSR' or 'SPSR' expected"));
! }
inst.instruction |= (flags & SPSR_BIT) >> 2;
inst.instruction |= inst.operands[1].imm & 0xff;
--- 10947,10960 ----
{
int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
! if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
! constraint (flags != 0, _("selected processor does not support "
! "requested special purpose register"));
! else
! /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
! devices). */
! constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
! _("'APSR', 'CPSR' or 'SPSR' expected"));
inst.instruction |= (flags & SPSR_BIT) >> 2;
inst.instruction |= inst.operands[1].imm & 0xff;
*************** do_t_msr (void)
*** 10867,10885 ****
else
flags = inst.operands[0].imm;
! if (flags & ~0xff)
{
! constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
! _("selected processor does not support "
! "requested special purpose register"));
}
else
! {
! constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
! _("selected processor does not support "
! "requested special purpose register"));
! flags |= PSR_f;
! }
Rn = inst.operands[1].reg;
reject_bad_reg (Rn);
--- 10979,10998 ----
else
flags = inst.operands[0].imm;
! if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
{
! int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
!
! constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
! && (bits & ~(PSR_s | PSR_f)) != 0)
! || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
! && bits != PSR_f),
! _("selected processor does not support requested special "
! "purpose register"));
}
else
! constraint ((flags & 0xff) != 0, _("selected processor does not support "
! "requested special purpose register"));
Rn = inst.operands[1].reg;
reject_bad_reg (Rn);
*************** static const struct asm_psr psrs[] =
*** 16440,16446 ****
{"c", PSR_c},
{"x", PSR_x},
{"s", PSR_s},
- {"g", PSR_s},
/* Combinations of flags. */
{"fs", PSR_f | PSR_s},
--- 16553,16558 ----
*************** static const struct asm_psr psrs[] =
*** 16503,16512 ****
{"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
{"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
{"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
-
- /* APSR flags */
- {"nzcvq", PSR_f},
- {"nzcvqg", PSR_s | PSR_f}
};
/* Table of V7M psr names. */
--- 16615,16620 ----
*************** static const struct asm_opcode insns[] =
*** 16955,16962 ****
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_msr
! TCE("mrs", 1000000, f3e08000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
! TCE("msr", 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
--- 17063,17070 ----
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_msr
! TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
! TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
Index: gas/testsuite/gas/arm/arch7.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arch7.d,v
retrieving revision 1.6
diff -c -p -r1.6 arch7.d
*** gas/testsuite/gas/arm/arch7.d 17 Sep 2010 10:42:04 -0000 1.6
--- gas/testsuite/gas/arm/arch7.d 4 Apr 2011 13:57:22 -0000
*************** Disassembly of section .text:
*** 57,69 ****
0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
! 0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MASK
0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
! 0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR), r0
! 0+0dc <[^>]*> f380 8801 msr IAPSR, r0
! 0+0e0 <[^>]*> f380 8802 msr EAPSR, r0
! 0+0e4 <[^>]*> f380 8803 msr PSR, r0
0+0e8 <[^>]*> f380 8805 msr IPSR, r0
0+0ec <[^>]*> f380 8806 msr EPSR, r0
0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
--- 57,69 ----
0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
! 0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MAX
0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
! 0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR_nzcvq), r0
! 0+0dc <[^>]*> f380 8801 msr IAPSR_nzcvq, r0
! 0+0e0 <[^>]*> f380 8802 msr EAPSR_nzcvq, r0
! 0+0e4 <[^>]*> f380 8803 msr PSR_nzcvq, r0
0+0e8 <[^>]*> f380 8805 msr IPSR, r0
0+0ec <[^>]*> f380 8806 msr EPSR, r0
0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
*************** Disassembly of section .text:
*** 71,78 ****
0+0f8 <[^>]*> f380 8809 msr PSP, r0
0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
0+100 <[^>]*> f380 8811 msr BASEPRI, r0
! 0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0
0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
0+10c <[^>]*> f380 8814 msr CONTROL, r0
0+110 <[^>]*> f3ef 8003 mrs r0, PSR
! 0+114 <[^>]*> f380 8803 msr PSR, r0
--- 71,78 ----
0+0f8 <[^>]*> f380 8809 msr PSP, r0
0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
0+100 <[^>]*> f380 8811 msr BASEPRI, r0
! 0+104 <[^>]*> f380 8812 msr BASEPRI_MAX, r0
0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
0+10c <[^>]*> f380 8814 msr CONTROL, r0
0+110 <[^>]*> f3ef 8003 mrs r0, PSR
! 0+114 <[^>]*> f380 8803 msr PSR_nzcvq, r0
Index: gas/testsuite/gas/arm/arch7.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arch7.s,v
retrieving revision 1.2
diff -c -p -r1.2 arch7.s
*** gas/testsuite/gas/arm/arch7.s 17 Sep 2010 10:42:04 -0000 1.2
--- gas/testsuite/gas/arm/arch7.s 4 Apr 2011 13:57:22 -0000
*************** label2:
*** 63,72 ****
mrs r0, basepri_max
mrs r0, faultmask
mrs r0, control
! msr apsr, r0
! msr iapsr, r0
! msr eapsr, r0
! msr psr, r0
msr ipsr, r0
msr epsr, r0
msr iepsr, r0
--- 63,72 ----
mrs r0, basepri_max
mrs r0, faultmask
mrs r0, control
! msr apsr_nzcvq, r0
! msr iapsr_nzcvq, r0
! msr eapsr_nzcvq, r0
! msr psr_nzcvq, r0
msr ipsr, r0
msr epsr, r0
msr iepsr, r0
*************** label2:
*** 78,81 ****
msr faultmask, r0
msr control, r0
mrs r0, xpsr
! msr xpsr, r0
--- 78,81 ----
msr faultmask, r0
msr control, r0
mrs r0, xpsr
! msr xpsr_nzcvq, r0
Index: gas/testsuite/gas/arm/archv6m.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/archv6m.s,v
retrieving revision 1.2
diff -c -p -r1.2 archv6m.s
*** gas/testsuite/gas/arm/archv6m.s 2 Mar 2009 00:29:23 -0000 1.2
--- gas/testsuite/gas/arm/archv6m.s 4 Apr 2011 13:57:22 -0000
***************
*** 5,11 ****
.align 2
.global foo
foo:
! msr apsr,r6
msr epsr,r9
mrs r2, iapsr
yield
--- 5,11 ----
.align 2
.global foo
foo:
! msr apsr_nzcvq,r6
msr epsr,r9
mrs r2, iapsr
yield
Index: gas/testsuite/gas/arm/mrs-msr-arm-v6.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v6.d
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v6.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v6.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,16 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MRS/MSR test, architecture v6, ARM mode
+
+ .*: file format .*
+
+
+ Disassembly of section .text:
+ 0+00 <[^>]*> e10f4000 mrs r4, CPSR
+ 0+04 <[^>]*> e10f5000 mrs r5, CPSR
+ 0+08 <[^>]*> e14f6000 mrs r6, SPSR
+ 0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 ; 0x40000000
+ 0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
+ 0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
+ 0+18 <[^>]*> e128f004 msr CPSR_f, r4
+ 0+1c <[^>]*> e128f005 msr CPSR_f, r5
+ 0+20 <[^>]*> e169f006 msr SPSR_fc, r6
Index: gas/testsuite/gas/arm/mrs-msr-arm-v6.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v6.s
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v6.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v6.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,13 ----
+ .arch armv6
+ .text
+ .arm
+
+ mrs r4, apsr
+ mrs r5, cpsr
+ mrs r6, spsr
+ msr apsr_nzcvq, #0x40000000
+ msr cpsr_f, #0x20000000
+ msr spsr, #0x10000000
+ msr apsr_nzcvq, r4
+ msr cpsr_f, r5
+ msr spsr, r6
Index: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,2 ----
+ # name: MRS/MSR negative test, architecture v7-A, ARM mode
+ # error-output: mrs-msr-arm-v7-a-bad.l
Index: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,5 ----
+ [^:]*: Assembler messages:
+ [^:]*:5: Error: 'APSR', 'CPSR' or 'SPSR' expected -- `mrs r4,apsr_nzcvq'
+ [^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,iapsr'
+ [^:]*:7: Error: selected processor does not support requested special purpose register -- `msr iapsr,r4'
+ [^:]*:8: writing to APSR without specifying a bitmask is deprecated
Index: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,8 ----
+ .arch armv7-a
+ .text
+ .arm
+
+ mrs r4, apsr_nzcvq
+ mrs r5, iapsr
+ msr iapsr, r4
+ msr apsr, r5
Index: gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,16 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MRS/MSR test, architecture v7-A, ARM mode
+
+ .*: file format .*
+
+
+ Disassembly of section .text:
+ 0+00 <[^>]*> e10f4000 mrs r4, CPSR
+ 0+04 <[^>]*> e10f5000 mrs r5, CPSR
+ 0+08 <[^>]*> e14f6000 mrs r6, SPSR
+ 0+0c <[^>]*> e32cf101 msr CPSR_fs, #1073741824 ; 0x40000000
+ 0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
+ 0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
+ 0+18 <[^>]*> e128f004 msr CPSR_f, r4
+ 0+1c <[^>]*> e128f005 msr CPSR_f, r5
+ 0+20 <[^>]*> e169f006 msr SPSR_fc, r6
Index: gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s
diff -N gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,13 ----
+ .arch armv7-a
+ .text
+ .arm
+
+ mrs r4, apsr
+ mrs r5, cpsr
+ mrs r6, spsr
+ msr apsr_nzcvqg, #0x40000000
+ msr cpsr_f, #0x20000000
+ msr spsr, #0x10000000
+ msr apsr_nzcvq, r4
+ msr cpsr_f, r5
+ msr spsr, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,13 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MRS/MSR test, architecture v6t2, Thumb mode
+
+ .*: file format .*
+
+
+ Disassembly of section .text:
+ 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
+ 0+04 <[^>]*> f3ef 8500 mrs r5, CPSR
+ 0+08 <[^>]*> f3ff 8600 mrs r6, SPSR
+ 0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
+ 0+10 <[^>]*> f385 8800 msr CPSR_f, r5
+ 0+14 <[^>]*> f396 8900 msr SPSR_fc, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,10 ----
+ .arch armv6t2
+ .text
+ .thumb
+
+ mrs r4, apsr
+ mrs r5, cpsr
+ mrs r6, spsr
+ msr apsr_nzcvqg, r4
+ msr cpsr_f, r5
+ msr spsr, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,2 ----
+ # name: MRS/MSR negative test, architecture v7-M, Thumb mode
+ # error-output: mrs-msr-thumb-v7-m-bad.l
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,10 ----
+ [^:]*: Assembler messages:
+ [^:]*:5: Error: selected processor does not support requested special purpose register -- `mrs r4,cpsr'
+ [^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,spsr'
+ [^:]*:7: Error: selected processor does not support DSP extension -- `msr apsr_nzcvqg,r4'
+ [^:]*:8: Error: selected processor does not support DSP extension -- `msr iapsr_nzcvqg,r5'
+ [^:]*:9: Error: bad bitmask specified after APSR -- `msr xpsr_nncvq,r6'
+ [^:]*:10: Error: bad bitmask specified after APSR -- `msr xpsr_nzcv,r7'
+ [^:]*:11: Error: selected processor does not support requested special purpose register -- `msr cpsr_f,r7'
+ [^:]*:12: Error: selected processor does not support requested special purpose register -- `msr spsr,r8'
+ [^:]*:13: Error: syntax error -- `msr primask_nzcvq,r9'
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,13 ----
+ .arch armv7-m
+ .text
+ .thumb
+
+ mrs r4, cpsr
+ mrs r5, spsr
+ msr apsr_nzcvqg, r4
+ msr iapsr_nzcvqg, r5
+ msr xpsr_nncvq, r6
+ msr xpsr_nzcv, r7
+ msr cpsr_f, r7
+ msr spsr, r8
+ msr primask_nzcvq, r9
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,15 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MRS/MSR test, architecture v7-M, Thumb mode
+
+
+ .*: file format .*
+
+
+ Disassembly of section .text:
+ 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
+ 0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
+ 0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
+ 0+0c <[^>]*> f383 8803 msr PSR_nzcvq, r3
+ 0+10 <[^>]*> f384 8800 msr CPSR_f, r4
+ 0+14 <[^>]*> f385 8801 msr IAPSR_nzcvq, r5
+ 0+18 <[^>]*> f386 8810 msr PRIMASK, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,11 ----
+ .arch armv7-m
+ .text
+ .thumb
+
+ mrs r4, apsr
+ mrs r5, eapsr
+ mrs r6, primask
+ msr xpsr_nzcvq, r3
+ msr apsr_nzcvq, r4
+ msr iapsr_nzcvq, r5
+ msr primask, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,13 ----
+ #objdump: -dr --prefix-addresses --show-raw-insn
+ #name: MRS/MSR test, architecture v7e-M, Thumb mode
+
+ .*: file format .*
+
+
+ Disassembly of section .text:
+ 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
+ 0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
+ 0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
+ 0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
+ 0+10 <[^>]*> f385 8401 msr IAPSR_g, r5
+ 0+14 <[^>]*> f386 8812 msr BASEPRI_MAX, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s
===================================================================
RCS file: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s
diff -N gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s 4 Apr 2011 13:57:22 -0000
***************
*** 0 ****
--- 1,10 ----
+ .arch armv7e-m
+ .text
+ .thumb
+
+ mrs r4, apsr
+ mrs r5, eapsr
+ mrs r6, primask
+ msr apsr_nzcvqg, r4
+ msr iapsr_g, r5
+ msr basepri_max, r6
Index: gas/testsuite/gas/arm/msr-imm-bad.l
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-imm-bad.l,v
retrieving revision 1.1
diff -c -p -r1.1 msr-imm-bad.l
*** gas/testsuite/gas/arm/msr-imm-bad.l 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-imm-bad.l 4 Apr 2011 13:57:22 -0000
***************
*** 1,5 ****
[^:]*: Assembler messages:
! [^:]*:9: Error: Thumb encoding does not support an immediate here -- `msr APSR,#0xc0000004'
[^:]*:10: Error: Thumb encoding does not support an immediate here -- `msr APSR_g,#0xc0000004'
[^:]*:11: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
[^:]*:12: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvqg,#0xc0000004'
--- 1,5 ----
[^:]*: Assembler messages:
! [^:]*:9: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
[^:]*:10: Error: Thumb encoding does not support an immediate here -- `msr APSR_g,#0xc0000004'
[^:]*:11: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
[^:]*:12: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvqg,#0xc0000004'
Index: gas/testsuite/gas/arm/msr-imm.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-imm.d,v
retrieving revision 1.1
diff -c -p -r1.1 msr-imm.d
*** gas/testsuite/gas/arm/msr-imm.d 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-imm.d 4 Apr 2011 13:57:22 -0000
***************
*** 5,11 ****
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
--- 5,11 ----
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
Index: gas/testsuite/gas/arm/msr-imm.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-imm.s,v
retrieving revision 1.1
diff -c -p -r1.1 msr-imm.s
*** gas/testsuite/gas/arm/msr-imm.s 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-imm.s 4 Apr 2011 13:57:22 -0000
***************
*** 6,12 ****
@ Write to Special Register from Immediate
@ Write to application status register
! msr APSR,#0xc0000004
msr APSR_g,#0xc0000004
msr APSR_nzcvq,#0xc0000004
msr APSR_nzcvqg,#0xc0000004
--- 6,12 ----
@ Write to Special Register from Immediate
@ Write to application status register
! msr APSR_nzcvq,#0xc0000004
msr APSR_g,#0xc0000004
msr APSR_nzcvq,#0xc0000004
msr APSR_nzcvqg,#0xc0000004
Index: gas/testsuite/gas/arm/msr-reg-bad.l
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-reg-bad.l,v
retrieving revision 1.1
diff -c -p -r1.1 msr-reg-bad.l
*** gas/testsuite/gas/arm/msr-reg-bad.l 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-reg-bad.l 4 Apr 2011 13:57:22 -0000
***************
*** 1,7 ****
[^:]*: Assembler messages:
! [^:]*:9: Error: syntax error -- `msr APSR_g,r9'
! [^:]*:10: Error: syntax error -- `msr APSR_nzcvq,r9'
! [^:]*:11: Error: syntax error -- `msr APSR_nzcvqg,r9'
[^:]*:14: Error: selected processor does not support requested special purpose register -- `msr CPSR,r9'
[^:]*:15: Error: selected processor does not support requested special purpose register -- `msr CPSR_s,r9'
[^:]*:16: Error: selected processor does not support requested special purpose register -- `msr CPSR_f,r9'
--- 1,7 ----
[^:]*: Assembler messages:
! [^:]*:8: writing to APSR without specifying a bitmask is deprecated
! [^:]*:9: Error: selected processor does not support DSP extension -- `msr APSR_g,r9'
! [^:]*:11: Error: selected processor does not support DSP extension -- `msr APSR_nzcvqg,r9'
[^:]*:14: Error: selected processor does not support requested special purpose register -- `msr CPSR,r9'
[^:]*:15: Error: selected processor does not support requested special purpose register -- `msr CPSR_s,r9'
[^:]*:16: Error: selected processor does not support requested special purpose register -- `msr CPSR_f,r9'
Index: gas/testsuite/gas/arm/msr-reg-thumb.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-reg-thumb.d,v
retrieving revision 1.2
diff -c -p -r1.2 msr-reg-thumb.d
*** gas/testsuite/gas/arm/msr-reg-thumb.d 22 Oct 2010 08:13:58 -0000 1.2
--- gas/testsuite/gas/arm/msr-reg-thumb.d 4 Apr 2011 13:57:22 -0000
***************
*** 2,13 ****
# as: -march=armv7-a -mthumb
# source: msr-reg.s
# objdump: -dr --prefix-addresses --show-raw-insn
# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> f389 8900 msr CPSR_fc, r9
00000004 <[^>]*> f389 8400 msr CPSR_s, r9
00000008 <[^>]*> f389 8800 msr CPSR_f, r9
0000000c <[^>]*> f389 8c00 msr CPSR_fs, r9
--- 2,14 ----
# as: -march=armv7-a -mthumb
# source: msr-reg.s
# objdump: -dr --prefix-addresses --show-raw-insn
+ # warning: writing to APSR without specifying a bitmask is deprecated
# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> f389 8800 msr CPSR_f, r9
00000004 <[^>]*> f389 8400 msr CPSR_s, r9
00000008 <[^>]*> f389 8800 msr CPSR_f, r9
0000000c <[^>]*> f389 8c00 msr CPSR_fs, r9
Index: gas/testsuite/gas/arm/msr-reg.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-reg.d,v
retrieving revision 1.1
diff -c -p -r1.1 msr-reg.d
*** gas/testsuite/gas/arm/msr-reg.d 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-reg.d 4 Apr 2011 13:57:22 -0000
***************
*** 1,11 ****
# name: MSR register operands
# as: -march=armv7-a
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> e129f009 msr CPSR_fc, r9
00000004 <[^>]*> e124f009 msr CPSR_s, r9
00000008 <[^>]*> e128f009 msr CPSR_f, r9
0000000c <[^>]*> e12cf009 msr CPSR_fs, r9
--- 1,12 ----
# name: MSR register operands
# as: -march=armv7-a
# objdump: -dr --prefix-addresses --show-raw-insn
+ # warning: writing to APSR without specifying a bitmask is deprecated
.*: +file format .*arm.*
Disassembly of section .text:
! 00000000 <[^>]*> e128f009 msr CPSR_f, r9
00000004 <[^>]*> e124f009 msr CPSR_s, r9
00000008 <[^>]*> e128f009 msr CPSR_f, r9
0000000c <[^>]*> e12cf009 msr CPSR_fs, r9
Index: gas/testsuite/gas/arm/msr-reg.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/msr-reg.s,v
retrieving revision 1.1
diff -c -p -r1.1 msr-reg.s
*** gas/testsuite/gas/arm/msr-reg.s 17 Sep 2010 10:42:04 -0000 1.1
--- gas/testsuite/gas/arm/msr-reg.s 4 Apr 2011 13:57:22 -0000
***************
*** 5,11 ****
.syntax unified
@ Write to Special Register from register
! msr APSR,r9
msr APSR_g,r9
msr APSR_nzcvq,r9
msr APSR_nzcvqg,r9
--- 5,11 ----
.syntax unified
@ Write to Special Register from register
! msr APSR,r9 @ deprecated usage.
msr APSR_g,r9
msr APSR_nzcvq,r9
msr APSR_nzcvqg,r9
Index: opcodes/arm-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/arm-dis.c,v
retrieving revision 1.138
diff -c -p -r1.138 arm-dis.c
*** opcodes/arm-dis.c 14 Mar 2011 16:04:08 -0000 1.138
--- opcodes/arm-dis.c 4 Apr 2011 13:57:22 -0000
*************** psr_name (int regno)
*** 3718,3724 ****
case 9: return "PSP";
case 16: return "PRIMASK";
case 17: return "BASEPRI";
! case 18: return "BASEPRI_MASK";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
default: return "<unknown>";
--- 3718,3724 ----
case 9: return "PSP";
case 16: return "PRIMASK";
case 17: return "BASEPRI";
! case 18: return "BASEPRI_MAX";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
default: return "<unknown>";
*************** print_insn_thumb32 (bfd_vma pc, struct d
*** 4188,4193 ****
--- 4188,4202 ----
else
func (stream, "(UNDEF: %lu)", sysm);
}
+ else if ((given & 0xff) <= 3)
+ {
+ func (stream, "%s_", psr_name (given & 0xff));
+
+ if (given & 0x800)
+ func (stream, "nzcvq");
+ if (given & 0x400)
+ func (stream, "g");
+ }
else
{
func (stream, psr_name (given & 0xff));