diff --git a/gas/ChangeLog b/gas/ChangeLog
index 50216fd..08f908d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2010-12-20  Quentin Neill  <quentin.neill@amd.com>
+
+	* config/tc-i386.c (cpu_arch): Add CPU_BMI_FLAGS.
+	(build_modrm_byte): Add BMI instruction encoding.
+
+	* doc/c-i386.texi (i386-BMI): New section.
+
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* config/tc-mips.c (insn_uses_reg): Handle the new flags
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 9c33cf9..4c12e9f 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -715,6 +715,8 @@ static const arch_entry cpu_arch[] =
     CPU_SSE4A_FLAGS, 0, 0 },
   { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
     CPU_ABM_FLAGS, 0, 0 },
+  { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
+    CPU_BMI_FLAGS, 0, 0 },
 };
 
 #ifdef I386COFF
@@ -5550,7 +5552,8 @@ build_modrm_byte (void)
       else
 	mem = ~0;
 
-      if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+      if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+          || (i.tm.opcode_modifier.vexsources == XOP2REVSOURCES))
 	{
 	  if (operand_type_check (i.types[0], imm))
 	    i.vex.register_specifier = NULL;
@@ -5558,7 +5561,8 @@ build_modrm_byte (void)
 	    {
 	      /* VEX.vvvv encodes one of the sources when the first
 		 operand is not an immediate.  */
-	      if (i.tm.opcode_modifier.vexw == VEXW0)
+              if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+                  && (i.tm.opcode_modifier.vexw == VEXW0))
 		i.vex.register_specifier = i.op[0].regs;
 	      else
 		i.vex.register_specifier = i.op[1].regs;
@@ -5575,7 +5579,8 @@ build_modrm_byte (void)
 	    {
 	      i.rm.mode = 3;
 
-	      if (i.tm.opcode_modifier.vexw == VEXW0)
+              if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+                  && (i.tm.opcode_modifier.vexw == VEXW0))
 		i.rm.regmem = i.op[1].regs->reg_num;
 	      else
 		i.rm.regmem = i.op[0].regs->reg_num;
@@ -5584,17 +5589,32 @@ build_modrm_byte (void)
 		i.rex |= REX_B;
 	    }
 	}
-      else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
+      else if (i.tm.opcode_modifier.vexvvvv == VEXVRM)
 	{
-	  i.vex.register_specifier = i.op[2].regs;
+	  unsigned int regspec_op = MAX_OPERANDS;
+	  unsigned int regmem_op = MAX_OPERANDS; 
+	  if (i.tm.opcode_modifier.modrmregext)
+	    {
+	      i.rm.reg = i.tm.extension_opcode;
+	      regspec_op = 1;
+	      regmem_op = 0;
+	    }
+	  else
+	    {
+	      regspec_op = 2;
+	      regmem_op = 1;
+	    }
+
+	  i.vex.register_specifier = i.op[regspec_op].regs;
 	  if (!i.mem_operands)
 	    {
 	      i.rm.mode = 3;
-	      i.rm.regmem = i.op[1].regs->reg_num;
-	      if ((i.op[1].regs->reg_flags & RegRex) != 0)
+	      i.rm.regmem = i.op[regmem_op].regs->reg_num;
+	      if ((i.op[regmem_op].regs->reg_flags & RegRex) != 0)
 		i.rex |= REX_B;
 	    }
 	}
+
       /* Fill in i.rm.reg or i.rm.regmem field with register operand
 	 (if any) based on i.tm.extension_opcode.  Again, we must be
 	 careful to make sure that segment/control/debug/test/MMX
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 1c6175b..fd315b0 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -35,6 +35,7 @@ extending the Intel architecture to 64-bits.
 * i386-Float::                  Floating Point
 * i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
 * i386-LWP::                    AMD's Lightweight Profiling Instructions
+* i386-BMI::                    Bit Manipulation Instructions
 * i386-16bit::                  Writing 16-bit Code
 * i386-Arch::                   Specifying an x86 CPU architecture
 * i386-Bugs::                   AT&T Syntax bugs
@@ -842,6 +843,20 @@ For detailed information on the LWP instruction set, see the
 @cite{AMD Lightweight Profiling Specification} available at
 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
 
+@node i386-BMI
+@section Bit Manipulation Instructions
+
+@cindex BMI, i386
+@cindex BMI, x86-64
+
+@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
+
+BMI instructions provide several instructions implementing individual
+bit manipulation operations such as isolation, masking, setting, or
+resetting.  
+
+@c Need to add a specification citation here.
+
 @node i386-16bit
 @section Writing 16-bit Code
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0cf93d6..01faa8d 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,20 @@
+2010-12-20  Quentin Neill  <quentin.neill@amd.com>
+
+	* gas/i386/i386.exp: Run bmi and x86-64-bmi.
+	* gas/i386/bmi.d: New.
+	* gas/i386/bmi.s: New.
+	* gas/i386/x86-64-bmi.d: New.
+	* gas/i386/x86-64-bmi.s: New.
+	* gas/i386/arch-10.s: Add a BMI instruction.
+	* gas/i386/x86-64-arch-2.s: Likewise.
+	* gas/i386/arch-10.d: Add bmi flag and BMI instruction pattern.
+	* gas/i386/x86-64-arch-2.d: Likewise.
+	* gas/i386/arch-10-1.l: Add BMI instruction pattern.
+	* gas/i386/arch-10-2.l: Likewise.
+	* gas/i386/arch-10-3.l: Likewise.
+	* gas/i386/arch-10-4.l: Likewise.
+
+
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* gas/mips/loongson-3a-2.s, gas/mips/loongson-3a-2.d,
diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l
index 0b78958..95f4425 100644
--- a/gas/testsuite/gas/i386/arch-10-1.l
+++ b/gas/testsuite/gas/i386/arch-10-1.l
@@ -29,6 +29,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -96,5 +97,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l
index d9e1b51..3e9d68f 100644
--- a/gas/testsuite/gas/i386/arch-10-2.l
+++ b/gas/testsuite/gas/i386/arch-10-2.l
@@ -28,6 +28,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -95,5 +96,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l
index 75c07ec..7183ea0 100644
--- a/gas/testsuite/gas/i386/arch-10-3.l
+++ b/gas/testsuite/gas/i386/arch-10-3.l
@@ -21,6 +21,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -91,5 +92,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l
index 3c40045..7cd68a3 100644
--- a/gas/testsuite/gas/i386/arch-10-4.l
+++ b/gas/testsuite/gas/i386/arch-10-4.l
@@ -19,6 +19,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -89,5 +90,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d
index 3efd52d..6e40abd 100644
--- a/gas/testsuite/gas/i386/arch-10.d
+++ b/gas/testsuite/gas/i386/arch-10.d
@@ -1,4 +1,4 @@
-#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
 #objdump: -dw
 #name: i386 arch 10
 
@@ -36,5 +36,6 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f 1f 00             	nopl   \(%eax\)
 #pass
diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s
index d0fb12b..7c669eb 100644
--- a/gas/testsuite/gas/i386/arch-10.s
+++ b/gas/testsuite/gas/i386/arch-10.s
@@ -58,5 +58,7 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
+# BMI
+blsr %ecx,%ebx
 # nop
 nopl (%eax)
diff --git a/gas/testsuite/gas/i386/bmi.d b/gas/testsuite/gas/i386/bmi.d
new file mode 100644
index 0000000..1f89b7c
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.d
@@ -0,0 +1,153 @@
+#objdump: -dw
+#name: i386 BMI
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c4 e2 78 f2 ff       	andn   %edi,%eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 70 f2 0c fa    	andn   \(%edx,%edi,8\),%ecx,%ecx
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 c3       	andn   %ebx,%esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f2 14 9b    	andn   \(%ebx,%ebx,4\),%ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 b1 dc 36 00 00 	andn   0x36dc\(%ecx\),%edi,%esi
+[ 	]*[a-f0-9]+:	c4 e2 48 f2 1b       	andn   \(%ebx\),%esi,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f8       	andn   %eax,%ebx,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f2 c1       	andn   %ecx,%eax,%eax
+[ 	]*[a-f0-9]+:	c4 e2 68 f2 a4 5e 86 a9 9d ae 	andn   -0x5162567a\(%esi,%ebx,2\),%edx,%esp
+[ 	]*[a-f0-9]+:	c4 e2 68 f2 2e       	andn   \(%esi\),%edx,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 c2       	andn   %edx,%esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f2 d6       	andn   %esi,%ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 be 53 21 ff ff 	andn   -0xdead\(%esi\),%edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 74 19 0a 	andn   0xa\(%ecx,%ebx,1\),%esp,%esi
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 00       	andn   \(%eax\),%edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 7c 13 ce 	andn   -0x32\(%ebx,%edx,1\),%edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 3b       	bextr  %eax,\(%ebx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 31       	bextr  %edi,\(%ecx\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 58 f7 cf       	bextr  %esp,%edi,%ecx
+[ 	]*[a-f0-9]+:	c4 e2 50 f7 c1       	bextr  %ebp,%ecx,%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 f8       	bextr  %ebx,%eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 48 f7 d3       	bextr  %esi,%ebx,%edx
+[ 	]*[a-f0-9]+:	c4 e2 68 f7 04 07    	bextr  %edx,\(%edi,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 2f       	bextr  %edi,\(%edi\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 70 f7 e6       	bextr  %ecx,%esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 18       	bextr  %edi,\(%eax\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 04 05 00 00 00 00 	bextr  %eax,0x0\(,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f7 22       	bextr  %ebp,\(%edx\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 48 f7 2c 85 0f a9 00 00 	bextr  %esi,0xa90f\(,%eax,4\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 7c 03 03 	bextr  %ebx,0x3\(%ebx,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 b9 ff ff ff 3f 	bextr  %edi,0x3fffffff\(%ecx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 04 12    	bextr  %eax,\(%edx,%edx,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 df       	blsi   %edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d8       	blsi   %eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1b       	blsi   \(%ebx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 de       	blsi   %esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 da       	blsi   %edx,%edx
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 1f       	blsi   \(%edi\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 59 08    	blsi   0x8\(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 1a       	blsi   \(%edx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 19       	blsi   \(%ecx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 dd       	blsi   %ebp,%esp
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 1c 19    	blsi   \(%ecx,%ebx,1\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 1c 4d 03 00 00 00 	blsi   0x3\(,%ecx,2\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 1c 02    	blsi   \(%edx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1c 71    	blsi   \(%ecx,%esi,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d8       	blsi   %eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 18       	blsi   \(%eax\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 d2       	blsmsk %edx,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d7       	blsmsk %edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d0       	blsmsk %eax,%eax
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 d5       	blsmsk %ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 d3       	blsmsk %ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 17       	blsmsk \(%edi\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 14 85 00 00 00 00 	blsmsk 0x0\(,%eax,4\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d4       	blsmsk %esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 13       	blsmsk \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 d3    	blsmsk \(%ebx,%edx,8\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 d6       	blsmsk %esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 94 7f af e6 3d a1 	blsmsk -0x5ec21951\(%edi,%edi,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 48    	blsmsk \(%eax,%ecx,2\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 1b    	blsmsk \(%ebx,%ebx,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 14 83    	blsmsk \(%ebx,%eax,4\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 8c 92 fe ca 00 00 	blsr   0xcafe\(%edx,%edx,4\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 cf       	blsr   %edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 0c cd 00 00 00 00 	blsr   0x0\(,%ecx,8\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 c8       	blsr   %eax,%edx
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 0e       	blsr   \(%esi\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 0c 9d 51 35 b0 66 	blsr   0x66b03551\(,%ebx,4\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 0c 85 0a ff ff ff 	blsr   -0xf6\(,%eax,4\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 ce       	blsr   %esi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 0b       	blsr   \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 8c 7b 3a f2 00 00 	blsr   0xf23a\(%ebx,%edi,2\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 09       	blsr   \(%ecx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 0c 05 05 00 00 00 	blsr   0x5\(,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 cd       	blsr   %ebp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 8c 03 c3 41 00 00 	blsr   0x41c3\(%ebx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 0c 5d 03 00 00 00 	blsr   0x3\(,%ebx,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 49 5a    	blsr   0x5a\(%ecx\),%edi
+[ 	]*[a-f0-9]+:	66 f3 0f bd 38       	lzcnt  \(%eax\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd e7       	lzcnt  %di,%sp
+[ 	]*[a-f0-9]+:	66 f3 0f bd 06       	lzcnt  \(%esi\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bd 14 cd 00 00 00 00 	lzcnt  0x0\(,%ecx,8\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bd fc       	lzcnt  %sp,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 14 35 09 60 ff ff 	lzcnt  -0x9ff7\(,%esi,1\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bd bc cb 4d 6e 00 00 	lzcnt  0x6e4d\(%ebx,%ecx,8\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 2a       	lzcnt  \(%edx\),%bp
+[ 	]*[a-f0-9]+:	66 f3 0f bd c9       	lzcnt  %cx,%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bd dd       	lzcnt  %bp,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bd f6       	lzcnt  %si,%si
+[ 	]*[a-f0-9]+:	66 f3 0f bd 04 05 00 00 00 00 	lzcnt  0x0\(,%eax,1\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bd f8       	lzcnt  %ax,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd db       	lzcnt  %bx,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bd fa       	lzcnt  %dx,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 1f       	lzcnt  \(%edi\),%bx
+[ 	]*[a-f0-9]+:	f3 0f bd db          	lzcnt  %ebx,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bd f9          	lzcnt  %ecx,%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 14 09       	lzcnt  \(%ecx,%ecx,1\),%edx
+[ 	]*[a-f0-9]+:	f3 0f bd c0          	lzcnt  %eax,%eax
+[ 	]*[a-f0-9]+:	f3 0f bd cf          	lzcnt  %edi,%ecx
+[ 	]*[a-f0-9]+:	f3 0f bd fc          	lzcnt  %esp,%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 34 7d 00 00 00 00 	lzcnt  0x0\(,%edi,2\),%esi
+[ 	]*[a-f0-9]+:	f3 0f bd 03          	lzcnt  \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bd 3c 43       	lzcnt  \(%ebx,%eax,2\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 1f          	lzcnt  \(%edi\),%ebx
+[ 	]*[a-f0-9]+:	f3 0f bd ed          	lzcnt  %ebp,%ebp
+[ 	]*[a-f0-9]+:	f3 0f bd a3 ad de 00 00 	lzcnt  0xdead\(%ebx\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bd c6          	lzcnt  %esi,%eax
+[ 	]*[a-f0-9]+:	f3 0f bd bc 00 05 63 00 00 	lzcnt  0x6305\(%eax,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd bc 07 74 8f ff ff 	lzcnt  -0x708c\(%edi,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 06          	lzcnt  \(%esi\),%eax
+[ 	]*[a-f0-9]+:	66 f3 0f bc eb       	tzcnt  %bx,%bp
+[ 	]*[a-f0-9]+:	66 f3 0f bc c7       	tzcnt  %di,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc fd       	tzcnt  %bp,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc 14 16    	tzcnt  \(%esi,%edx,1\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 0f       	tzcnt  \(%edi\),%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 0a       	tzcnt  \(%edx\),%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  %ax,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 24 8d 00 00 00 00 	tzcnt  0x0\(,%ecx,4\),%sp
+[ 	]*[a-f0-9]+:	66 f3 0f bc 31       	tzcnt  \(%ecx\),%si
+[ 	]*[a-f0-9]+:	66 f3 0f bc 03       	tzcnt  \(%ebx\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc 3c c7    	tzcnt  \(%edi,%eax,8\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc 1c 3b    	tzcnt  \(%ebx,%edi,1\),%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc c1       	tzcnt  %cx,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc b9 63 27 ff ff 	tzcnt  -0xd89d\(%ecx\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc c5       	tzcnt  %bp,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc c5       	tzcnt  %bp,%ax
+[ 	]*[a-f0-9]+:	f3 0f bc f8          	tzcnt  %eax,%edi
+[ 	]*[a-f0-9]+:	f3 0f bc f7          	tzcnt  %edi,%esi
+[ 	]*[a-f0-9]+:	f3 0f bc 44 3b 61    	tzcnt  0x61\(%ebx,%edi,1\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc de          	tzcnt  %esi,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bc 2a          	tzcnt  \(%edx\),%ebp
+[ 	]*[a-f0-9]+:	f3 0f bc 16          	tzcnt  \(%esi\),%edx
+[ 	]*[a-f0-9]+:	f3 0f bc 0c 0f       	tzcnt  \(%edi,%ecx,1\),%ecx
+[ 	]*[a-f0-9]+:	f3 0f bc f5          	tzcnt  %ebp,%esi
+[ 	]*[a-f0-9]+:	f3 0f bc 07          	tzcnt  \(%edi\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3c 07       	tzcnt  \(%edi,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bc 24 00       	tzcnt  \(%eax,%eax,1\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bc 00          	tzcnt  \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3c 45 bf ff ff ff 	tzcnt  -0x41\(,%eax,2\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bc 24 1d 01 00 00 c0 	tzcnt  -0x3fffffff\(,%ebx,1\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bc c3          	tzcnt  %ebx,%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3b          	tzcnt  \(%ebx\),%edi
+
diff --git a/gas/testsuite/gas/i386/bmi.s b/gas/testsuite/gas/i386/bmi.s
new file mode 100644
index 0000000..f3f9c38
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.s
@@ -0,0 +1,151 @@
+
+	.allow_index_reg
+	.text
+	
+_start:
+
+    ANDN     %edi,%eax,%edi
+    ANDN     (%edx,%edi,8),%ecx,%ecx
+    ANDN     %ebx,%esp,%eax
+    ANDN     (%ebx,%ebx,4),%ebp,%edx
+    ANDN     0x36DC(%ecx),%edi,%esi
+    ANDN     (%ebx),%esi,%ebx
+    ANDN     %eax,%ebx,%edi
+    ANDN     %ecx,%eax,%eax
+    ANDN     -0x5162567A(%esi,%ebx,2),%edx,%esp
+    ANDN     (%esi),%edx,%ebp
+    ANDN     %edx,%esp,%eax
+    ANDN     %esi,%ebp,%edx
+    ANDN     -0xDEAD(%esi),%edi,%edi
+    ANDN     0xA(%ecx,%ebx),%esp,%esi
+    ANDN     (%eax),%edi,%eax
+    ANDN     -0x32(%ebx,%edx),%edi,%edi
+    BEXTR    %eax,(%ebx),%edi
+    BEXTR    %edi,(%ecx),%esi
+    BEXTR    %esp,%edi,%ecx
+    BEXTR    %ebp,%ecx,%eax
+    BEXTR    %ebx,%eax,%edi
+    BEXTR    %esi,%ebx,%edx
+    BEXTR    %edx,(%edi,%eax),%eax
+    BEXTR    %edi,(%edi),%ebp
+    BEXTR    %ecx,%esi,%esp
+    BEXTR    %edi,0x0(%eax),%ebx
+    BEXTR    %eax,(,%eax,1),%eax
+    BEXTR    %ebp,(%edx),%esp
+    BEXTR    %esi,0xA90F(,%eax,4),%ebp
+    BEXTR    %ebx,0x3(%ebx,%eax),%edi
+    BEXTR    %edi,0x3FFFFFFF(%ecx),%edi
+    BEXTR    %eax,(%edx,%edx),%eax
+    BLSI     %edi,%eax
+    BLSI     %eax,%edi
+    BLSI     (%ebx),%edi
+    BLSI     %esi,%esp
+    BLSI     %edx,%edx
+    BLSI     (%edi),%esi
+    BLSI     0x8(%ecx),%ebx
+    BLSI     (%edx),%eax
+    BLSI     (%ecx),%eax
+    BLSI     %ebp,%esp
+    BLSI     (%ecx,%ebx),%ebp
+    BLSI     0x3(,%ecx,2),%ecx
+    BLSI     (%edx,%eax),%eax
+    BLSI     (%ecx,%esi,2),%edi
+    BLSI     %eax,%edi
+    BLSI     (%eax),%eax
+    BLSMSK   %edx,%ebp
+    BLSMSK   %edi,%edi
+    BLSMSK   %eax,%eax
+    BLSMSK   %ebp,%edx
+    BLSMSK   %ebx,%esi
+    BLSMSK   (%edi),%ecx
+    BLSMSK   (%ecx),%ebx
+    BLSMSK   (,%eax,4),%esp
+    BLSMSK   %esp,%eax
+    BLSMSK   (%ebx),%eax
+    BLSMSK   (%ebx,%edx,8),%eax
+    BLSMSK   %esi,%esp
+    BLSMSK   -0x5EC21951(%edi,%edi,2),%edi
+    BLSMSK   (%eax,%ecx,2),%eax
+    BLSMSK   (%ebx,%ebx),%eax
+    BLSMSK   (%ebx,%eax,4),%edi
+    BLSR     0xCAFE(%edx,%edx,4),%esp
+    BLSR     %edi,%eax
+    BLSR     (,%ecx,8),%esi
+    BLSR     %eax,%edx
+    BLSR     (%esi),%ecx
+    BLSR     0x66B03551(,%ebx,4),%edi
+    BLSR     -0xF6(,%eax,4),%ebp
+    BLSR     %esi,%edi
+    BLSR     (%ebx),%eax
+    BLSR     0xF23A(%ebx,%edi,2),%ebx
+    BLSR     (%ecx),%edi
+    BLSR     0x5(,%eax),%eax
+    BLSR     %ebp,%eax
+    BLSR     0x41C3(%ebx,%eax),%eax
+    BLSR     0x3(,%ebx,2),%edi
+    BLSR     0x5A(%ecx),%edi
+    LZCNT    (%eax),%di
+    LZCNT    %di,%sp
+    LZCNT    (%esi),%ax
+    LZCNT    (,%ecx,8),%dx
+    LZCNT    %sp,%di
+    LZCNT    -0x9FF7(,%esi),%dx
+    LZCNT    0x6E4D(%ebx,%ecx,8),%di
+    LZCNT    (%edx),%bp
+    LZCNT    %cx,%cx
+    LZCNT    %bp,%bx
+    LZCNT    %si,%si
+    LZCNT    (,%eax,1),%ax
+    LZCNT    %ax,%di
+    LZCNT    %bx,%bx
+    LZCNT    %dx,%di
+    LZCNT    (%edi),%bx
+    LZCNT    %ebx,%ebx
+    LZCNT    %ecx,%edi
+    LZCNT    (%ecx,%ecx),%edx
+    LZCNT    %eax,%eax
+    LZCNT    %edi,%ecx
+    LZCNT    %esp,%edi
+    LZCNT    (,%edi,2),%esi
+    LZCNT    (%ebx),%eax
+    LZCNT    (%ebx,%eax,2),%edi
+    LZCNT    (%edi),%ebx
+    LZCNT    %ebp,%ebp
+    LZCNT    0xDEAD(%ebx),%esp
+    LZCNT    %esi,%eax
+    LZCNT    0x6305(%eax,%eax,1),%edi
+    LZCNT    -0x708C(%edi,%eax),%edi
+    LZCNT    (%esi),%eax
+    TZCNT    %bx,%bp
+    TZCNT    %di,%ax
+    TZCNT    %bp,%di
+    TZCNT    (%esi,%edx,1),%dx
+    TZCNT    (%edi),%cx
+    TZCNT    (%edx),%cx
+    TZCNT    %ax,%bx
+    TZCNT    (,%ecx,4),%sp
+    TZCNT    (%ecx),%si
+    TZCNT    (%ebx),%ax
+    TZCNT    (%edi,%eax,8),%di
+    TZCNT    (%ebx,%edi),%bx
+    TZCNT    %cx,%ax
+    TZCNT    -0xD89D(%ecx),%di
+    TZCNT    %bp,%ax
+    TZCNT    %bp,%ax
+    TZCNT    %eax,%edi
+    TZCNT    %edi,%esi
+    TZCNT    0x61(%ebx,%edi),%eax
+    TZCNT    %esi,%ebx
+    TZCNT    (%edx),%ebp
+    TZCNT    (%esi),%edx
+    TZCNT    (%edi,%ecx),%ecx
+    TZCNT    %ebp,%esi
+    TZCNT    (%edi),%eax
+    TZCNT    (%edi,%eax,1),%edi
+    TZCNT    (%eax,%eax),%esp
+    TZCNT    (%eax),%eax
+    TZCNT    -0x41(,%eax,2),%edi
+    TZCNT    -0x3FFFFFFF(,%ebx),%esp
+    TZCNT    %ebx,%eax
+    TZCNT    (%ebx),%edi
+
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3a966d7..01a3ecb 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -173,6 +173,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "fma4"
     run_dump_test "lwp"
     run_dump_test "xop"
+    run_dump_test "bmi"
     run_dump_test "f16c"
     run_dump_test "f16c-intel"
     run_dump_test "fsgs"
@@ -372,6 +373,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-fma4"
     run_dump_test "x86-64-lwp"
     run_dump_test "x86-64-xop"
+    run_dump_test "x86-64-bmi"
     run_dump_test "x86-64-f16c"
     run_dump_test "x86-64-f16c-intel"
     run_dump_test "x86-64-fsgs"
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d
index 9cd1306..ac09453 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
 #objdump: -dw
 #name: x86-64 arch 2
 
@@ -36,4 +36,5 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s
index ddc0d40..962f15e 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.s
@@ -58,3 +58,5 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
+# BMI
+blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.d b/gas/testsuite/gas/i386/x86-64-bmi.d
new file mode 100644
index 0000000..180e40f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.d
@@ -0,0 +1,265 @@
+#objdump: -dw
+#name: x86-64 BMI
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c4 c2 00 f2 c0       	andn   %r8d,%r15d,%eax
+[ 	]*[a-f0-9]+:	c4 62 78 f2 14 0e    	andn   \(%rsi,%rcx,1\),%eax,%r10d
+[ 	]*[a-f0-9]+:	67 c4 c2 48 f2 2e    	andn   \(%r14d\),%esi,%ebp
+[ 	]*[a-f0-9]+:	c4 42 40 f2 7d 00    	andn   0x0\(%r13\),%edi,%r15d
+[ 	]*[a-f0-9]+:	c4 42 18 f2 fe       	andn   %r14d,%r12d,%r15d
+[ 	]*[a-f0-9]+:	67 c4 82 08 f2 3c 50 	andn   \(%r8d,%r10d,2\),%r14d,%edi
+[ 	]*[a-f0-9]+:	67 c4 42 28 f2 29    	andn   \(%r9d\),%r10d,%r13d
+[ 	]*[a-f0-9]+:	67 c4 22 70 f2 0c bd 00 00 00 00 	andn   0x0\(,%r15d,4\),%ecx,%r9d
+[ 	]*[a-f0-9]+:	c4 a2 38 f2 24 85 00 00 00 00 	andn   0x0\(,%r8,4\),%r8d,%esp
+[ 	]*[a-f0-9]+:	c4 62 38 f2 24 07    	andn   \(%rdi,%rax,1\),%r8d,%r12d
+[ 	]*[a-f0-9]+:	67 c4 c2 20 f2 44 1d 00 	andn   0x0\(%r13d,%ebx,1\),%r11d,%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f2       	andn   %edx,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 c2 58 f2 11       	andn   \(%r9\),%esp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 00 f2 0f       	andn   \(%rdi\),%r15d,%ecx
+[ 	]*[a-f0-9]+:	67 c4 62 50 f2 37    	andn   \(%edi\),%ebp,%r14d
+[ 	]*[a-f0-9]+:	c4 a2 28 f2 84 83 fa b5 bb c6 	andn   -0x39444a06\(%rbx,%r8,4\),%r10d,%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f2 02    	andn   \(%r10d\),%rax,%rax
+[ 	]*[a-f0-9]+:	67 c4 c2 80 f2 16    	andn   \(%r14d\),%r15,%rdx
+[ 	]*[a-f0-9]+:	c4 02 d8 f2 bc 0f 93 5b 00 00 	andn   0x5b93\(%r15,%r9,1\),%rsp,%r15
+[ 	]*[a-f0-9]+:	c4 42 a0 f2 09       	andn   \(%r9\),%r11,%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 80 f2 3c 45 00 00 00 00 	andn   0x0\(,%eax,2\),%r15,%rdi
+[ 	]*[a-f0-9]+:	c4 62 c8 f2 dd       	andn   %rbp,%rsi,%r11
+[ 	]*[a-f0-9]+:	c4 42 e0 f2 45 00    	andn   0x0\(%r13\),%rbx,%r8
+[ 	]*[a-f0-9]+:	c4 62 c0 f2 d0       	andn   %rax,%rdi,%r10
+[ 	]*[a-f0-9]+:	c4 c2 98 f2 e4       	andn   %r12,%r12,%rsp
+[ 	]*[a-f0-9]+:	67 c4 62 a8 f2 3e    	andn   \(%esi\),%r10,%r15
+[ 	]*[a-f0-9]+:	67 c4 62 f8 f2 3a    	andn   \(%edx\),%rax,%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f2 37    	andn   \(%r15d\),%r8,%rsi
+[ 	]*[a-f0-9]+:	67 c4 42 80 f2 20    	andn   \(%r8d\),%r15,%r12
+[ 	]*[a-f0-9]+:	c4 c2 80 f2 ef       	andn   %r15,%r15,%rbp
+[ 	]*[a-f0-9]+:	c4 a2 d0 f2 0c e5 00 00 00 00 	andn   0x0\(,%r12,8\),%rbp,%rcx
+[ 	]*[a-f0-9]+:	c4 62 f0 f2 2a       	andn   \(%rdx\),%rcx,%r13
+[ 	]*[a-f0-9]+:	c4 e2 00 f7 c0       	bextr  %r15d,%eax,%eax
+[ 	]*[a-f0-9]+:	c4 42 78 f7 fa       	bextr  %eax,%r10d,%r15d
+[ 	]*[a-f0-9]+:	67 c4 82 68 f7 0c cf 	bextr  %edx,\(%r15d,%r9d,8\),%ecx
+[ 	]*[a-f0-9]+:	c4 02 50 f7 54 3d 00 	bextr  %ebp,0x0\(%r13,%r15,1\),%r10d
+[ 	]*[a-f0-9]+:	c4 c2 20 f7 ef       	bextr  %r11d,%r15d,%ebp
+[ 	]*[a-f0-9]+:	c4 82 00 f7 64 35 00 	bextr  %r15d,0x0\(%r13,%r14,1\),%esp
+[ 	]*[a-f0-9]+:	67 c4 02 30 f7 84 c3 ad de 00 00 	bextr  %r9d,0xdead\(%r11d,%r8d,8\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 c2 20 f7 44 04 01 	bextr  %r11d,0x1\(%r12d,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	67 c4 42 28 f7 76 f4 	bextr  %r10d,-0xc\(%r14d\),%r14d
+[ 	]*[a-f0-9]+:	c4 62 78 f7 18       	bextr  %eax,\(%rax\),%r11d
+[ 	]*[a-f0-9]+:	67 c4 c2 60 f7 14 24 	bextr  %ebx,\(%r12d\),%edx
+[ 	]*[a-f0-9]+:	67 c4 62 48 f7 28    	bextr  %esi,\(%eax\),%r13d
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 dd       	bextr  %eax,%ebp,%ebx
+[ 	]*[a-f0-9]+:	c4 c2 78 f7 04 24    	bextr  %eax,\(%r12\),%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 50 f7 04 02 	bextr  %ebp,\(%r10d,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	67 c4 e2 10 f7 44 03 99 	bextr  %r13d,-0x67\(%ebx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 82 a8 f7 84 7b fe ca 00 00 	bextr  %r10,0xcafe\(%r11,%r15,2\),%rax
+[ 	]*[a-f0-9]+:	c4 42 a8 f7 b1 fe ca 00 00 	bextr  %r10,0xcafe\(%r9\),%r14
+[ 	]*[a-f0-9]+:	c4 62 f8 f7 ff       	bextr  %rax,%rdi,%r15
+[ 	]*[a-f0-9]+:	67 c4 62 f8 f7 2a    	bextr  %rax,\(%edx\),%r13
+[ 	]*[a-f0-9]+:	c4 42 f8 f7 17       	bextr  %rax,\(%r15\),%r10
+[ 	]*[a-f0-9]+:	c4 c2 80 f7 ea       	bextr  %r15,%r10,%rbp
+[ 	]*[a-f0-9]+:	67 c4 e2 f8 f7 3e    	bextr  %rax,\(%esi\),%rdi
+[ 	]*[a-f0-9]+:	c4 42 98 f7 e1       	bextr  %r12,%r9,%r12
+[ 	]*[a-f0-9]+:	c4 c2 b8 f7 dd       	bextr  %r8,%r13,%rbx
+[ 	]*[a-f0-9]+:	c4 c2 f8 f7 24 24    	bextr  %rax,\(%r12\),%rsp
+[ 	]*[a-f0-9]+:	c4 42 f8 f7 5d 00    	bextr  %rax,0x0\(%r13\),%r11
+[ 	]*[a-f0-9]+:	c4 c2 f8 f7 30       	bextr  %rax,\(%r8\),%rsi
+[ 	]*[a-f0-9]+:	c4 e2 f0 f7 d6       	bextr  %rcx,%rsi,%rdx
+[ 	]*[a-f0-9]+:	67 c4 02 b8 f7 7c 0a 03 	bextr  %r8,0x3\(%r10d,%r9d,1\),%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f7 07    	bextr  %rax,\(%r15d\),%rax
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f7 08    	bextr  %rax,\(%r8d\),%rcx
+[ 	]*[a-f0-9]+:	67 c4 a2 48 f3 1c 7d f3 ff ff ff 	blsi   -0xd\(,%r15d,2\),%esi
+[ 	]*[a-f0-9]+:	c4 c2 00 f3 df       	blsi   %r15d,%r15d
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d8       	blsi   %eax,%eax
+[ 	]*[a-f0-9]+:	c4 c2 28 f3 19       	blsi   \(%r9\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 30 f3 dd       	blsi   %ebp,%r9d
+[ 	]*[a-f0-9]+:	c4 a2 68 f3 1c 4d 05 00 00 00 	blsi   0x5\(,%r9,2\),%edx
+[ 	]*[a-f0-9]+:	c4 a2 70 f3 1c 5d 96 ff ff ff 	blsi   -0x6a\(,%r11,2\),%ecx
+[ 	]*[a-f0-9]+:	67 c4 e2 50 f3 19    	blsi   \(%ecx\),%ebp
+[ 	]*[a-f0-9]+:	67 c4 e2 20 f3 1f    	blsi   \(%edi\),%r11d
+[ 	]*[a-f0-9]+:	c4 e2 38 f3 5f f9    	blsi   -0x7\(%rdi\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 c2 10 f3 18    	blsi   \(%r8d\),%r13d
+[ 	]*[a-f0-9]+:	c4 c2 60 f3 1a       	blsi   \(%r10\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1c 05 fe ca 00 00 	blsi   0xcafe\(,%rax,1\),%edi
+[ 	]*[a-f0-9]+:	67 c4 e2 78 f3 1e    	blsi   \(%esi\),%eax
+[ 	]*[a-f0-9]+:	c4 c2 78 f3 d9       	blsi   %r9d,%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 78 f3 5c 3a 99 	blsi   -0x67\(%r10d,%edi,1\),%eax
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 5a 0f    	blsi   0xf\(%r10\),%r15
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 df       	blsi   %r15,%rax
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 d8       	blsi   %rax,%rsp
+[ 	]*[a-f0-9]+:	67 c4 e2 a8 f3 18    	blsi   \(%eax\),%r10
+[ 	]*[a-f0-9]+:	67 c4 c2 90 f3 18    	blsi   \(%r8d\),%r13
+[ 	]*[a-f0-9]+:	67 c4 a2 88 f3 9c cf 85 00 00 00 	blsi   0x85\(%edi,%r9d,8\),%r14
+[ 	]*[a-f0-9]+:	c4 c2 98 f3 da       	blsi   %r10,%r12
+[ 	]*[a-f0-9]+:	c4 c2 b8 f3 1b       	blsi   \(%r11\),%r8
+[ 	]*[a-f0-9]+:	c4 c2 b0 f3 9f 20 d6 db b8 	blsi   -0x472429e0\(%r15\),%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 e8 f3 1f    	blsi   \(%edi\),%rdx
+[ 	]*[a-f0-9]+:	67 c4 e2 e0 f3 1c 95 00 00 00 00 	blsi   0x0\(,%edx,4\),%rbx
+[ 	]*[a-f0-9]+:	67 c4 e2 c0 f3 1b    	blsi   \(%ebx\),%rdi
+[ 	]*[a-f0-9]+:	c4 c2 f0 f3 9a ad de 00 00 	blsi   0xdead\(%r10\),%rcx
+[ 	]*[a-f0-9]+:	c4 82 c0 f3 5c f7 1b 	blsi   0x1b\(%r15,%r14,8\),%rdi
+[ 	]*[a-f0-9]+:	c4 e2 a0 f3 1b       	blsi   \(%rbx\),%r11
+[ 	]*[a-f0-9]+:	c4 82 f8 f3 5c 08 0a 	blsi   0xa\(%r8,%r9,1\),%rax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d0       	blsmsk %eax,%eax
+[ 	]*[a-f0-9]+:	c4 a2 48 f3 14 8d 00 00 00 00 	blsmsk 0x0\(,%r9,4\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 00 f3 14 7d 00 00 00 00 	blsmsk 0x0\(,%edi,2\),%r15d
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 17       	blsmsk \(%rdi\),%esp
+[ 	]*[a-f0-9]+:	67 c4 c2 70 f3 55 00 	blsmsk 0x0\(%r13d\),%ecx
+[ 	]*[a-f0-9]+:	c4 c2 08 f3 d1       	blsmsk %r9d,%r14d
+[ 	]*[a-f0-9]+:	c4 e2 38 f3 12       	blsmsk \(%rdx\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 e2 18 f3 16    	blsmsk \(%esi\),%r12d
+[ 	]*[a-f0-9]+:	c4 c2 20 f3 94 15 c5 22 f8 65 	blsmsk 0x65f822c5\(%r13,%rdx,1\),%r11d
+[ 	]*[a-f0-9]+:	67 c4 e2 28 f3 54 0b fd 	blsmsk -0x3\(%ebx,%ecx,1\),%r10d
+[ 	]*[a-f0-9]+:	c4 c2 50 f3 d7       	blsmsk %r15d,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 10 f3 d6       	blsmsk %esi,%r13d
+[ 	]*[a-f0-9]+:	c4 c2 68 f3 17       	blsmsk \(%r15\),%edx
+[ 	]*[a-f0-9]+:	c4 c2 28 f3 16       	blsmsk \(%r14\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d5       	blsmsk %ebp,%edi
+[ 	]*[a-f0-9]+:	c4 a2 60 f3 14 21    	blsmsk \(%rcx,%r12,1\),%ebx
+[ 	]*[a-f0-9]+:	c4 c2 e8 f3 d7       	blsmsk %r15,%rdx
+[ 	]*[a-f0-9]+:	c4 e2 f8 f3 14 c8    	blsmsk \(%rax,%rcx,8\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d1       	blsmsk %r9,%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f3 17    	blsmsk \(%r15d\),%r8
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 d0       	blsmsk %rax,%r15
+[ 	]*[a-f0-9]+:	c4 e2 98 f3 56 fd    	blsmsk -0x3\(%rsi\),%r12
+[ 	]*[a-f0-9]+:	c4 e2 c8 f3 14 12    	blsmsk \(%rdx,%rdx,1\),%rsi
+[ 	]*[a-f0-9]+:	c4 c2 e0 f3 16       	blsmsk \(%r14\),%rbx
+[ 	]*[a-f0-9]+:	c4 c2 c0 f3 17       	blsmsk \(%r15\),%rdi
+[ 	]*[a-f0-9]+:	c4 a2 d0 f3 14 25 24 ff ff ff 	blsmsk -0xdc\(,%r12,1\),%rbp
+[ 	]*[a-f0-9]+:	67 c4 e2 a0 f3 13    	blsmsk \(%ebx\),%r11
+[ 	]*[a-f0-9]+:	67 c4 a2 f8 f3 14 35 b8 43 00 00 	blsmsk 0x43b8\(,%r14d,1\),%rax
+[ 	]*[a-f0-9]+:	c4 e2 90 f3 d2       	blsmsk %rdx,%r13
+[ 	]*[a-f0-9]+:	c4 e2 b0 f3 d5       	blsmsk %rbp,%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 d8 f3 10    	blsmsk \(%eax\),%rsp
+[ 	]*[a-f0-9]+:	67 c4 c2 80 f3 16    	blsmsk \(%r14d\),%r15
+[ 	]*[a-f0-9]+:	c4 c2 00 f3 cf       	blsr   %r15d,%r15d
+[ 	]*[a-f0-9]+:	c4 e2 30 f3 c8       	blsr   %eax,%r9d
+[ 	]*[a-f0-9]+:	67 c4 e2 08 f3 0c 15 01 00 00 00 	blsr   0x1\(,%edx,1\),%r14d
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 ca       	blsr   %edx,%ecx
+[ 	]*[a-f0-9]+:	c4 a2 60 f3 0c 71    	blsr   \(%rcx,%r14,2\),%ebx
+[ 	]*[a-f0-9]+:	67 c4 a2 78 f3 0c 8d 4a 46 00 00 	blsr   0x464a\(,%r9d,4\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 0e       	blsr   \(%rsi\),%esp
+[ 	]*[a-f0-9]+:	67 c4 e2 48 f3 09    	blsr   \(%ecx\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 48 f3 0f    	blsr   \(%edi\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 28 f3 0c 7d 00 00 00 00 	blsr   0x0\(,%edi,2\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 20 f3 0a       	blsr   \(%rdx\),%r11d
+[ 	]*[a-f0-9]+:	c4 c2 10 f3 0b       	blsr   \(%r11\),%r13d
+[ 	]*[a-f0-9]+:	c4 c2 38 f3 c9       	blsr   %r9d,%r8d
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 cf       	blsr   %edi,%edx
+[ 	]*[a-f0-9]+:	67 c4 e2 78 f3 0b    	blsr   \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 08       	blsr   \(%rax\),%edi
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 0b       	blsr   \(%r11\),%r15
+[ 	]*[a-f0-9]+:	67 c4 e2 b0 f3 0c 0d 03 00 00 00 	blsr   0x3\(,%ecx,1\),%r9
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 0e       	blsr   \(%rsi\),%rsp
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 4d 00    	blsr   0x0\(%r13\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 e8 f3 cf       	blsr   %r15,%rdx
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f3 0e    	blsr   \(%r14d\),%r8
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 0e       	blsr   \(%r14\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 d0 f3 08       	blsr   \(%r8\),%rbp
+[ 	]*[a-f0-9]+:	c4 e2 a0 f3 ca       	blsr   %rdx,%r11
+[ 	]*[a-f0-9]+:	67 c4 e2 80 f3 0a    	blsr   \(%edx\),%r15
+[ 	]*[a-f0-9]+:	67 c4 a2 e0 f3 0c 25 7e 33 00 00 	blsr   0x337e\(,%r12d,1\),%rbx
+[ 	]*[a-f0-9]+:	c4 e2 f0 f3 08       	blsr   \(%rax\),%rcx
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 cd       	blsr   %rbp,%rsp
+[ 	]*[a-f0-9]+:	c4 e2 a8 f3 c8       	blsr   %rax,%r10
+[ 	]*[a-f0-9]+:	c4 82 98 f3 4c a5 67 	blsr   0x67\(%r13,%r12,4\),%r12
+[ 	]*[a-f0-9]+:	67 c4 a2 c0 f3 0c 2d 00 00 00 00 	blsr   0x0\(,%r13d,1\),%rdi
+[ 	]*[a-f0-9]+:	67 66 f3 46 0f bd 2c 05 5a 1f 00 00 	lzcnt  0x1f5a\(,%r8d,1\),%r13w
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd e0    	lzcnt  %ax,%r12w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 11    	lzcnt  \(%r9\),%r10w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd c5    	lzcnt  %r13w,%ax
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd 3c c5 99 ff ff ff 	lzcnt  -0x67\(,%rax,8\),%r15w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd 7c 15 00 	lzcnt  0x0\(%r13,%rdx,1\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 2f       	lzcnt  \(%rdi\),%bp
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 03    	lzcnt  \(%r11\),%r8w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd f7    	lzcnt  %r15w,%si
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bd 26 	lzcnt  \(%r14d\),%sp
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd 09    	lzcnt  \(%rcx\),%r9w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 8c db e7 9a 00 00 	lzcnt  0x9ae7\(%r11,%rbx,8\),%r9w
+[ 	]*[a-f0-9]+:	66 f3 0f bd f6       	lzcnt  %si,%si
+[ 	]*[a-f0-9]+:	67 66 f3 0f bd 0b    	lzcnt  \(%ebx\),%cx
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bd 1a 	lzcnt  \(%r10d\),%bx
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd f1    	lzcnt  %r9w,%r14w
+[ 	]*[a-f0-9]+:	67 f3 45 0f bd 7d 00 	lzcnt  0x0\(%r13d\),%r15d
+[ 	]*[a-f0-9]+:	f3 0f bd e7          	lzcnt  %edi,%esp
+[ 	]*[a-f0-9]+:	67 f3 45 0f bd 2e    	lzcnt  \(%r14d\),%r13d
+[ 	]*[a-f0-9]+:	f3 41 0f bd 16       	lzcnt  \(%r14\),%edx
+[ 	]*[a-f0-9]+:	f3 45 0f bd df       	lzcnt  %r15d,%r11d
+[ 	]*[a-f0-9]+:	f3 0f bd c0          	lzcnt  %eax,%eax
+[ 	]*[a-f0-9]+:	f3 41 0f bd 30       	lzcnt  \(%r8\),%esi
+[ 	]*[a-f0-9]+:	f3 45 0f bd f9       	lzcnt  %r9d,%r15d
+[ 	]*[a-f0-9]+:	f3 45 0f bd 04 24    	lzcnt  \(%r12\),%r8d
+[ 	]*[a-f0-9]+:	f3 41 0f bd e8       	lzcnt  %r8d,%ebp
+[ 	]*[a-f0-9]+:	67 f3 41 0f bd 1a    	lzcnt  \(%r10d\),%ebx
+[ 	]*[a-f0-9]+:	f3 41 0f bd 3c 0c    	lzcnt  \(%r12,%rcx,1\),%edi
+[ 	]*[a-f0-9]+:	f3 44 0f bd 3f       	lzcnt  \(%rdi\),%r15d
+[ 	]*[a-f0-9]+:	67 f3 44 0f bd 3f    	lzcnt  \(%edi\),%r15d
+[ 	]*[a-f0-9]+:	f3 45 0f bd d4       	lzcnt  %r12d,%r10d
+[ 	]*[a-f0-9]+:	f3 42 0f bd 04 2d 00 00 00 00 	lzcnt  0x0\(,%r13,1\),%eax
+[ 	]*[a-f0-9]+:	67 f3 49 0f bd 6d 00 	lzcnt  0x0\(%r13d\),%rbp
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bd 02    	lzcnt  \(%r10d\),%r8
+[ 	]*[a-f0-9]+:	67 f3 48 0f bd 06    	lzcnt  \(%esi\),%rax
+[ 	]*[a-f0-9]+:	f3 4c 0f bd eb       	lzcnt  %rbx,%r13
+[ 	]*[a-f0-9]+:	f3 4d 0f bd 39       	lzcnt  \(%r9\),%r15
+[ 	]*[a-f0-9]+:	f3 48 0f bd ca       	lzcnt  %rdx,%rcx
+[ 	]*[a-f0-9]+:	f3 4a 0f bd 04 6d 00 00 00 00 	lzcnt  0x0\(,%r13,2\),%rax
+[ 	]*[a-f0-9]+:	67 f3 48 0f bd 30    	lzcnt  \(%eax\),%rsi
+[ 	]*[a-f0-9]+:	67 f3 49 0f bd 27    	lzcnt  \(%r15d\),%rsp
+[ 	]*[a-f0-9]+:	67 f3 4e 0f bd 1c bd 00 00 00 00 	lzcnt  0x0\(,%r15d,4\),%r11
+[ 	]*[a-f0-9]+:	f3 4d 0f bd e7       	lzcnt  %r15,%r12
+[ 	]*[a-f0-9]+:	f3 48 0f bd 17       	lzcnt  \(%rdi\),%rdx
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bd 0c 24 	lzcnt  \(%r12d\),%r9
+[ 	]*[a-f0-9]+:	f3 4d 0f bd d3       	lzcnt  %r11,%r10
+[ 	]*[a-f0-9]+:	67 f3 4c 0f bd 2c dd fe ca 00 00 	lzcnt  0xcafe\(,%ebx,8\),%r13
+[ 	]*[a-f0-9]+:	f3 48 0f bd c0       	lzcnt  %rax,%rax
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc f2    	tzcnt  %r10w,%r14w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc 86 7a 73 00 00 	tzcnt  0x737a\(%r14\),%ax
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc d0    	tzcnt  %ax,%r10w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc f7    	tzcnt  %r15w,%si
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc 3c 24 	tzcnt  \(%r12\),%r15w
+[ 	]*[a-f0-9]+:	67 66 f3 0f bc 22    	tzcnt  \(%edx\),%sp
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc 28    	tzcnt  \(%rax\),%r13w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc ec    	tzcnt  %r12w,%bp
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bc 81 ad 3c 00 00 	tzcnt  0x3cad\(%r9d\),%ax
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc 44 12 06 	tzcnt  0x6\(%r10,%rdx,1\),%ax
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc dd    	tzcnt  %r13w,%r11w
+[ 	]*[a-f0-9]+:	67 66 f3 43 0f bc 0c 32 	tzcnt  \(%r10d,%r14d,1\),%cx
+[ 	]*[a-f0-9]+:	67 66 f3 45 0f bc a4 9a 44 ae d0 4c 	tzcnt  0x4cd0ae44\(%r10d,%ebx,4\),%r12w
+[ 	]*[a-f0-9]+:	67 66 f3 45 0f bc 3f 	tzcnt  \(%r15d\),%r15w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc 08    	tzcnt  \(%r8\),%r9w
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bc 01 	tzcnt  \(%r9d\),%ax
+[ 	]*[a-f0-9]+:	f3 41 0f bc 10       	tzcnt  \(%r8\),%edx
+[ 	]*[a-f0-9]+:	67 f3 44 0f bc 1e    	tzcnt  \(%esi\),%r11d
+[ 	]*[a-f0-9]+:	f3 41 0f bc 02       	tzcnt  \(%r10\),%eax
+[ 	]*[a-f0-9]+:	f3 45 0f bc 7c 16 c3 	tzcnt  -0x3d\(%r14,%rdx,1\),%r15d
+[ 	]*[a-f0-9]+:	f3 41 0f bc 75 00    	tzcnt  0x0\(%r13\),%esi
+[ 	]*[a-f0-9]+:	f3 44 0f bc 27       	tzcnt  \(%rdi\),%r12d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 01       	tzcnt  \(%ecx\),%eax
+[ 	]*[a-f0-9]+:	f3 47 0f bc ac e9 bc 9a ff ff 	tzcnt  -0x6544\(%r9,%r13,8\),%r13d
+[ 	]*[a-f0-9]+:	f3 0f bc e0          	tzcnt  %eax,%esp
+[ 	]*[a-f0-9]+:	f3 45 0f bc c7       	tzcnt  %r15d,%r8d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 3c 0d f1 ff ff ff 	tzcnt  -0xf\(,%ecx,1\),%edi
+[ 	]*[a-f0-9]+:	f3 45 0f bc 09       	tzcnt  \(%r9\),%r9d
+[ 	]*[a-f0-9]+:	f3 0f bc 21          	tzcnt  \(%rcx\),%esp
+[ 	]*[a-f0-9]+:	f3 43 0f bc 2c 10    	tzcnt  \(%r8,%r10,1\),%ebp
+[ 	]*[a-f0-9]+:	f3 46 0f bc 34 17    	tzcnt  \(%rdi,%r10,1\),%r14d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 30       	tzcnt  \(%eax\),%esi
+[ 	]*[a-f0-9]+:	67 f3 4c 0f bc 0f    	tzcnt  \(%edi\),%r9
+[ 	]*[a-f0-9]+:	f3 49 0f bc 29       	tzcnt  \(%r9\),%rbp
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bc 3c 9f 	tzcnt  \(%r15d,%ebx,4\),%r15
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 26       	tzcnt  \(%r14\),%r12
+[ 	]*[a-f0-9]+:	f3 4e 0f bc 14 05 0e 8a f2 62 	tzcnt  0x62f28a0e\(,%r8,1\),%r10
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 34 30    	tzcnt  \(%r8,%rsi,1\),%r14
+[ 	]*[a-f0-9]+:	67 f3 48 0f bc 06    	tzcnt  \(%esi\),%rax
+[ 	]*[a-f0-9]+:	f3 49 0f bc c5       	tzcnt  %r13,%rax
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 81 6c 3d 00 00 	tzcnt  0x3d6c\(%r9\),%r8
+[ 	]*[a-f0-9]+:	f3 4c 0f bc f8       	tzcnt  %rax,%r15
+[ 	]*[a-f0-9]+:	f3 4a 0f bc 24 4d 00 00 00 00 	tzcnt  0x0\(,%r9,2\),%rsp
+[ 	]*[a-f0-9]+:	67 f3 4a 0f bc 1c e5 00 00 00 00 	tzcnt  0x0\(,%r12d,8\),%rbx
+[ 	]*[a-f0-9]+:	f3 4c 0f bc 1c 16    	tzcnt  \(%rsi,%rdx,1\),%r11
+[ 	]*[a-f0-9]+:	f3 4a 0f bc 3c a9    	tzcnt  \(%rcx,%r13,4\),%rdi
+[ 	]*[a-f0-9]+:	f3 49 0f bc 44 c3 f1 	tzcnt  -0xf\(%r11,%rax,8\),%rax
+[ 	]*[a-f0-9]+:	f3 49 0f bc 00       	tzcnt  \(%r8\),%rax
+
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.s b/gas/testsuite/gas/i386/x86-64-bmi.s
new file mode 100644
index 0000000..e4059ec
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.s
@@ -0,0 +1,263 @@
+
+	.allow_index_reg
+	.text
+	
+_start:
+
+    ANDN     %eax,%r15d,%eax
+    ANDN     (%rsi,%rcx),%eax,%r10d
+    ANDN     (%r14d),%esi,%ebp
+    ANDN     (%r13),%edi,%r15d
+    ANDN     %esi,%r12d,%r15d
+    ANDN     (%r8d,%r10d,2),%r14d,%edi
+    ANDN     (%r9d),%r10d,%r13d
+    ANDN     (,%r15d,4),%ecx,%r9d
+    ANDN     (,%r8,4),%r8d,%esp
+    ANDN     (%rdi,%rax),%r8d,%r12d
+    ANDN     (%r13d,%ebx),%r11d,%eax
+    ANDN     %edx,%ebx,%esi
+    ANDN     (%r9),%esp,%edx
+    ANDN     (%rdi),%r15d,%ecx
+    ANDN     (%edi),%ebp,%r14d
+    ANDN     -0x39444A06(%rbx,%r8,4),%r10d,%eax
+    ANDN     (%r10d),%rax,%rax
+    ANDN     (%r14d),%r15,%rdx
+    ANDN     0x5B93(%r15,%r9),%rsp,%r15
+    ANDN     (%r9),%r11,%r9
+    ANDN     (,%eax,2),%r15,%rdi
+    ANDN     %rbp,%rsi,%r11
+    ANDN     (%r13),%rbx,%r8
+    ANDN     %rax,%rdi,%r10
+    ANDN     %rsp,%r12,%rsp
+    ANDN     (%esi),%r10,%r15
+    ANDN     (%edx),%rax,%r15
+    ANDN     (%r15d),%r8,%rsi
+    ANDN     (%r8d),%r15,%r12
+    ANDN     %rdi,%r15,%rbp
+    ANDN     (,%r12,8),%rbp,%rcx
+    ANDN     (%rdx),%rcx,%r13
+    BEXTR    %r15d,%eax,%eax
+    BEXTR    %eax,%r10d,%r15d
+    BEXTR    %edx,(%r15d,%r9d,8),%ecx
+    BEXTR    %ebp,(%r13,%r15),%r10d
+    BEXTR    %r11d,%r15d,%ebp
+    BEXTR    %r15d,(%r13,%r14),%esp
+    BEXTR    %r9d,0xDEAD(%r11d,%r8d,8),%r8d
+    BEXTR    %r11d,0x1(%r12d,%eax),%eax
+    BEXTR    %r10d,-0xC(%r14d),%r14d
+    BEXTR    %eax,(%rax),%r11d
+    BEXTR    %ebx,(%r12d),%edx
+    BEXTR    %esi,(%eax),%r13d
+    BEXTR    %eax,%ebp,%ebx
+    BEXTR    %eax,(%r12),%eax
+    BEXTR    %ebp,(%r10d,%eax),%eax
+    BEXTR    %r13d,-0x67(%ebx,%eax),%eax
+    BEXTR    %r15,0xCAFE(%r11,%r15,2),%rax
+    BEXTR    %r14,0xCAFE(%r9),%r14
+    BEXTR    %rdi,%rax,%r15
+    BEXTR    %rax,(%edx),%r13
+    BEXTR    %rdx,(%r15),%r10
+    BEXTR    %r10,%r15,%rbp
+    BEXTR    %r12,(%esi),%rdi
+    BEXTR    %rcx,%r12,%r12
+    BEXTR    %rbp,%r8,%rbx
+    BEXTR    %rbx,(%r12),%rsp
+    BEXTR    %r9,(%r13),%r11
+    BEXTR    %r11,(%r8),%rsi
+    BEXTR    %rsi,%rcx,%rdx
+    BEXTR    %r13,0x3(%r10d,%r9d,1),%r15
+    BEXTR    %rax,(%r15d),%rax
+    BEXTR    %r15,(%r8d),%rcx
+    BLSI     -0xD(,%r15d,2),%esi
+    BLSI     %r15d,%r15d
+    BLSI     %eax,%eax
+    BLSI     (%r9),%r10d
+    BLSI     %ebp,%r9d
+    BLSI     0x5(,%r9,2),%edx
+    BLSI     -0x6A(,%r11,2),%ecx
+    BLSI     (%ecx),%ebp
+    BLSI     (%edi),%r11d
+    BLSI     -0x7(%rdi),%r8d
+    BLSI     (%r8d),%r13d
+    BLSI     (%r10),%ebx
+    BLSI     0xCAFE(,%rax),%edi
+    BLSI     (%esi),%eax
+    BLSI     %r9d,%eax
+    BLSI     -0x67(%r10d,%edi,1),%eax
+    BLSI     0xF(%r10),%r15
+    BLSI     %r15,%rax
+    BLSI     %rax,%rsp
+    BLSI     (%eax),%r10
+    BLSI     (%r8d),%r13
+    BLSI     0x85(%edi,%r9d,8),%r14
+    BLSI     %r10,%r12
+    BLSI     (%r11),%r8
+    BLSI     -0x472429E0(%r15),%r9
+    BLSI     (%edi),%rdx
+    BLSI     (,%edx,4),%rbx
+    BLSI     (%ebx),%rdi
+    BLSI     0xDEAD(%r10),%rcx
+    BLSI     0x1B(%r15,%r14,8),%rdi
+    BLSI     (%rbx),%r11
+    BLSI     0xA(%r8,%r9),%rax
+    BLSMSK   %eax,%eax
+    BLSMSK   (,%r9,4),%esi
+    BLSMSK   (,%edi,2),%r15d
+    BLSMSK   (%rdi),%esp
+    BLSMSK   (%r13d),%ecx
+    BLSMSK   %r9d,%r14d
+    BLSMSK   (%rdx),%r8d
+    BLSMSK   (%esi),%r12d
+    BLSMSK   0x65F822C5(%r13,%rdx),%r11d
+    BLSMSK   -0x3(%ebx,%ecx,1),%r10d
+    BLSMSK   %r15d,%ebp
+    BLSMSK   %esi,%r13d
+    BLSMSK   (%r15),%edx
+    BLSMSK   (%r14),%r10d
+    BLSMSK   %ebp,%edi
+    BLSMSK   (%rcx,%r12),%ebx
+    BLSMSK   %r15,%rdx
+    BLSMSK   (%rax,%rcx,8),%rax
+    BLSMSK   %r9,%r15
+    BLSMSK   (%r15d),%r8
+    BLSMSK   %rax,%r15
+    BLSMSK   -0x3(%rsi),%r12
+    BLSMSK   -0x0(%rdx,%rdx),%rsi
+    BLSMSK   (%r14),%rbx
+    BLSMSK   (%r15),%rdi
+    BLSMSK   -0xDC(,%r12),%rbp
+    BLSMSK   (%ebx),%r11
+    BLSMSK   0x43B8(,%r14d),%rax
+    BLSMSK   %rdx,%r13
+    BLSMSK   %rbp,%r9
+    BLSMSK   (%eax),%rsp
+    BLSMSK   (%r14d),%r15
+    BLSR     %r15d,%r15d
+    BLSR     %eax,%r9d
+    BLSR     0x1(,%edx),%r14d
+    BLSR     %edx,%ecx
+    BLSR     (%rcx,%r14,2),%ebx
+    BLSR     0x464A(,%r9d,4),%eax
+    BLSR     (%rsi),%esp
+    BLSR     (%ecx),%esi
+    BLSR     (%edi),%esi
+    BLSR     (,%edi,2),%r10d
+    BLSR     (%rdx),%r11d
+    BLSR     (%r11),%r13d
+    BLSR     %r9d,%r8d
+    BLSR     %edi,%edx
+    BLSR     (%ebx),%eax
+    BLSR     (%rax),%edi
+    BLSR     (%r11),%r15
+    BLSR     0x3(,%ecx),%r9
+    BLSR     (%rsi),%rsp
+    BLSR     (%r13),%rax
+    BLSR     %r15,%rdx
+    BLSR     (%r14d),%r8
+    BLSR     (%r14),%rax
+    BLSR     (%r8),%rbp
+    BLSR     %rdx,%r11
+    BLSR     (%edx),%r15
+    BLSR     0x337E(,%r12d),%rbx
+    BLSR     (%rax),%rcx
+    BLSR     %rbp,%rsp
+    BLSR     %rax,%r10
+    BLSR     0x67(%r13,%r12,4),%r12
+    BLSR     (,%r13d,1),%rdi
+    LZCNT    0x1F5A(,%r8d),%r13w
+    LZCNT    %ax,%r12w
+    LZCNT    (%r9),%r10w
+    LZCNT    %r13w,%ax
+    LZCNT    -0x67(,%rax,8),%r15w
+    LZCNT    (%r13,%rdx),%di
+    LZCNT    (%rdi),%bp
+    LZCNT    (%r11),%r8w
+    LZCNT    %r15w,%si
+    LZCNT    (%r14d),%sp
+    LZCNT    (%rcx),%r9w
+    LZCNT    0x9AE7(%r11,%rbx,8),%r9w
+    LZCNT    %si,%si
+    LZCNT    (%ebx),%cx
+    LZCNT    (%r10d),%bx
+    LZCNT    %r9w,%r14w
+    LZCNT    (%r13d),%r15d
+    LZCNT    %edi,%esp
+    LZCNT    (%r14d),%r13d
+    LZCNT    (%r14),%edx
+    LZCNT    %r15d,%r11d
+    LZCNT    %eax,%eax
+    LZCNT    (%r8),%esi
+    LZCNT    %r9d,%r15d
+    LZCNT    (%r12),%r8d
+    LZCNT    %r8d,%ebp
+    LZCNT    (%r10d),%ebx
+    LZCNT    (%r12,%rcx),%edi
+    LZCNT    (%rdi),%r15d
+    LZCNT    (%edi),%r15d
+    LZCNT    %r12d,%r10d
+    LZCNT    (,%r13,1),%eax
+    LZCNT    (%r13d),%rbp
+    LZCNT    (%r10d),%r8
+    LZCNT    (%esi),%rax
+    LZCNT    %rbx,%r13
+    LZCNT    (%r9),%r15
+    LZCNT    %rdx,%rcx
+    LZCNT    (,%r13,2),%rax
+    LZCNT    (%eax),%rsi
+    LZCNT    (%r15d),%rsp
+    LZCNT    (,%r15d,4),%r11
+    LZCNT    %r15,%r12
+    LZCNT    (%rdi),%rdx
+    LZCNT    (%r12d),%r9
+    LZCNT    %r11,%r10
+    LZCNT    0xCAFE(,%ebx,8),%r13
+    LZCNT    %rax,%rax
+    TZCNT    %r10w,%r14w
+    TZCNT    0x737A(%r14),%ax
+    TZCNT    %ax,%r10w
+    TZCNT    %r15w,%si
+    TZCNT    (%r12),%r15w
+    TZCNT    (%edx),%sp
+    TZCNT    (%rax),%r13w
+    TZCNT    %r12w,%bp
+    TZCNT    0x3CAD(%r9d),%ax
+    TZCNT    0x6(%r10,%rdx),%ax
+    TZCNT    %r13w,%r11w
+    TZCNT    (%r10d,%r14d),%cx
+    TZCNT    0x4CD0AE44(%r10d,%ebx,4),%r12w
+    TZCNT    (%r15d),%r15w
+    TZCNT    (%r8),%r9w
+    TZCNT    (%r9d),%ax
+    TZCNT    (%r8),%edx
+    TZCNT    (%esi),%r11d
+    TZCNT    (%r10),%eax
+    TZCNT    -0x3D(%r14,%rdx),%r15d
+    TZCNT    (%r13),%esi
+    TZCNT    (%rdi),%r12d
+    TZCNT    (%ecx),%eax
+    TZCNT    -0x6544(%r9,%r13,8),%r13d
+    TZCNT    %eax,%esp
+    TZCNT    %r15d,%r8d
+    TZCNT    -0xF(,%ecx),%edi
+    TZCNT    (%r9),%r9d
+    TZCNT    (%rcx),%esp
+    TZCNT    (%r8,%r10),%ebp
+    TZCNT    (%rdi,%r10),%r14d
+    TZCNT    (%eax),%esi
+    TZCNT    (%edi),%r9
+    TZCNT    (%r9),%rbp
+    TZCNT    (%r15d,%ebx,4),%r15
+    TZCNT    (%r14),%r12
+    TZCNT    0x62F28A0E(,%r8),%r10
+    TZCNT    (%r8,%rsi),%r14
+    TZCNT    (%esi),%rax
+    TZCNT    %r13,%rax
+    TZCNT    0x3D6C(%r9),%r8
+    TZCNT    %rax,%r15
+    TZCNT    (,%r9,2),%rsp
+    TZCNT    (,%r12d,8),%rbx
+    TZCNT    (%rsi,%rdx),%r11
+    TZCNT    (%rcx,%r13,4),%rdi
+    TZCNT    -0xF(%r11,%rax,8),%rax
+    TZCNT    (%r8),%rax
+
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b18b6b9..8f1b4bd 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,42 @@
+2010-12-20  Quentin Neill  <quentin.neill@amd.com>
+
+	* i386-dis.c (REG_XOP_BMI_F3): New.
+	(PREFIX_BMI_F30F): New.
+	(dis386_twobyte): Redirect to PREFIX_BMI_F30F entry.
+	(reg_table): Add REG_XOP_BMI_F3 table.
+	(prefix_table): Add PREFIX_BMI_F30F table.
+	(x86_64_table): Add andn, bextr, and redirect to
+	REG_XOP_BMI_F3 entry.
+
+	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS, CpuBMI.
+	(cpu_flags): Add CpuBMI.
+	(opcode_modifiers): Define bitfield ModrmRegExt.
+
+	* i386-opc.h (CpuBMI) New.
+	(i386_cpu_flags): Add bit cpubmi.
+	(enum): New ModrmRegExt enum, rename VexVVVV
+	encoding from VEX.LWP to VEX.VRM, add VexOpcode
+	encoding XOP02, and add VexSources enoding
+	XOP2REVSOURCES.
+	(i386_opcode_modifier): Add modrmregext bit, increase
+	vexvvvv bit width to 3.
+
+	* i386-opc.tbl (andn): Added.
+	(andn): Added.
+	(bextr): Added.
+	(bextr): Added.
+	(blsi): Added.
+	(blsi): Added.
+	(blsmsk): Added.
+	(blsmsk): Added.
+	(blsr): Added.
+	(blsr): Added.
+	(tzcnt): Added.
+
+	* i386-init.h: Regenerated.
+
+	* i386-tbl.h: Regenerated
+
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f2def13..30ea470 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -599,7 +599,8 @@ enum
   REG_VEX_0F73,
   REG_VEX_0FAE,
   REG_XOP_LWPCB,
-  REG_XOP_LWP
+  REG_XOP_LWP,
+  REG_XOP_BMI_F3
 };
 
 enum
@@ -1068,7 +1069,8 @@ enum
   PREFIX_VEX_0F3A7D,
   PREFIX_VEX_0F3A7E,
   PREFIX_VEX_0F3A7F,
-  PREFIX_VEX_0F3ADF
+  PREFIX_VEX_0F3ADF,
+  PREFIX_BMI_F30F
 };
 
 enum
@@ -2158,7 +2160,7 @@ static const struct dis386 dis386_twobyte[] = {
   { "ud1",		{ XX } },
   { REG_TABLE (REG_0FBA) },
   { "btcS",		{ Ev, Gv } },
-  { "bsfS",		{ Gv, Ev } },
+  { PREFIX_TABLE (PREFIX_BMI_F30F) },
   { PREFIX_TABLE (PREFIX_0FBD) },
   { "movs{bR|x}",	{ Gv, Eb } },
   { "movs{wR|x}",	{ Gv, Ew } }, /* yes, there really is movsww ! */
@@ -2759,6 +2761,13 @@ static const struct dis386 reg_table[][8] = {
     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
     { "lwpval",	{ { OP_LWP_E, 0 }, Ed, Iq } },
   },
+  /* REG_XOP_BMI_F3 */
+  {
+    { Bad_Opcode },
+    { "blsr",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blsmsk",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blsi",	{ { OP_LWP_E, 0 }, Ev } },
+  },
 };
 
 static const struct dis386 prefix_table[][4] = {
@@ -5354,6 +5363,14 @@ static const struct dis386 prefix_table[][4] = {
     { Bad_Opcode },
     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
   },
+
+  /* PREFIX_BMI_F30F */
+  {
+    { "bsfS",		{ Gv, Ev } },
+    { "tzcntS",		{ Gv, Ev } },
+    { "bsfS",		{ Gv, Ev } },
+    { "tzcntS",		{ Gv, Ev } },
+  },
 };
 
 static const struct dis386 x86_64_table[][2] = {
@@ -7828,12 +7845,12 @@ static const struct dis386 vex_table[][256] = {
     /* f0 */
     { Bad_Opcode },
     { Bad_Opcode },
+    { "andn",	{ Gv, { OP_LWP_E, 0 }, Ev } },
+    { REG_TABLE (REG_XOP_BMI_F3) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { "bextr",	{ Gv, Ev, { OP_LWP_E, 0 } } },
     /* f8 */
     { Bad_Opcode },
     { Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index ee06338..c4ed21f 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -140,6 +140,8 @@ static initializer cpu_flag_init[] =
     "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" },
   { "CPU_LWP_FLAGS",
     "CpuLWP" },
+  { "CPU_BMI_FLAGS",
+    "CpuBMI" },
   { "CPU_MOVBE_FLAGS",
     "CpuMovbe" },
   { "CPU_RDTSCP_FLAGS",
@@ -320,6 +322,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuFMA4),
   BITFIELD (CpuXOP),
   BITFIELD (CpuLWP),
+  BITFIELD (CpuBMI),
   BITFIELD (CpuLM),
   BITFIELD (CpuMovbe),
   BITFIELD (CpuEPT),
@@ -340,6 +343,7 @@ static bitfield opcode_modifiers[] =
   BITFIELD (W),
   BITFIELD (S),
   BITFIELD (Modrm),
+  BITFIELD (ModrmRegExt),
   BITFIELD (ShortForm),
   BITFIELD (Jump),
   BITFIELD (JumpDword),
diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h
index fe546b6..d5697de 100644
Binary files a/opcodes/i386-init.h and b/opcodes/i386-init.h differ
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index fe4fe97..43c0d14 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -110,6 +110,8 @@ enum
   CpuXOP,
   /* LWP support required */
   CpuLWP,
+  /* BMI support required */
+  CpuBMI,
   /* MOVBE Instruction support required */
   CpuMovbe,
   /* EPT Instructions required */
@@ -186,6 +188,7 @@ typedef union i386_cpu_flags
       unsigned int cpufma4:1;
       unsigned int cpuxop:1;
       unsigned int cpulwp:1;
+      unsigned int cpubmi:1;
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
@@ -215,6 +218,8 @@ enum
   S,
   /* insn has a modrm byte. */
   Modrm,
+  /* instruction has opcode extension in ModRM reg.  */
+  ModrmRegExt,
   /* register is in low 3 bits of opcode */
   ShortForm,
   /* special case for jump insns.  */
@@ -304,12 +309,12 @@ enum
 	For assembler, there are no difference between VEX.NDS and
 	VEX.DDS.
      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
-     3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
+     3. VEX.VRM.  Register destination is encoded in VEX.vvvv and one
 	of the operands can access a memory location.
    */
 #define VEXXDS	1
 #define VEXNDD	2
-#define VEXLWP	3
+#define VEXVRM	3
   VexVVVV,
   /* How the VEX.W bit is used:
      0: Set by the REX.W bit.
@@ -333,14 +338,17 @@ enum
 #define XOP08		3
 #define XOP09		4
 #define XOP0A		5
+#define XOP02		6
   VexOpcode,
   /* number of VEX source operands:
      0: <= 2 source operands.
      1: 2 XOP source operands.
      2: 3 source operands.
+     3: 2 XOP source operands but order reversed.
    */
 #define XOP2SOURCES	1
 #define VEX3SOURCES	2
+#define XOP2REVSOURCES	3
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
@@ -366,6 +374,7 @@ typedef struct i386_opcode_modifier
   unsigned int w:1;
   unsigned int s:1;
   unsigned int modrm:1;
+  unsigned int modrmregext:1;
   unsigned int shortform:1;
   unsigned int jump:1;
   unsigned int jumpdword:1;
@@ -401,7 +410,7 @@ typedef struct i386_opcode_modifier
   unsigned int rex64:1;
   unsigned int ugh:1;
   unsigned int vex:2;
-  unsigned int vexvvvv:2;
+  unsigned int vexvvvv:3;
   unsigned int vexw:2;
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index f63919e..23eb2f2 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2733,6 +2733,19 @@ lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_
 lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
 lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
 
+// BMI instructions
+andn,    3, 0xF2,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32, Reg32 }
+andn,    3, 0xF2,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64, Reg64 }
+bextr,   3, 0xF7,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+bextr,   3, 0xF7,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64, Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsi,    2, 0xF3,      0x3, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsi,    2, 0xF3,      0x3, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsmsk,  2, 0xF3,      0x2, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsmsk,  2, 0xF3,      0x2, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsr,    2, 0xF3,      0x1, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsr,    2, 0xF3,      0x1, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+tzcnt,   2, 0xf30fbc, None, 2, CpuBMI, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
+
 // AMD 3DNow! instructions.
 
 prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 5c4e7e8..72e1173 100644
Binary files a/opcodes/i386-tbl.h and b/opcodes/i386-tbl.h differ