Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.82
diff -u -p -r1.82 mips-opc.c
--- opcodes/mips-opc.c	11 Nov 2010 10:23:39 -0000	1.82
+++ opcodes/mips-opc.c	1 Dec 2010 02:54:33 -0000
@@ -1838,28 +1838,40 @@ const struct mips_opcode mips_builtin_op
 /* ST Microelectronics Loongson-2E and -2F.  */
 {"mult.g",	"d,s,t",	0x7c000018,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"mult.g",	"d,s,t",	0x70000010,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsmult",	"d,s,t",	0x70000010,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"multu.g",	"d,s,t",	0x7c000019,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"multu.g",	"d,s,t",	0x70000012,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsmultu",	"d,s,t",	0x70000012,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"dmult.g",	"d,s,t",	0x7c00001c,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"dmult.g",	"d,s,t",	0x70000011,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdmult",	"d,s,t",	0x70000011,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"dmultu.g",	"d,s,t",	0x7c00001d,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"dmultu.g",	"d,s,t",	0x70000013,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdmultu",	"d,s,t",	0x70000013,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"div.g",	"d,s,t",	0x7c00001a,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"div.g",	"d,s,t",	0x70000014,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdiv",	"d,s,t",	0x70000014,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"divu.g",	"d,s,t",	0x7c00001b,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"divu.g",	"d,s,t",	0x70000016,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdivu",	"d,s,t",	0x70000016,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"ddiv.g",	"d,s,t",	0x7c00001e,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"ddiv.g",	"d,s,t",	0x70000015,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsddiv",	"d,s,t",	0x70000015,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"ddivu.g",	"d,s,t",	0x7c00001f,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"ddivu.g",	"d,s,t",	0x70000017,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsddivu",	"d,s,t",	0x70000017,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"mod.g",	"d,s,t",	0x7c000022,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"mod.g",	"d,s,t",	0x7000001c,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsmod",	"d,s,t",	0x7000001c,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"modu.g",	"d,s,t",	0x7c000023,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"modu.g",	"d,s,t",	0x7000001e,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsmodu",	"d,s,t",	0x7000001e,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"dmod.g",	"d,s,t",	0x7c000026,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"dmod.g",	"d,s,t",	0x7000001d,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdmod",	"d,s,t",	0x7000001d,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"dmodu.g",	"d,s,t",	0x7c000027,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"dmodu.g",	"d,s,t",	0x7000001f,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdmodu",	"d,s,t",	0x7000001f,	0xfc0007ff,	WR_d|RD_s|RD_t,	0,	IL3A	},
 {"packsshb",	"D,S,T",	0x47400002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"packsshb",	"D,S,T",	0x4b400002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"packsswh",	"D,S,T",	0x47200002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},