This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH,ppc] prohibit string instructions on processors that don't support them
- From: Nathan Froyd <froydnj at codesourcery dot com>
- To: binutils at sourceware dot org
- Date: Wed, 25 Aug 2010 12:40:08 -0700
- Subject: [PATCH,ppc] prohibit string instructions on processors that don't support them
Processors in the E500 family (both the SPE and oddly-named e500mc*
variety) do not support load/store string instructions. This patch adds
a PPC_OPCODE_STRING flag for marking these instructions so the assembler
can give appropriate error messages when attempting to assemble such
instructions.
I've attempted to add the PPC_OPCODE_STRING flag to only processors that
support it; when in doubt, I have added it, on the grounds that doing so
won't break anything. I left the flag off the "efs" and "spe"
pseudo-CPUs; I know of no embedded floating-point CPU that supports
string instructions.
Tested on powerpc-eabi. OK to commit?
-Nathan
include/opcode/
* ppc.h (PPC_OPCODE_STRING): Define.
opcodes/
* ppc-dis.c (ppc_opts): Add PPC_OPCODE_STRING where appropriate.
* ppc-opc.c (PPCSTR): Define.
(powerpc_opcodes) [lswx,lswi,stswx,stswi]: Use PPCSTR instead of
PPCCOM.
Index: include/opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.42
diff -u -u -r1.42 ppc.h
--- include/opcode/ppc.h 3 Jul 2010 06:51:53 -0000 1.42
+++ include/opcode/ppc.h 25 Aug 2010 19:33:11 -0000
@@ -174,6 +174,9 @@
/* Opcode which is supported by the e500 family */
#define PPC_OPCODE_E500 0x100000000ull
+/* Opcode is supported by CPUs with string instruction support. */
+#define PPC_OPCODE_STRING 0x200000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.50
diff -u -u -r1.50 ppc-dis.c
--- opcodes/ppc-dis.c 3 Jul 2010 08:27:23 -0000 1.50
+++ opcodes/ppc-dis.c 25 Aug 2010 19:33:11 -0000
@@ -50,55 +50,57 @@
};
struct ppc_mopt ppc_opts[] = {
- { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403),
+ { "403", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_STRING),
0 },
- { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405),
+ { "405", (PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405
+ | PPC_OPCODE_STRING),
0 },
{ "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
- | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
+ | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI | PPC_OPCODE_STRING),
0 },
{ "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
- | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
+ | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI | PPC_OPCODE_STRING),
0 },
{ "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
- | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
+ | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5
+ | PPC_OPCODE_STRING),
0 },
- { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601),
+ { "601", (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_STRING),
0 },
- { "603", (PPC_OPCODE_PPC),
+ { "603", (PPC_OPCODE_PPC | PPC_OPCODE_STRING),
0 },
- { "604", (PPC_OPCODE_PPC),
+ { "604", (PPC_OPCODE_PPC | PPC_OPCODE_STRING),
0 },
- { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64),
+ { "620", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_STRING),
0 },
- { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
+ { "7400", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC | PPC_OPCODE_STRING),
0 },
- { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
+ { "7410", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC | PPC_OPCODE_STRING),
0 },
- { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
+ { "7450", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC | PPC_OPCODE_STRING),
0 },
- { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC),
+ { "7455", (PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC | PPC_OPCODE_STRING),
0 },
- { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS)
+ { "750cl", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS | PPC_OPCODE_STRING)
, 0 },
{ "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64
- | PPC_OPCODE_A2),
+ | PPC_OPCODE_A2 | PPC_OPCODE_STRING),
0 },
- { "altivec", (PPC_OPCODE_PPC),
+ { "altivec", (PPC_OPCODE_PPC | PPC_OPCODE_STRING),
PPC_OPCODE_ALTIVEC },
{ "any", 0,
PPC_OPCODE_ANY },
- { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
+ { "booke", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_STRING),
0 },
- { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE),
+ { "booke32", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_STRING),
0 },
{ "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
- | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC),
+ | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC | PPC_OPCODE_STRING),
0 },
- { "com", (PPC_OPCODE_COMMON),
+ { "com", (PPC_OPCODE_COMMON | PPC_OPCODE_STRING),
0 },
- { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300),
+ { "e300", (PPC_OPCODE_PPC | PPC_OPCODE_E300 | PPC_OPCODE_STRING),
0 },
{ "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
@@ -121,55 +123,61 @@
0 },
{ "efs", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
0 },
- { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
+ { "power4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_STRING),
0 },
{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
- | PPC_OPCODE_POWER5),
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_STRING),
0 },
{ "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
- | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC
+ | PPC_OPCODE_STRING),
0 },
{ "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
- | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
+ | PPC_OPCODE_STRING),
0 },
- { "ppc", (PPC_OPCODE_PPC),
+ { "ppc", (PPC_OPCODE_PPC | PPC_OPCODE_STRING),
0 },
- { "ppc32", (PPC_OPCODE_PPC),
+ { "ppc32", (PPC_OPCODE_PPC | PPC_OPCODE_STRING),
0 },
- { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64),
+ { "ppc64", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_STRING),
0 },
- { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE),
+ { "ppc64bridge", (PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE | PPC_OPCODE_STRING),
0 },
- { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS),
+ { "ppcps", (PPC_OPCODE_PPC | PPC_OPCODE_PPCPS | PPC_OPCODE_STRING),
0 },
- { "pwr", (PPC_OPCODE_POWER),
+ { "pwr", (PPC_OPCODE_POWER | PPC_OPCODE_STRING),
0 },
- { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
+ { "pwr2", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_STRING),
0 },
- { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4),
+ { "pwr4", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_STRING),
0 },
{ "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
- | PPC_OPCODE_POWER5),
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_STRING),
0 },
{ "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
- | PPC_OPCODE_POWER5),
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_STRING),
0 },
{ "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
- | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC),
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC
+ | PPC_OPCODE_STRING),
0 },
{ "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
- | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
+ | PPC_OPCODE_STRING),
0 },
- { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
+ { "pwrx", (PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_STRING),
0 },
{ "spe", (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
PPC_OPCODE_SPE },
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
- | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
+ | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN | PPC_OPCODE_STRING),
0 },
- { "vsx", (PPC_OPCODE_PPC),
+ { "vsx", (PPC_OPCODE_PPC | PPC_OPCODE_STRING),
PPC_OPCODE_VSX },
};
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.134
diff -u -u -r1.134 ppc-opc.c
--- opcodes/ppc-opc.c 3 Jul 2010 06:51:54 -0000 1.134
+++ opcodes/ppc-opc.c 25 Aug 2010 19:33:11 -0000
@@ -1946,6 +1946,7 @@
#define TITAN PPC_OPCODE_TITAN
#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
#define E500 PPC_OPCODE_E500
+#define PPCSTR PPC_OPCODE_STRING
/* The opcode table.
@@ -4420,7 +4421,7 @@
{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RT, RA0, RB}},
-{"lswx", X(31,533), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
+{"lswx", X(31,533), X_MASK, PPCSTR, PPCNONE, {RT, RA0, RB}},
{"lsx", X(31,533), X_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
{"lwbrx", X(31,534), X_MASK, PPCCOM, PPCNONE, {RT, RA0, RB}},
@@ -4466,7 +4467,7 @@
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
-{"lswi", X(31,597), X_MASK, PPCCOM, PPCNONE, {RT, RA0, NB}},
+{"lswi", X(31,597), X_MASK, PPCSTR, PPCNONE, {RT, RA0, NB}},
{"lsi", X(31,597), X_MASK, PWRCOM, PPCNONE, {RT, RA0, NB}},
{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
@@ -4517,7 +4518,7 @@
{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, PPCNONE, {RS, RA0, RB}},
-{"stswx", X(31,661), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
+{"stswx", X(31,661), X_MASK, PPCSTR, PPCNONE, {RS, RA0, RB}},
{"stsx", X(31,661), X_MASK, PWRCOM, PPCNONE, {RS, RA0, RB}},
{"stwbrx", X(31,662), X_MASK, PPCCOM, PPCNONE, {RS, RA0, RB}},
@@ -4559,7 +4560,7 @@
{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}},
{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}},
-{"stswi", X(31,725), X_MASK, PPCCOM, PPCNONE, {RS, RA0, NB}},
+{"stswi", X(31,725), X_MASK, PPCSTR, PPCNONE, {RS, RA0, NB}},
{"stsi", X(31,725), X_MASK, PWRCOM, PPCNONE, {RS, RA0, NB}},
{"sthcx.", XRC(31,726,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}},
Index: opcodes/sparc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/sparc-dis.c,v
retrieving revision 1.17
diff -u -u -r1.17 sparc-dis.c
--- opcodes/sparc-dis.c 27 Jun 2010 04:07:55 -0000 1.17
+++ opcodes/sparc-dis.c 25 Aug 2010 19:33:11 -0000
@@ -529,9 +529,6 @@
field of the opcode table. */
int found_plus = 0;
- /* Nonzero means we have an annulled branch. */
- int is_annulled = 0;
-
/* Do we have an `add' or `or' instruction combining an
immediate with rs1? */
if (opcode->match == 0x80102000) /* or */
@@ -566,7 +563,6 @@
{
case 'a':
(*info->fprintf_func) (stream, "a");
- is_annulled = 1;
++s;
continue;
case 'N':