Fix default Thumb NOP instruction

[Daniel Jacobowitz <dan at codesourcery dot com>]

Nick fixed a bug last year which caused .syntax unified to
automatically generate a Thumb-2 nop instruction.  I discovered a
related problem in the same area, which was not covered by the first
fix.  cpu_variant is by default permissive; so if you don't give any
-mcpu, you now get Thumb-2 instructions.  I've adjusted the check
to match the one in arm_handle_align.

I can see now I flubbed the testcase; it's missing .syntax unified.
Will retest and fix.

Tested on arm-none-eabi, checked in.

-- 
Daniel Jacobowitz
CodeSourcery

2010-01-13  Daniel Jacobowitz  <dan@codesourcery.com>

	* config/tc-arm.c (do_t_nop): Correct check for Thumb-2 NOP.

	* gas/arm/thumb-nop.d, gas/arm/thumb-nop.s: New test.
	* gas/arm/relax_branch_align.d: Expect a default NOP instruction.
	* gas/arm/vfp1_t2.d, gas/arm/vfp1xD_t2.d: Specify a CPU with
	Thumb-2.

	* ld-arm/arm-elf.exp (armelftests): Assemble Cortex-A8 tests with
	-mcpu=cortex-a8.

Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.426
diff -u -p -r1.426 tc-arm.c
--- gas/config/tc-arm.c	6 Jan 2010 15:02:44 -0000	1.426
+++ gas/config/tc-arm.c	13 Jan 2010 18:52:57 -0000
@@ -10623,7 +10623,7 @@ do_t_nop (void)
 	{
 	  /* PR9722: Check for Thumb2 availability before
 	     generating a thumb2 nop instruction.  */
-	  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
+	  if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
 	    {
 	      inst.instruction = THUMB_OP16 (inst.instruction);
 	      inst.instruction |= inst.operands[0].imm << 4;
Index: gas/testsuite/gas/arm/relax_branch_align.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/relax_branch_align.d,v
retrieving revision 1.1
diff -u -p -r1.1 relax_branch_align.d
--- gas/testsuite/gas/arm/relax_branch_align.d	2 Mar 2007 18:22:59 -0000	1.1
+++ gas/testsuite/gas/arm/relax_branch_align.d	13 Jan 2010 18:52:57 -0000
@@ -4,10 +4,10 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0+000 <[^>]+> bf00      	nop
+0+000 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
 0+002 <[^>]+> f000 8080 	beq.w	0+106 <[^>]*>
-0+006 <[^>]+> bf00      	nop
+0+006 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
 #...
-0+100 <[^>]+> bf00      	nop
+0+100 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
 0+102 <[^>]+> f47f af80 	bne.w	0+006 <[^>]*>
-0+106 <[^>]+> bf00      	nop
+0+106 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
Index: gas/testsuite/gas/arm/thumb-nop.d
===================================================================
RCS file: gas/testsuite/gas/arm/thumb-nop.d
diff -N gas/testsuite/gas/arm/thumb-nop.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/arm/thumb-nop.d	13 Jan 2010 18:52:57 -0000
@@ -0,0 +1,11 @@
+# name: Thumb NOP
+# objdump: -dr --prefix-addresses --show-raw-insn
+#
+# Both explicit nop and padding should not use Thumb-2 NOP for the
+# default CPU.
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0+000 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
+0+002 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
Index: gas/testsuite/gas/arm/thumb-nop.s
===================================================================
RCS file: gas/testsuite/gas/arm/thumb-nop.s
diff -N gas/testsuite/gas/arm/thumb-nop.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/arm/thumb-nop.s	13 Jan 2010 18:52:57 -0000
@@ -0,0 +1,5 @@
+	.text
+	.code 16
+	.p2align 2
+.foo:	
+	nop
Index: gas/testsuite/gas/arm/vfp1_t2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/vfp1_t2.d,v
retrieving revision 1.5
diff -u -p -r1.5 vfp1_t2.d
--- gas/testsuite/gas/arm/vfp1_t2.d	30 Jun 2009 11:57:05 -0000	1.5
+++ gas/testsuite/gas/arm/vfp1_t2.d	13 Jan 2010 18:52:58 -0000
@@ -1,6 +1,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn
 #name: Thumb-2 VFP Double-precision instructions
-#as: -mfpu=vfp
+#as: -mfpu=vfp -mcpu=arm1156t2f-s
 
 # Test the ARM VFP Double Precision instructions
 
Index: gas/testsuite/gas/arm/vfp1xD_t2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/vfp1xD_t2.d,v
retrieving revision 1.7
diff -u -p -r1.7 vfp1xD_t2.d
--- gas/testsuite/gas/arm/vfp1xD_t2.d	29 Jun 2009 08:08:15 -0000	1.7
+++ gas/testsuite/gas/arm/vfp1xD_t2.d	13 Jan 2010 18:52:58 -0000
@@ -1,6 +1,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn
 #name: Thumb-2 VFP Single-precision instructions
-#as: -mfpu=vfpxd
+#as: -mfpu=vfpxd -mcpu=arm1156t2f-s
 
 # Test the ARM VFP Single Precision instructions
 
Index: ld/testsuite/ld-arm/arm-elf.exp
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-arm/arm-elf.exp,v
retrieving revision 1.67
diff -u -p -r1.67 arm-elf.exp
--- ld/testsuite/ld-arm/arm-elf.exp	28 Dec 2009 18:55:16 -0000	1.67
+++ ld/testsuite/ld-arm/arm-elf.exp	13 Jan 2010 18:52:59 -0000
@@ -207,11 +207,13 @@ set armelftests {
      {{objdump -dr cortex-a8-fix-blx-rel-thumb.d}}
      "cortex-a8-fix-blx-rel-thumb"}
     {"Cortex-A8 erratum fix, relocate bl.w and far call"
-     "-EL -Ttext=0x00 --fix-cortex-a8 --defsym far_fn1=0x80000000 --defsym far_fn2=0x80000004  --defsym far_fn=0x7fff0000 --defsym _start=0" "-EL" {cortex-a8-far-1.s cortex-a8-far-2.s}
+     "-EL -Ttext=0x00 --fix-cortex-a8 --defsym far_fn1=0x80000000 --defsym far_fn2=0x80000004  --defsym far_fn=0x7fff0000 --defsym _start=0"
+     "-EL -mcpu=cortex-a8" {cortex-a8-far-1.s cortex-a8-far-2.s}
      {{objdump -dr cortex-a8-far.d}}
      "cortex-a8-far"}
     {"Cortex-A8 erratum fix, headers"
-     "-EL --fix-cortex-a8 -T cortex-a8-fix-hdr.t" "-EL" {cortex-a8-fix-hdr.s}
+     "-EL --fix-cortex-a8 -T cortex-a8-fix-hdr.t"
+     "-EL -mcpu=cortex-a8" {cortex-a8-fix-hdr.s}
      {{objdump -dr cortex-a8-fix-hdr.d}}
      "cortex-a8-fix-hdr"}
     {"Unwinding and -gc-sections" "-gc-sections" "" {gc-unwind.s}