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Hi, The attached patches add support for the XOP instructions, see: http://support.amd.com/us/Processor_TechDocs/43479.pdf that will be part of the upcoming AMD Orochi processor. I opened a PR http://sourceware.org/bugzilla/show_bug.cgi?id=10973 for a problem that we identified as part of OP_E_memory that also existed before in the FMA4 instructions. We discovered this problem in some of the 4 operands XOP tests. This bug should be fixed independently of the current patch adding support for XOP instructions. 2009-11-17 Sebastian Pop <sebastian.pop@amd.com> Quentin Neill <quentin.neill@amd.com> gas/ * config/tc-i386.c (cpu_arch): Added .xop. (build_vex_prefix): Handle xop08. (md_assemble): Don't special case the constant 3 for insns using MODRM. (build_modrm_byte): Handle vex2sources. (md_show_usage): Add xop. * doc/c-i386.texi: Document fma4 and xop. gas/testsuite/ * gas/i386/i386.exp: Run xop in 32-bit mode. Run x86-64-xop in 64-bit mode. * gas/i386/lwp.d: Update name of the testcase. * gas/i386/x86-64-xop.d: New. * gas/i386/x86-64-xop.s: New. * gas/i386/xop.d: New. * gas/i386/xop.s: New. opcodes/ * i386-dis.c (OP_Vex_2src_1): New. (OP_Vex_2src_2): New. (Vex_2src_1): New. (Vex_2src_2): New. (XOP_08): Added. (VEX_LEN_XOP_08_A0): Added. (VEX_LEN_XOP_08_A1): Added. (VEX_LEN_XOP_09_80): Added. (VEX_LEN_XOP_09_81): Added. (xop_table): Added an entry for XOP_08. Handle xop instructions. (vex_len_table): Added entries for VEX_LEN_XOP_08_A0, VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81. (get_valid_dis386): Handle XOP_08. (OP_Vex_2src): New. * i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS. (cpu_flags): Add CpuXOP. (opcode_modifiers): Add XOP08, Vex2Sources. * i386-opc.h (CpuXOP): Added. (i386_cpu_flags): Add cpuxop. (XOP08): Added. (Vex2Sources): Added. (i386_opcode_modifier): Add xop08, vex2sources. * i386-opc.tbl: Add entries for XOP instructions. Tested on x86-64-linux with make -k check and on simnow. Ok to commit? Thanks, Sebastian Pop -- AMD / Open Source Compiler Engineering / GNU Tools
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2009-11-17 Sebastian Pop <sebastian.pop@amd.com> Quentin Neill <quentin.neill@amd.com> gas/ * config/tc-i386.c (cpu_arch): Added .xop. (build_vex_prefix): Handle xop08. (md_assemble): Don't special case the constant 3 for insns using MODRM. (build_modrm_byte): Handle vex2sources. (md_show_usage): Add xop. * doc/c-i386.texi: Document fma4 and xop. opcodes/ * i386-dis.c (OP_Vex_2src_1): New. (OP_Vex_2src_2): New. (Vex_2src_1): New. (Vex_2src_2): New. (XOP_08): Added. (VEX_LEN_XOP_08_A0): Added. (VEX_LEN_XOP_08_A1): Added. (VEX_LEN_XOP_09_80): Added. (VEX_LEN_XOP_09_81): Added. (xop_table): Added an entry for XOP_08. Handle xop instructions. (vex_len_table): Added entries for VEX_LEN_XOP_08_A0, VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81. (get_valid_dis386): Handle XOP_08. (OP_Vex_2src): New. * i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS. (cpu_flags): Add CpuXOP. (opcode_modifiers): Add XOP08, Vex2Sources. * i386-opc.h (CpuXOP): Added. (i386_cpu_flags): Add cpuxop. (XOP08): Added. (Vex2Sources): Added. (i386_opcode_modifier): Add xop08, vex2sources. * i386-opc.tbl: Add entries for XOP instructions. Index: gas/config/tc-i386.c =================================================================== RCS file: /cvs/src/src/gas/config/tc-i386.c,v retrieving revision 1.403 diff -u -d -d -u -p -r1.403 tc-i386.c --- gas/config/tc-i386.c 5 Nov 2009 23:40:03 -0000 1.403 +++ gas/config/tc-i386.c 17 Nov 2009 21:51:25 -0000 @@ -641,6 +641,8 @@ static const arch_entry cpu_arch[] = CPU_FMA_FLAGS }, { ".fma4", PROCESSOR_UNKNOWN, CPU_FMA4_FLAGS }, + { ".xop", PROCESSOR_UNKNOWN, + CPU_XOP_FLAGS }, { ".lwp", PROCESSOR_UNKNOWN, CPU_LWP_FLAGS }, { ".movbe", PROCESSOR_UNKNOWN, @@ -2731,6 +2733,11 @@ build_vex_prefix (const insn_template *t m = 0x2; else if (i.tm.opcode_modifier.vex0f3a) m = 0x3; + else if (i.tm.opcode_modifier.xop08) + { + m = 0x8; + i.vex.bytes[0] = 0x8f; + } else if (i.tm.opcode_modifier.xop09) { m = 0x9; @@ -2968,8 +2975,11 @@ md_assemble (char *line) if (i.tm.opcode_modifier.vex) build_vex_prefix (t); - /* Handle conversion of 'int $3' --> special int3 insn. */ - if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) + /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 + instructions may define INT_OPCODE as well, so avoid this corner + case for those instructions that use MODRM. */ + if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3 + && !i.tm.opcode_modifier.modrm) { i.tm.base_opcode = INT3_OPCODE; i.imm_operands = 0; @@ -4877,11 +4887,12 @@ build_modrm_byte (void) { const seg_entry *default_seg = 0; unsigned int source, dest; - int vex_3_sources; + int vex_3_sources, vex_2_sources; /* The first operand of instructions with VEX prefix and 3 sources must be VEX_Imm4. */ vex_3_sources = i.tm.opcode_modifier.vex3sources; + vex_2_sources = i.tm.opcode_modifier.vex2sources; if (vex_3_sources) { unsigned int nds, reg; @@ -5265,7 +5276,41 @@ build_modrm_byte (void) else mem = ~0; - if (i.tm.opcode_modifier.vexlwp) + if (vex_2_sources) + { + if (operand_type_check (i.types[0], imm)) + i.vex.register_specifier = NULL; + else + { + /* VEX.vvvv encodes one of the sources when the first + operand is not an immediate. */ + if (i.tm.opcode_modifier.vexw0) + i.vex.register_specifier = i.op[0].regs; + else + i.vex.register_specifier = i.op[1].regs; + } + + /* Destination is a XMM register encoded in the ModRM.reg + and VEX.R bit. */ + i.rm.reg = i.op[2].regs->reg_num; + if ((i.op[2].regs->reg_flags & RegRex) != 0) + i.rex |= REX_R; + + /* ModRM.rm and VEX.B encodes the other source. */ + if (!i.mem_operands) + { + i.rm.mode = 3; + + if (i.tm.opcode_modifier.vexw0) + i.rm.regmem = i.op[1].regs->reg_num; + else + i.rm.regmem = i.op[0].regs->reg_num; + + if ((i.op[1].regs->reg_flags & RegRex) != 0) + i.rex |= REX_B; + } + } + else if (i.tm.opcode_modifier.vexlwp) { i.vex.register_specifier = i.op[2].regs; if (!i.mem_operands) @@ -8044,7 +8089,7 @@ md_show_usage (stream) ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\ vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\ clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\ - svme, abm, padlock, fma4, lwp\n")); + svme, abm, padlock, fma4, xop, lwp\n")); fprintf (stream, _("\ -mtune=CPU optimize for CPU, CPU is one of:\n\ i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ Index: gas/doc/c-i386.texi =================================================================== RCS file: /cvs/src/src/gas/doc/c-i386.texi,v retrieving revision 1.43 diff -u -d -d -u -p -r1.43 c-i386.texi --- gas/doc/c-i386.texi 6 Nov 2009 22:59:44 -0000 1.43 +++ gas/doc/c-i386.texi 17 Nov 2009 21:51:25 -0000 @@ -142,6 +142,8 @@ accept various extension mnemonics. For @code{ept}, @code{clflush}, @code{lwp}, +@code{fma4}, +@code{xop}, @code{syscall}, @code{rdtscp}, @code{3dnow}, @@ -922,7 +924,7 @@ supported on the CPU specified. The cho @item @samp{.ept} @tab @samp{.clflush} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} -@item @samp{.lwp} +@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @item @samp{.padlock} @end multitable Index: opcodes/i386-dis.c =================================================================== RCS file: /cvs/src/src/opcodes/i386-dis.c,v retrieving revision 1.208 diff -u -d -d -u -p -r1.208 i386-dis.c --- opcodes/i386-dis.c 6 Nov 2009 23:17:26 -0000 1.208 +++ opcodes/i386-dis.c 17 Nov 2009 21:51:25 -0000 @@ -117,6 +117,8 @@ static void CRC32_Fixup (int, int); static void OP_LWPCB_E (int, int); static void OP_LWP_E (int, int); static void OP_LWP_I (int, int); +static void OP_Vex_2src_1 (int, int); +static void OP_Vex_2src_2 (int, int); static void MOVBE_Fixup (int, int); @@ -360,6 +362,8 @@ fetch_data (struct disassemble_info *inf #define OPSUF { OP_3DNowSuffix, 0 } #define CMP { CMP_Fixup, 0 } #define XMM0 { XMM_Fixup, 0 } +#define Vex_2src_1 { OP_Vex_2src_1, 0 } +#define Vex_2src_2 { OP_Vex_2src_2, 0 } #define Vex { OP_VEX, vex_mode } #define Vex128 { OP_VEX, vex128_mode } @@ -1077,7 +1081,8 @@ enum enum { - XOP_09 = 0, + XOP_08 = 0, + XOP_09, XOP_0A }; @@ -1291,7 +1296,11 @@ enum VEX_LEN_3A7B_P_2, VEX_LEN_3A7E_P_2, VEX_LEN_3A7F_P_2, - VEX_LEN_3ADF_P_2 + VEX_LEN_3ADF_P_2, + VEX_LEN_XOP_08_A0, + VEX_LEN_XOP_08_A1, + VEX_LEN_XOP_09_80, + VEX_LEN_XOP_09_81 }; typedef void (*op_rtn) (int bytemode, int sizeflag); @@ -6379,7 +6388,7 @@ static const struct dis386 three_byte_ta }; static const struct dis386 xop_table[][256] = { - /* XOP_09 */ + /* XOP_08 */ { /* 00 */ { "(bad)", { XX } }, @@ -6402,7 +6411,7 @@ static const struct dis386 xop_table[][2 /* 10 */ { "(bad)", { XX } }, { "(bad)", { XX } }, - { REG_TABLE (REG_XOP_LWPCB) }, + { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -6531,29 +6540,46 @@ static const struct dis386 xop_table[][2 { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, + { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + /* 88 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* 88 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, + { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + /* 90 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* 90 */ + { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + /* 98 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, + { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + /* a0 */ + { VEX_LEN_TABLE (VEX_LEN_XOP_08_A0) }, + { VEX_LEN_TABLE (VEX_LEN_XOP_08_A1) }, + { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* 98 */ + { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, { "(bad)", { XX } }, + /* a8 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -6561,16 +6587,17 @@ static const struct dis386 xop_table[][2 { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* a0 */ { "(bad)", { XX } }, + /* b0 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, + { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, { "(bad)", { XX } }, - /* a8 */ + /* b8 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -6579,16 +6606,25 @@ static const struct dis386 xop_table[][2 { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* b0 */ + /* c0 */ + { "vprotb", { XM, Vex_2src_1, Ib } }, + { "vprotw", { XM, Vex_2src_1, Ib } }, + { "vprotd", { XM, Vex_2src_1, Ib } }, + { "vprotq", { XM, Vex_2src_1, Ib } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, + /* c8 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* b8 */ + { "vpcomb", { XM, Vex128, EXx, Ib } }, + { "vpcomw", { XM, Vex128, EXx, Ib } }, + { "vpcomd", { XM, Vex128, EXx, Ib } }, + { "vpcomq", { XM, Vex128, EXx, Ib } }, + /* d0 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -6597,7 +6633,7 @@ static const struct dis386 xop_table[][2 { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* c0 */ + /* d8 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -6606,7 +6642,7 @@ static const struct dis386 xop_table[][2 { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* c8 */ + /* e0 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -6615,29 +6651,293 @@ static const struct dis386 xop_table[][2 { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* d0 */ + /* e8 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, + { "vpcomub", { XM, Vex128, EXx, Ib } }, + { "vpcomuw", { XM, Vex128, EXx, Ib } }, + { "vpcomud", { XM, Vex128, EXx, Ib } }, + { "vpcomuq", { XM, Vex128, EXx, Ib } }, + /* f0 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* d8 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, + /* f8 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - /* e0 */ { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, + }, + /* XOP_09 */ + { + /* 00 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 08 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 10 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { REG_TABLE (REG_XOP_LWPCB) }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 18 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 20 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 28 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 30 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 38 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 40 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 48 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 50 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 58 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 60 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 68 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 70 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 78 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 80 */ + { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) }, + { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) }, + { "vfrczss", { XM, EXd } }, + { "vfrczsd", { XM, EXq } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 88 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* 90 */ + { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, + /* 98 */ + { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* a8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b0 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* b8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* c0 */ + { "(bad)", { XX } }, + { "vphaddbw", { XM, EXxmm } }, + { "vphaddbd", { XM, EXxmm } }, + { "vphaddbq", { XM, EXxmm } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vphaddwd", { XM, EXxmm } }, + { "vphaddwq", { XM, EXxmm } }, + /* c8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vphadddq", { XM, EXxmm } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* d0 */ + { "(bad)", { XX } }, + { "vphaddubw", { XM, EXxmm } }, + { "vphaddubd", { XM, EXxmm } }, + { "vphaddubq", { XM, EXxmm } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vphadduwd", { XM, EXxmm } }, + { "vphadduwq", { XM, EXxmm } }, + /* d8 */ + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "vphaddudq", { XM, EXxmm } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + /* e0 */ + { "(bad)", { XX } }, + { "vphsubbw", { XM, EXxmm } }, + { "vphsubwd", { XM, EXxmm } }, + { "vphsubdq", { XM, EXxmm } }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, @@ -9051,6 +9351,26 @@ static const struct dis386 vex_len_table { "vaeskeygenassist", { XM, EXx, Ib } }, { "(bad)", { XX } }, }, + /* VEX_LEN_XOP_08_A0 */ + { + { "vcvtph2ps", { XM, EXq, Ib } }, + { "vcvtph2ps", { XM, EXxmm, Ib } }, + }, + /* VEX_LEN_XOP_08_A1 */ + { + { "vcvtps2ph", { EXq, XM, Ib } }, + { "vcvtps2ph", { EXxmm, XM, Ib } }, + }, + /* VEX_LEN_XOP_09_80 */ + { + { "vfrczps", { XM, EXxmm } }, + { "vfrczps", { XM, EXymmq } }, + }, + /* VEX_LEN_XOP_09_81 */ + { + { "vfrczpd", { XM, EXxmm } }, + { "vfrczpd", { XM, EXymmq } }, + }, }; static const struct dis386 mod_table[][2] = { @@ -9945,6 +10265,9 @@ get_valid_dis386 (const struct dis386 *d { default: BadOp (); + case 0x8: + vex_table_index = XOP_08; + break; case 0x9: vex_table_index = XOP_09; break; @@ -13377,6 +13700,58 @@ OP_EX_VexReg (int bytemode, int sizeflag } static void +OP_Vex_2src (int bytemode, int sizeflag) +{ + if (modrm.mod == 3) + { + USED_REX (REX_B); + sprintf (scratchbuf, "%%xmm%d", rex & REX_B ? modrm.rm + 8 : modrm.rm); + oappend (scratchbuf + intel_syntax); + } + else + { + if (intel_syntax + && (bytemode == v_mode || bytemode == v_swap_mode)) + { + bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; + used_prefixes |= (prefixes & PREFIX_DATA); + } + OP_E (bytemode, sizeflag); + } +} + +static void +OP_Vex_2src_1 (int bytemode, int sizeflag) +{ + if (modrm.mod == 3) + { + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + } + + if (vex.w) + { + sprintf (scratchbuf, "%%xmm%d", vex.register_specifier); + oappend (scratchbuf + intel_syntax); + } + else + OP_Vex_2src (bytemode, sizeflag); +} + +static void +OP_Vex_2src_2 (int bytemode, int sizeflag) +{ + if (vex.w) + OP_Vex_2src (bytemode, sizeflag); + else + { + sprintf (scratchbuf, "%%xmm%d", vex.register_specifier); + oappend (scratchbuf + intel_syntax); + } +} + +static void OP_EX_VexW (int bytemode, int sizeflag) { int reg = -1; Index: opcodes/i386-gen.c =================================================================== RCS file: /cvs/src/src/opcodes/i386-gen.c,v retrieving revision 1.54 diff -u -d -d -u -p -r1.54 i386-gen.c --- opcodes/i386-gen.c 5 Nov 2009 23:40:05 -0000 1.54 +++ opcodes/i386-gen.c 17 Nov 2009 21:51:25 -0000 @@ -128,6 +128,8 @@ static initializer cpu_flag_init[] = "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" }, { "CPU_FMA4_FLAGS", "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA4" }, + { "CPU_XOP_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" }, { "CPU_LWP_FLAGS", "CpuLWP" }, { "CPU_MOVBE_FLAGS", @@ -298,6 +300,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuPCLMUL), BITFIELD (CpuFMA), BITFIELD (CpuFMA4), + BITFIELD (CpuXOP), BITFIELD (CpuLWP), BITFIELD (CpuLM), BITFIELD (CpuMovbe), @@ -358,9 +361,11 @@ static bitfield opcode_modifiers[] = BITFIELD (Vex0F), BITFIELD (Vex0F38), BITFIELD (Vex0F3A), + BITFIELD (XOP08), BITFIELD (XOP09), BITFIELD (XOP0A), BITFIELD (Vex3Sources), + BITFIELD (Vex2Sources), BITFIELD (VexImmExt), BITFIELD (SSE2AVX), BITFIELD (NoAVX), Index: opcodes/i386-opc.h =================================================================== RCS file: /cvs/src/src/opcodes/i386-opc.h,v retrieving revision 1.57 diff -u -d -d -u -p -r1.57 i386-opc.h --- opcodes/i386-opc.h 5 Nov 2009 23:40:05 -0000 1.57 +++ opcodes/i386-opc.h 17 Nov 2009 21:51:25 -0000 @@ -102,6 +102,8 @@ enum CpuFMA, /* FMA4 support required */ CpuFMA4, + /* XOP support required */ + CpuXOP, /* LWP support required */ CpuLWP, /* MOVBE Instuction support required */ @@ -170,6 +172,7 @@ typedef union i386_cpu_flags unsigned int cpupclmul:1; unsigned int cpufma:1; unsigned int cpufma4:1; + unsigned int cpuxop:1; unsigned int cpulwp:1; unsigned int cpumovbe:1; unsigned int cpuept:1; @@ -289,11 +292,15 @@ enum Vex0F38, /* insn has VEX 0x0F3A opcode prefix. */ Vex0F3A, + /* insn has XOP 0x08 opcode prefix. */ + XOP08, /* insn has XOP 0x09 opcode prefix. */ XOP09, /* insn has XOP 0x0A opcode prefix. */ XOP0A, - /* insn has VEX prefix with 3 soures. */ + /* insn has VEX prefix with 2 sources. */ + Vex2Sources, + /* insn has VEX prefix with 3 sources. */ Vex3Sources, /* instruction has VEX 8 bit imm */ VexImmExt, @@ -361,8 +368,10 @@ typedef struct i386_opcode_modifier unsigned int vex0f:1; unsigned int vex0f38:1; unsigned int vex0f3a:1; + unsigned int xop08:1; unsigned int xop09:1; unsigned int xop0a:1; + unsigned int vex2sources:1; unsigned int vex3sources:1; unsigned int veximmext:1; unsigned int sse2avx:1; Index: opcodes/i386-opc.tbl =================================================================== RCS file: /cvs/src/src/opcodes/i386-opc.tbl,v retrieving revision 1.67 diff -u -d -d -u -p -r1.67 i386-opc.tbl --- opcodes/i386-opc.tbl 5 Nov 2009 23:40:05 -0000 1.67 +++ opcodes/i386-opc.tbl 17 Nov 2009 21:51:25 -0000 @@ -2548,6 +2548,88 @@ vfnmsubsd, 4, 0x667f, None, 1, CpuFMA4, vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW1|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM, RegXMM } vfnmsubss, 4, 0x667e, None, 1, CpuFMA4, Modrm|Vex|Vex0F3A|VexNDS|VexW0|Vex3Sources|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexImmExt, {RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } +// XOP instructions + +vcvtph2ps, 3, 0xa0, None, 1, CpuXOP, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vcvtph2ps, 3, 0xa0, None, 1, CpuXOP, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM } +vcvtps2ph, 3, 0xa1, None, 1, CpuXOP, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, RegXMM, Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex } +vcvtps2ph, 3, 0xa1, None, 1, CpuXOP, Modrm|XOP08|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Imm8, RegYMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex } +vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vfrczpd, 2, 0x81, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM } +vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vfrczps, 2, 0x80, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM } +vfrczsd, 2, 0x83, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Qword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vfrczss, 2, 0x82, None, 1, CpuXOP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Dword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { RegYMM, Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM, RegYMM } +vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM, RegXMM } +vpcmov, 4, 0xa2, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex=2, { Ymmword|RegYMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegYMM, RegYMM, RegYMM } +vpcomb, 4, 0xcc, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomd, 4, 0xce, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomq, 4, 0xcf, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomub, 4, 0xec, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomud, 4, 0xee, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomuq, 4, 0xef, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomuw, 4, 0xed, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpcomw, 4, 0xcd, None, 1, CpuXOP, Modrm|XOP08|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Imm8, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vphaddbd, 2, 0xc2, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddbq, 2, 0xc3, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddbw, 2, 0xc1, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphadddq, 2, 0xcb, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddubd, 2, 0xd2, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddubq, 2, 0xd3, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddubw, 2, 0xd1, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddudq, 2, 0xdb, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphadduwd, 2, 0xd6, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphadduwq, 2, 0xd7, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddwd, 2, 0xc6, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphaddwq, 2, 0xc7, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphsubbw, 2, 0xe1, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphsubdq, 2, 0xe3, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vphsubwd, 2, 0xe2, None, 1, CpuXOP, Modrm|XOP09|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpmacsdd, 4, 0x9e, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdqh, 4, 0x9f, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdql, 4, 0x97, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdd, 4, 0x8e, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdqh, 4, 0x8f, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdql, 4, 0x87, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsswd, 4, 0x86, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssww, 4, 0x85, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacswd, 4, 0x96, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsww, 4, 0x95, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcsswd, 4, 0xa6, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcswd, 4, 0xb6, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpperm, 4, 0xa3, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM } +vpperm, 4, 0xa3, None, 1, CpuXOP, Modrm|XOP08|Vex3Sources|VexImmExt|VexNDS|VexW1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Xmmword|RegXMM|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM, RegXMM } +vprotb, 3, 0x90, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotb, 3, 0x90, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vprotb, 3, 0xc0, None, 1, CpuXOP, Modrm|XOP08|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotd, 3, 0x92, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotd, 3, 0x92, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vprotd, 3, 0xc2, None, 1, CpuXOP, Modrm|XOP08|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotq, 3, 0x93, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotq, 3, 0x93, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vprotq, 3, 0xc3, None, 1, CpuXOP, Modrm|XOP08|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotw, 3, 0x91, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vprotw, 3, 0x91, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vprotw, 3, 0xc1, None, 1, CpuXOP, Modrm|XOP08|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshab, 3, 0x98, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshab, 3, 0x98, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshad, 3, 0x9a, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshad, 3, 0x9a, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshaq, 3, 0x9b, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshaq, 3, 0x9b, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshaw, 3, 0x99, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshaw, 3, 0x99, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshlb, 3, 0x94, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshlb, 3, 0x94, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshld, 3, 0x96, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshld, 3, 0x96, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshlq, 3, 0x97, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshlq, 3, 0x97, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } +vpshlw, 3, 0x95, None, 1, CpuXOP, Modrm|XOP09|VexW0|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { RegXMM, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM } +vpshlw, 3, 0x95, None, 1, CpuXOP, Modrm|XOP09|VexW1|Vex2Sources|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|IgnoreSize|Vex, { Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM, RegXMM } + // LWP instructions llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|XOP09|VexW0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Reg16 }
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