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Re: [PATCH] Remove SSE5 support

From: "Jan Beulich" <JBeulich at novell dot com>
To: "dwarak rajagopal" <dwarak dot rajagopal at amd dot com>
Cc: <binutils at sourceware dot org>
Date: Mon, 08 Jun 2009 14:46:18 +0100
Subject: Re: [PATCH] Remove SSE5 support
References: <E7FB0F2BB5FEF242BB2929F02A12B8F303D60D@SAUSEXMB2.amd.com>

>>> "rajagopal, dwarak" <dwarak.rajagopal@amd.com> 22.05.09 00:16 >>>
>Hello,
>AMD announced the new instruction sets XOP, FMA4 and CVT16 instructions
>replacing the previously announced SSE5 instructions that will be part
>of future processors. The programmers guide for these instructions is
>located at http://support.amd.com/us/Processor_TechDocs/43479.pdf.

Is it really intended to add FMA support different from Intel's, yet using their
VEX opcode space rather than your XOP one?

If not, then what is the plan: 3- or 4-operand FMA? And if 3-operand, will
the XOP space specification get changed again (due to the resulting
differences in operand handling between VEX and XOP)?

Thanks, Jan

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