On Thu, 2009-02-19 at 12:19 +1030, Alan Modra wrote:
On Wed, Feb 18, 2009 at 01:40:18PM -0600, Edmar Wienskoski-RA8797 wrote:
! {"wait", X(31,62), X_MASK, E500MC, PPCNONE, {WC}},
X_MASK here has got to be wrong. X_MASK has 15 zero bits
corresponding to RA, RB and RT fields, so you'll disassemble a bunch
of (invalid) opcode bit patterns as "wait".
This is the change I'll soon be submitting as part of the POWER7 changes
(also ISA 2.06):
-{"wait", X(31,62), 0xffffffff, E500MC, {0}},
+{"waitrsv", X(31,62)|(1<<21), 0xffffffff, POWER7, {0}},
+{"waitimpl", X(31,62)|(2<<21), 0xffffffff, POWER7, {0}},
+{"wait", X(31,62), XWC_MASK, E500MC|POWER7, {WC}}
Peter