gas/ 2008-12-18 H.J. Lu * gas/config/tc-i386.c (_i386_insn): Add reverse_operand. (parse_insn): Handle ".r". (match_template): Handle reverse_operand. opcodes/ 2008-12-18 H.J. Lu * i386-dis.c (EbR): New. (EvR): Likewise. (EXxR): Likewise. (b_reverse_mode): Likewise. (v_reverse_mode): Likewise. (x_reverse_mode): Likewise. (STiR): Likewise. (Reverse_Fixup): Likewise. (v_mode): Updated. (w_mode): Likewise. (xmm_mode): Likewise. (dis386): Use EbR on movB. Use EvR on moveS. Use EXxR on movapX, movdqu, movdqa, vmovdqu, vmovdqa, vmovapX. (float_reg): Use STiR on fadd, fmul, fsub!M, fsubM, fdiv!M and fdivM. (OP_STi): Use Reverse_Fixup. (OP_E_register): Likewise. (OP_EX): Likewise. 2008-12-18 H.J. Lu * i386-opc.h (R): New. (Modrm): Updated. (i386_opcode_modifier): Add r. * i386-gen.c (opcode_modifiers): Add R. * i386-opc.tbl: Add R to fadd, fdiv, fsub, fsubr, mov, movapd, movaps, movdqa, movdqu, vmovapd, vmovaps, vmovdqa and vmovdqu. * i386-tbl.h: Regenerated. diff -upr -x .svn -x i386-tbl.h -x i386-init.h \ ../binutils/src binutils Only in binutils/bfd: REVISION Only in binutils/gas: ChangeLog.option diff -upr -x .svn -x i386-tbl.h -x i386-init.h ../binutils/src/gas/config/tc-i386.c binutils/gas/config/tc-i386.c --- ../binutils/src/gas/config/tc-i386.c 2008-12-08 10:41:30.000000000 -0800 +++ binutils/gas/config/tc-i386.c 2008-12-18 12:26:49.000000000 -0800 @@ -279,6 +279,9 @@ struct _i386_insn sib_byte sib; drex_byte drex; vex_prefix vex; + + /* Reverse operand in encoding. */ + unsigned int reverse_operand : 1; }; typedef struct _i386_insn i386_insn; @@ -2990,6 +2993,21 @@ parse_insn (char *line, char *mnemonic) if (!current_templates) { + if (mnem_p[-2] == '.') + { + /* Check if we should reverse operand in encoding. */ + if (mnem_p[-1] == 'r') + i.reverse_operand = 1; + else + goto check_suffix; + mnem_p[-2] = '\0'; + current_templates = hash_find (op_hash, mnemonic); + } + } + + if (!current_templates) + { +check_suffix: /* See if we can get a match by trimming off a suffix. */ switch (mnem_p[-1]) { @@ -3712,6 +3730,17 @@ match_template (void) && operand_type_equal (&i.types [0], &acc32) && operand_type_equal (&i.types [1], &acc32)) continue; + if (i.reverse_operand) + { + /* If we reverse operand in encoding, we either match + the next one or reverse direction of operands. */ + if (t->opcode_modifier.r) + continue; + else if (t->opcode_modifier.d + || t->opcode_modifier.floatd) + goto check_reverse; + } + case 3: case 4: case 5: @@ -3728,6 +3757,7 @@ match_template (void) if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) continue; +check_reverse: /* Try reversing direction of operands. */ overlap0 = operand_type_and (i.types[0], operand_types[1]); overlap1 = operand_type_and (i.types[1], operand_types[0]); Only in binutils/opcodes: ChangeLog.option diff -upr -x .svn -x i386-tbl.h -x i386-init.h ../binutils/src/opcodes/i386-dis.c binutils/opcodes/i386-dis.c --- ../binutils/src/opcodes/i386-dis.c 2008-12-18 14:48:23.000000000 -0800 +++ binutils/opcodes/i386-dis.c 2008-12-18 15:48:58.000000000 -0800 @@ -240,7 +240,9 @@ fetch_data (struct disassemble_info *inf #define XX { NULL, 0 } #define Eb { OP_E, b_mode } +#define EbR { OP_E, b_reverse_mode } #define Ev { OP_E, v_mode } +#define EvR { OP_E, v_reverse_mode } #define Ed { OP_E, d_mode } #define Edq { OP_E, dq_mode } #define Edqw { OP_E, dqw_mode } @@ -361,6 +363,7 @@ fetch_data (struct disassemble_info *inf #define EXd { OP_EX, d_mode } #define EXq { OP_EX, q_mode } #define EXx { OP_EX, x_mode } +#define EXxR { OP_EX, x_reverse_mode } #define EXxmm { OP_EX, xmm_mode } #define EXxmmq { OP_EX, xmmq_mode } #define EXymmq { OP_EX, ymmq_mode } @@ -412,10 +415,14 @@ fetch_data (struct disassemble_info *inf /* byte operand */ #define b_mode 1 +/* byte operand in reverse encoding */ +#define b_reverse_mode (b_mode + 1) /* operand size depends on prefixes */ -#define v_mode (b_mode + 1) +#define v_mode (b_reverse_mode + 1) +/* operand size depends on prefixes reverse encoding */ +#define v_reverse_mode (v_mode + 1) /* word operand */ -#define w_mode (v_mode + 1) +#define w_mode (v_reverse_mode + 1) /* double word operand */ #define d_mode (w_mode + 1) /* quad word operand */ @@ -424,8 +431,11 @@ fetch_data (struct disassemble_info *inf #define t_mode (q_mode + 1) /* 16-byte XMM or 32-byte YMM operand */ #define x_mode (t_mode + 1) +/* 16-byte XMM or 32-byte YMM operand in reverse encoding */ +#define x_reverse_mode (x_mode + 1) /* 16-byte XMM operand */ -#define xmm_mode (x_mode + 1) +/* 16-byte XMM operand */ +#define xmm_mode (x_reverse_mode + 1) /* 16-byte XMM or quad word operand */ #define xmmq_mode (xmm_mode + 1) /* 32-byte YMM or quad word operand */ @@ -1458,8 +1468,8 @@ static const struct dis386 dis386[] = { /* 88 */ { "movB", { Eb, Gb } }, { "movS", { Ev, Gv } }, - { "movB", { Gb, Eb } }, - { "movS", { Gv, Ev } }, + { "movB", { Gb, EbR } }, + { "movS", { Gv, EvR } }, { "movD", { Sv, Sw } }, { MOD_TABLE (MOD_8D) }, { "movD", { Sw, Sv } }, @@ -1640,7 +1650,7 @@ static const struct dis386 dis386_twobyt { "(bad)", { XX } }, /* 28 */ { "movapX", { XM, EXx } }, - { "movapX", { EXx, XM } }, + { "movapX", { EXxR, XM } }, { PREFIX_TABLE (PREFIX_0F2A) }, { PREFIX_TABLE (PREFIX_0F2B) }, { PREFIX_TABLE (PREFIX_0F2C) }, @@ -2686,8 +2696,8 @@ static const struct dis386 prefix_table[ /* PREFIX_0F7F */ { { "movq", { EM, MX } }, - { "movdqu", { EXx, XM } }, - { "movdqa", { EXx, XM } }, + { "movdqu", { EXxR, XM } }, + { "movdqa", { EXxR, XM } }, { "(bad)", { XX } }, }, @@ -3718,8 +3728,8 @@ static const struct dis386 prefix_table[ /* PREFIX_VEX_7F */ { { "(bad)", { XX } }, - { "vmovdqu", { EXx, XM } }, - { "vmovdqa", { EXx, XM } }, + { "vmovdqu", { EXxR, XM } }, + { "vmovdqa", { EXxR, XM } }, { "(bad)", { XX } }, }, @@ -6989,7 +6999,7 @@ static const struct dis386 vex_table[][2 { "(bad)", { XX } }, /* 28 */ { "vmovapX", { XM, EXx } }, - { "vmovapX", { EXx, XM } }, + { "vmovapX", { EXxR, XM } }, { PREFIX_TABLE (PREFIX_VEX_2A) }, { MOD_TABLE (MOD_VEX_2B) }, { PREFIX_TABLE (PREFIX_VEX_2C) }, @@ -10573,6 +10583,7 @@ static const unsigned char float_mem_mod #define ST { OP_ST, 0 } #define STi { OP_STi, 0 } +#define STiR { OP_STi, 1 } #define FGRPd9_2 NULL, { { NULL, 0 } } #define FGRPd9_4 NULL, { { NULL, 1 } } @@ -10631,14 +10642,14 @@ static const struct dis386 float_reg[][8 }, /* dc */ { - { "fadd", { STi, ST } }, - { "fmul", { STi, ST } }, + { "fadd", { STiR, ST } }, + { "fmul", { STiR, ST } }, { "(bad)", { XX } }, { "(bad)", { XX } }, - { "fsub!M", { STi, ST } }, - { "fsubM", { STi, ST } }, - { "fdiv!M", { STi, ST } }, - { "fdivM", { STi, ST } }, + { "fsub!M", { STiR, ST } }, + { "fsubM", { STiR, ST } }, + { "fdiv!M", { STiR, ST } }, + { "fdivM", { STiR, ST } }, }, /* dd */ { @@ -10724,6 +10735,14 @@ static char *fgrps[][8] = { }; static void +Reverse_Fixup (void) +{ + mnemonicendp[0] = '.'; + mnemonicendp[1] = 'r'; + mnemonicendp += 2; +} + +static void OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { @@ -10786,8 +10805,11 @@ OP_ST (int bytemode ATTRIBUTE_UNUSED, in } static void -OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +OP_STi (int bytemode, int sizeflag ATTRIBUTE_UNUSED) { + if (bytemode) + Reverse_Fixup (); + sprintf (scratchbuf, "%%st(%d)", modrm.rm); oappend (scratchbuf + intel_syntax); } @@ -11485,9 +11507,13 @@ OP_E_register (int bytemode, int sizefla if ((rex & REX_B)) reg += 8; + if (bytemode == b_reverse_mode || bytemode == v_reverse_mode) + Reverse_Fixup (); + switch (bytemode) { case b_mode: + case b_reverse_mode: USED_REX (0); if (rex) names = names8rex; @@ -11516,6 +11542,7 @@ OP_E_register (int bytemode, int sizefla bytemode = v_mode; /* FALLTHRU */ case v_mode: + case v_reverse_mode: case dq_mode: case dqb_mode: case dqd_mode: @@ -11523,7 +11550,9 @@ OP_E_register (int bytemode, int sizefla USED_REX (REX_W); if (rex & REX_W) names = names64; - else if ((sizeflag & DFLAG) || bytemode != v_mode) + else if ((sizeflag & DFLAG) + || (bytemode != v_mode + && bytemode != v_reverse_mode)) names = names32; else names = names16; @@ -12614,6 +12643,9 @@ OP_EX (int bytemode, int sizeflag) else add = 0; + if (bytemode == x_reverse_mode) + Reverse_Fixup (); + /* Skip mod/rm byte. */ MODRM_CHECK; codep++; diff -upr -x .svn -x i386-tbl.h -x i386-init.h ../binutils/src/opcodes/i386-gen.c binutils/opcodes/i386-gen.c --- ../binutils/src/opcodes/i386-gen.c 2008-12-08 10:41:28.000000000 -0800 +++ binutils/opcodes/i386-gen.c 2008-12-18 12:03:09.000000000 -0800 @@ -284,6 +284,7 @@ static bitfield opcode_modifiers[] = { BITFIELD (D), BITFIELD (W), + BITFIELD (R), BITFIELD (Modrm), BITFIELD (ShortForm), BITFIELD (Jump), diff -upr -x .svn -x i386-tbl.h -x i386-init.h ../binutils/src/opcodes/i386-opc.h binutils/opcodes/i386-opc.h --- ../binutils/src/opcodes/i386-opc.h 2008-09-15 09:37:35.000000000 -0700 +++ binutils/opcodes/i386-opc.h 2008-12-18 12:02:49.000000000 -0800 @@ -166,8 +166,10 @@ typedef union i386_cpu_flags #define D 0 /* set if operands can be words or dwords encoded the canonical way */ #define W (D + 1) +/* Can reverse operand in encoding. */ +#define R (W + 1) /* insn has a modrm byte. */ -#define Modrm (W + 1) +#define Modrm (R + 1) /* register is in low 3 bits of opcode */ #define ShortForm (Modrm + 1) /* special case for jump insns. */ @@ -284,6 +286,7 @@ typedef struct i386_opcode_modifier { unsigned int d:1; unsigned int w:1; + unsigned int r:1; unsigned int modrm:1; unsigned int shortform:1; unsigned int jump:1; diff -upr -x .svn -x i386-tbl.h -x i386-init.h ../binutils/src/opcodes/i386-opc.tbl binutils/opcodes/i386-opc.tbl --- ../binutils/src/opcodes/i386-opc.tbl 2008-11-03 11:38:38.000000000 -0800 +++ binutils/opcodes/i386-opc.tbl 2008-12-18 12:43:20.000000000 -0800 @@ -1199,9 +1199,9 @@ minps, 2, 0x5d, None, 1, CpuAVX, Modrm|V minps, 2, 0xf5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } minss, 2, 0xf35d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } minss, 2, 0xf30f5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -movaps, 2, 0x28, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movaps, 2, 0x28, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movaps, 2, 0xf28, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movaps, 2, 0xf28, None, 2, CpuSSE, R|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movaps, 2, 0xf29, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movhlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } movhlps, 2, 0xf12, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } @@ -1227,9 +1227,9 @@ movss, 2, 0xf310, None, 1, CpuAVX, Modrm movss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } movss, 2, 0xf30f10, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movss, 2, 0xf30f11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movups, 2, 0x10, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movups, 2, 0x10, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movups, 2, 0xf10, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movups, 2, 0xf10, None, 2, CpuSSE, R|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movups, 2, 0xf11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } mulps, 2, 0x59, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } mulps, 2, 0xf59, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } @@ -1375,9 +1375,9 @@ minpd, 2, 0x665d, None, 1, CpuAVX, Modrm minpd, 2, 0x660f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } minsd, 2, 0xf25d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } minsd, 2, 0xf20f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -movapd, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movapd, 2, 0x6628, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movapd, 2, 0x660f28, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movapd, 2, 0x660f28, None, 2, CpuSSE2, R|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movapd, 2, 0x660f29, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movhpd, 2, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } movhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } @@ -1399,9 +1399,9 @@ movsd, 2, 0xf210, None, 1, CpuAVX, Modrm movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } movsd, 2, 0xf20f10, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movsd, 2, 0xf20f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movupd, 2, 0x6610, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movupd, 2, 0x6610, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movupd, 2, 0x660f10, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movupd, 2, 0x660f10, None, 2, CpuSSE2, R|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movupd, 2, 0x660f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } mulpd, 2, 0x6659, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } mulpd, 2, 0x660f59, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } @@ -1455,13 +1455,13 @@ cvttps2dq, 2, 0xf35b, None, 1, CpuAVX, M cvttps2dq, 2, 0xf30f5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } maskmovdqu, 2, 0x66f7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM } maskmovdqu, 2, 0x660ff7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } -movdqa, 2, 0x666f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqa, 2, 0x666f, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movdqa, 2, 0x660f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqa, 2, 0x660f6f, None, 2, CpuSSE2, R|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movdqa, 2, 0x660f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqu, 2, 0xf36f, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, R|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX } movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM } @@ -2075,12 +2075,12 @@ vminps, 3, 0x5d, None, 1, CpuAVX, Modrm| vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM } vminsd, 3, 0xf25d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } vminss, 3, 0xf35d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM } -vmovapd, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovapd, 2, 0x6628, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovapd, 2, 0x6628, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -vmovapd, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } -vmovaps, 2, 0x28, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -vmovaps, 2, 0x28, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovaps, 2, 0x28, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovaps, 2, 0x28, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } // vmovd really shouldn't allow for 64bit operand (vmovq is the right @@ -2094,12 +2094,12 @@ vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegXMM, Qword|Reg64|BaseIndex|Disp8|Disp32|Disp32S } vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } -vmovdqa, 2, 0x666f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -vmovdqa, 2, 0x666f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovdqa, 2, 0x666f, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovdqa, 2, 0x666f, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } -vmovdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -vmovdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } +vmovdqu, 2, 0xf36f, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +vmovdqu, 2, 0xf36f, None, 1, CpuAVX, R|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM } vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM } vmovhlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }