Index: gas/testsuite/gas/i386/sse-noavx.d =================================================================== --- gas/testsuite/gas/i386/sse-noavx.d (revision 2309) +++ gas/testsuite/gas/i386/sse-noavx.d (working copy) @@ -15,7 +15,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: dd 08 fisttpll \(%eax\) [ ]*[a-f0-9]+: 0f f7 c7 maskmovq %mm7,%mm0 [ ]*[a-f0-9]+: 0f 01 c8 monitor %eax,%ecx,%edx +[ ]*[a-f0-9]+: f2 0f d6 c8 movdq2q %xmm0,%mm1 [ ]*[a-f0-9]+: 0f e7 10 movntq %mm2,\(%eax\) +[ ]*[a-f0-9]+: f3 0f d6 c8 movq2dq %mm0,%xmm1 [ ]*[a-f0-9]+: 0f 01 c9 mwait %eax,%ecx [ ]*[a-f0-9]+: 0f 38 1c c1 pabsb %mm1,%mm0 [ ]*[a-f0-9]+: 0f 38 1e c1 pabsd %mm1,%mm0 Index: gas/testsuite/gas/i386/sse-noavx.s =================================================================== --- gas/testsuite/gas/i386/sse-noavx.s (revision 2309) +++ gas/testsuite/gas/i386/sse-noavx.s (working copy) @@ -10,7 +10,9 @@ _start: fisttpll (%eax) maskmovq %mm7,%mm0 monitor + movdq2q %xmm0, %mm1 movntq %mm2,(%eax) + movq2dq %mm0, %xmm1 mwait pabsb %mm1,%mm0 pabsd %mm1,%mm0 Index: gas/testsuite/gas/i386/x86-64-sse-noavx.d =================================================================== --- gas/testsuite/gas/i386/x86-64-sse-noavx.d (revision 2309) +++ gas/testsuite/gas/i386/x86-64-sse-noavx.d (working copy) @@ -16,7 +16,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: dd 08 fisttpll \(%rax\) [ ]*[a-f0-9]+: 0f f7 c7 maskmovq %mm7,%mm0 [ ]*[a-f0-9]+: 0f 01 c8 monitor %rax,%rcx,%rdx +[ ]*[a-f0-9]+: f2 0f d6 c8 movdq2q %xmm0,%mm1 [ ]*[a-f0-9]+: 0f e7 10 movntq %mm2,\(%rax\) +[ ]*[a-f0-9]+: f3 0f d6 c8 movq2dq %mm0,%xmm1 [ ]*[a-f0-9]+: 0f 01 c9 mwait %rax,%rcx [ ]*[a-f0-9]+: 0f 38 1c c1 pabsb %mm1,%mm0 [ ]*[a-f0-9]+: 0f 38 1e c1 pabsd %mm1,%mm0 Index: gas/testsuite/gas/i386/x86-64-sse-noavx.s =================================================================== --- gas/testsuite/gas/i386/x86-64-sse-noavx.s (revision 2309) +++ gas/testsuite/gas/i386/x86-64-sse-noavx.s (working copy) @@ -11,7 +11,9 @@ _start: fisttpll (%rax) maskmovq %mm7,%mm0 monitor + movdq2q %xmm0, %mm1 movntq %mm2,(%rax) + movq2dq %mm0, %xmm1 mwait pabsb %mm1,%mm0 pabsd %mm1,%mm0 Index: opcodes/i386-tbl.h =================================================================== --- opcodes/i386-tbl.h (revision 2418) +++ opcodes/i386-tbl.h (working copy) @@ -13206,7 +13206,7 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, @@ -13218,7 +13218,7 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, Index: opcodes/i386-opc.tbl =================================================================== --- opcodes/i386-opc.tbl (revision 2418) +++ opcodes/i386-opc.tbl (working copy) @@ -1453,8 +1453,8 @@ movdqu, 2, 0xf36f, None, 1, CpuAVX, Modr movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegMMX } -movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, RegXMM } +movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX } +movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM } pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuludq, 2, 0x660ff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuludq, 2, 0xff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }